CN112148659B - Data transmission circuit - Google Patents
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- CN112148659B CN112148659B CN202011004948.6A CN202011004948A CN112148659B CN 112148659 B CN112148659 B CN 112148659B CN 202011004948 A CN202011004948 A CN 202011004948A CN 112148659 B CN112148659 B CN 112148659B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0042—Universal serial bus [USB]
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Abstract
The application provides a data transmission circuit, relates to the circuit design field, has reached the purpose of avoiding the wasting of resources. The data transmission circuit includes a main communication circuit and a sideband circuit connected with the main communication circuit, the sideband circuit including: the register module is electrically connected with the main communication circuit and used for receiving communication data written into the sideband circuit by the main communication circuit; the sideband input module is connected with other circuits and is used for receiving input data input into the sideband circuit by other circuits; the data processing module is electrically connected with the sideband input module, electrically connected with the register module and used for performing data interaction with the register module based on input data; and the sideband output module is electrically connected with the data processing module and is used for outputting the output data acquired by the data processing module from the register module, so that the purpose of data transmission by using a sideband circuit to replace a main communication circuit is realized, and the resource waste can be avoided to a certain extent.
Description
Technical Field
The present application relates to the field of circuit design, and in particular, to a data transmission circuit.
Background
Universal Serial Bus (usb) is used to standardize the connection and communication between computer and external devices. USB4 is the latest protocol version at present, with higher data transfer rates and more compatibility.
The USB4 protocol standard has a main communication channel, which has a high-speed data transmission channel and can efficiently transmit data, but in the use process of the USB4 protocol standard, sometimes a low data transmission rate can meet the requirement, and there is a possibility that resources are wasted by always using the high-speed main communication channel to transmit data.
Disclosure of Invention
It is an object of the present application to alleviate the problem of resource waste to some extent.
In order to solve the above problem, the present application provides a data transmission circuit including a main communication circuit and a sideband circuit connected to the main communication circuit, the sideband circuit including: the register module is electrically connected with the main communication circuit and used for receiving communication data written into the sideband circuit by the main communication circuit; the sideband input module is connected with other circuits and used for receiving input data input into the sideband circuit by the other circuits; the data processing module is electrically connected with the sideband input module, electrically connected with the register module and used for performing data interaction with the register module based on the input data; and the sideband output module is electrically connected with the data processing module and is used for outputting the output data acquired by the data processing module from the register module.
In one embodiment of the present application, the sideband input module comprises: a sideband input submodule for receiving the input data; and the decoding submodule is electrically connected with the sideband input submodule, is electrically connected with the data processing module and is used for decoding the input data and transmitting the decoded input data to the data processing module.
In one embodiment of the present application, the data processing module further includes: and the register arbitration submodule is electrically connected with the sideband input module, electrically connected with the register module, and used for judging the sequence of the input data entering the register module and also used for judging the sequence of the output data outputting the register module.
In one embodiment of the present application, the data processing module further includes: and the output cache submodule is electrically connected with the register arbitration submodule and the sideband output module and is used for caching the output data and transmitting the output data to the sideband output module.
In an embodiment of the present application, the output buffer submodule is electrically connected to the main communication circuit, and is configured to forward the main communication data output by the main communication circuit.
In one embodiment of the present application, the data processing module is further electrically connected to the primary communication circuit, the data processing module further comprising: and the data distribution submodule is connected with the sideband input module, is electrically connected with the register arbitration submodule, is electrically connected with the main communication circuit, is electrically connected with the output cache submodule and is used for inputting the input data into the register arbitration module or the main communication circuit or the output cache submodule.
In an embodiment of the application, the data distribution sub-module is further configured to determine whether the format of the input data is incorrect, and send a determination result to the output cache sub-module.
In one embodiment of the present application, the other circuit includes a first other circuit and a second other circuit, and the number of the sideband input modules is two, and the two sideband input modules correspond to the first other circuit and the second other circuit respectively; the two sideband output modules correspond to the first other circuit and the second other circuit respectively; the number of the data distribution sub-modules is two, and the two data distribution sub-modules respectively correspond to the first other circuit and the second other circuit; the number of the output cache sub-modules is two, and the two output cache sub-modules respectively correspond to the first other circuit and the second other circuit.
In an embodiment of the present application, each of the data distribution sub-modules is electrically connected to two of the output cache sub-modules, and is configured to determine an output cache sub-module of the two output cache sub-modules, which receives the input data.
In one embodiment of the present application, the sideband output module comprises: the encoding submodule is electrically connected with the data processing module and is used for encoding the output data or the main communication data to obtain encoded data; and the sideband output sub-module is electrically connected with the coding sub-module and is used for outputting the coded data.
According to the technical scheme, the method has at least the following advantages and positive effects:
the data transmission circuit comprises a main communication circuit and a sideband circuit connected with the main communication circuit, wherein the sideband circuit comprises a register module, a sideband input module, a data processing module and a sideband output module, the register module is electrically connected with the main communication circuit and is used for receiving communication data written into the sideband circuit by the main communication circuit, the sideband input module is connected with other circuits and is used for receiving input data input into the sideband circuit by other circuits, the data processing module is electrically connected with the sideband input module and is electrically connected with the register module and used for performing data interaction with the register module based on the input data so as to write data into the register module or read data from the register module based on the input data, the sideband output module is electrically connected with the data processing module and is used for outputting output data acquired by the data processing module from the register module, the output data acquired from the register module may be communication data written into the sideband circuit by the main communication circuit, and the output data may also be input data input into the sideband circuit by other circuits, so that the purpose of transmitting data in the main communication circuit or other circuits connected with the sideband circuit by using the sideband circuit instead of the main communication circuit is achieved, and resource waste possibly caused by data transmission by using the main communication circuit can be avoided to a certain extent.
Drawings
FIG. 1 schematically illustrates a data transmission circuit according to an embodiment of the present application;
FIG. 2 schematically illustrates a data transmission circuit configuration of an embodiment of the present application;
FIG. 3 schematically illustrates a sideband circuit structure of the present application;
FIG. 4 is a schematic diagram of the sideband module function module structure and data flow diagram of the present application;
FIG. 5 is a schematic diagram illustrating the flow of data between a data processing module and an output buffer of the present application;
FIG. 6 is a schematic diagram illustrating the data flow between the data processing module and the decision module of the present application;
fig. 7 schematically shows a sideband module secondary structure and data flow diagram of the present application.
Reference numerals:
10. sideband circuitry, 11, register module, 12, sideband input module, 13, data processing module, 14, sideband output module, 15, other circuitry, 151, second other circuitry, 152, second other circuitry;
20. a 0 side component, 21, a 1 side component, 22, a re-timer, 23, a sideband module of the re-timer, 24 and a data processing module;
40. reading and writing invalid feedback of an SB register of the re-timer component by error, 41, reading and writing data or feedback of the SB register of the re-timer component in a correct format, 42, a command for reading a 1 side adjacent register required by the Lane module, 43, forwarding data sent by a judgment 0 module, 44 and an output buffer 1 module;
50. invalid feedback of the SB register of the re-timer component is wrongly read and written, the 51 Lane module sends out data received after reading an adjacent register, 52, read-write SB register data with a correct format, 53, data to be forwarded, 54 and a judgment 0 module.
Detailed Description
Exemplary embodiments that embody features and advantages of the present application will be described in detail in the following description. It is to be understood that the present application is capable of various modifications in various embodiments without departing from the scope of the application, and that the description and drawings are to be taken as illustrative and not restrictive in character.
The present embodiment provides a data transmission circuit including a main communication circuit and a sideband circuit 10 connected to the main communication circuit.
In one embodiment of the present application, as shown in fig. 1, the sideband circuitry 10 includes a register module 11, a sideband input module 12, a data processing module 13, and a sideband output module 14. Fig. 1 schematically shows a data transmission circuit structure of an embodiment of the present application. The register module 11 is electrically connected with the main communication circuit and used for receiving communication data written into the sideband circuit 10 by the main communication circuit, the sideband input module 12 is connected with the other circuits 15 and used for receiving input data input into the sideband circuit 10 by the other circuits 15, the data processing module 13 is electrically connected with the sideband input module 12 and electrically connected with the register module 11 and used for carrying out data interaction with the register module 11 based on the input data, and the sideband output module 14 is electrically connected with the data processing module 13 and used for outputting output data acquired by the data processing module 13 from the register module 11.
In one embodiment of the present application, the register module 11 is electrically connected to the main communication circuit and is configured to receive and store communication data written by the main communication circuit to the sideband circuit 10, where the communication data may be an instruction issued by the main communication circuit to the sideband circuit 10, and the main communication circuit may control connection or disconnection of the sideband circuit 10.
In an embodiment of the application, the output of the sideband circuitry 10 may be connected to further circuitry 15, and the communication data may be data sent by the main communication circuitry to the further circuitry 15, or may be data sent by the main communication circuitry to the further circuitry 15 in response to a read instruction sent by the further circuitry 15. The communication data may also send instructions to the other circuitry 15 to read data from the other circuitry 15 for data interaction with the main communication circuitry and the other circuitry 15 via the sideband circuitry 10.
In one embodiment of the present application, the register module 11 may be a static base register (SB register).
In an embodiment of the present application, the sideband input module 12 may include a sideband input sub-module and a decoding sub-module, the sideband input sub-module is configured to receive input data, and the decoding sub-module is electrically connected to the sideband input sub-module and electrically connected to the data processing module 13, and is configured to decode the input data and transmit the decoded input data to the data processing module 13.
In an embodiment of the present application, the input data may be read/write instructions and read/write contents input to the sideband circuit 10 by the other circuits 15, so that data may be read from the register module 11 based on the input data, and data may also be read from and written to the register module 11 based on the input data.
In one embodiment of the present application, the sideband input module 12 may be electrically connected to the primary communication circuitry to write input data to the primary communication circuitry.
In one embodiment of the present application, the input data may be a master communication circuit control instruction, and the master communication circuit control instruction is transmitted to the master communication circuit to enable control of the master communication circuit.
In one embodiment of the present application, the control instruction may be a master communication circuit initialization, a master communication circuit connection establishment, whether the master communication circuit enters a sleep mode, whether the master communication circuit is active, whether the master communication circuit is disconnected, and the like.
In one embodiment of the present application, the sideband input sub-module and the decoding sub-module may each be connected to a primary communication circuit to transmit input data to the primary communication circuit.
In an embodiment of the present application, the data processing module 13 may include a register arbitration sub-module, electrically connected to the sideband input module 12, electrically connected to the register module 11, and configured to determine an order of input data entering the register module 11 and an order of output data outputting the register module 11, so as to implement processing of a data transmission order.
In an embodiment of the present application, an order of data entering or outputting the register may be determined according to a maximum race condition, and if which data source has the most data input to the register at the same time among the multiple data sources that input data to the register, the data from the data source is first stored in the register according to the input order; when the register outputs data to a plurality of data receiving ends at the same time, the register receives the output data to which data receiving end the output data is the most at the same time, and the register receives the output data to the receiving end firstly.
In one embodiment of the present application, the order of data entering or outputting the register may be determined according to the maximum length of a single data message, and the data message with the data message length exceeding the capacity of the output buffer submodule is preferentially output.
In one embodiment of the present application, the order of input or output may be determined according to the maximum race condition and the maximum length of the single data message, so as to ensure that the input data is not covered due to insufficient buffer capacity, because the sideband input data is input at a low speed but does not wait.
In one embodiment of the present application, the maximum length of a single data message and the maximum number of inputs simultaneously input to the same register may be multiplied, and the storage space of the register module 11 is larger than the result of the multiplication.
In an embodiment of the present application, the data processing module 13 further includes an output buffer sub-module electrically connected to the register arbitration sub-module and electrically connected to the sideband output module 14, and configured to buffer and transmit the output data to the sideband output module 14.
In an embodiment of the present application, the output cache submodule may output data having the same identifier in the output cache submodule at a time according to the identifier of the output data, so as to implement asynchronous transmission of the data.
In an embodiment of the present application, the output cache submodule may split a piece of data according to data characteristics and then output the split piece of data for multiple times, so as to implement asynchronous transmission of the data.
In one embodiment of the present application, the output buffer submodule may be electrically connected to the main communication circuit, and configured to forward the main communication data output by the main communication circuit.
In one embodiment of the present application, the data processing module 13 may be electrically connected to a main communication circuit, the main communication circuit may be connected to a register arbitration submodule in the data processing module 13, and the register arbitration submodule may receive communication data sent by the main communication circuit to the register module 11 to determine an order of the communication data entering the register module 11.
In one embodiment of the present application, the data processing module 13 may include a data distribution sub-module, connected to the sideband input module 12, electrically connected to the register arbitration sub-module, electrically connected to the main communication circuit, and electrically connected to the output buffer sub-module, for inputting input data into the register arbitration sub-module or the main communication circuit or the output buffer sub-module.
In one embodiment of the present application, data characteristics of input data may be obtained, and the input data may be input to the register arbitration module or the main communication circuit or the output buffer submodule according to the data characteristics.
In one embodiment of the present application, the data characteristic of the input data may be a target address of the input data.
In an embodiment of the present application, the data distribution submodule may be configured to determine whether the format of the input data is incorrect, and send the determination result to the output cache submodule, and the output cache submodule may send the determination result to the other circuit 15 of the input data connected to the sideband output module 14.
In one embodiment of the present application, the determination result may include an error reason.
In an embodiment of the present application, the sideband output module 14 may include an encoding sub-module and a sideband output sub-module, and the encoding sub-module is electrically connected to the data processing module 13 and is configured to encode the output data or the main communication data to obtain encoded data; the sideband output sub-module is electrically connected with the encoding sub-module and used for outputting the encoded data and transmitting the encoded data to other circuits 15 connected with the sideband output module 14.
In one embodiment of the present application, the sideband output module 14 may be electrically connected with the main communication circuit for forwarding data sent by the main communication circuit to other circuits 15 connected with the sideband output module 14, and both the encoding sub-module and the sideband output sub-module may be electrically connected with the main communication circuit so that the other circuits 15 may receive data before encoding or data after encoding.
In one embodiment of the application, the sideband output module 14 can forward a read instruction sent by the main communication circuit to the other circuit 15, and the sideband output module 14 can also forward data sent by the main communication circuit to the other circuit 15 in response to the read instruction of the other circuit 15.
In an embodiment of the present application, as shown in fig. 2, fig. 2 schematically shows a schematic diagram of a data transmission circuit structure of an embodiment of the present application, the other circuit 15 may include a first other circuit 151 and a second other circuit 152, two sideband input modules 12 are provided, and the two sideband input modules 12 correspond to the first other circuit 151 and the second other circuit 152 respectively; the number of the sideband output modules 14 is two, and the two sideband output modules 14 correspond to the first other circuit 151 and the second other circuit 152 respectively; the number of the data distribution sub-modules is two, and the two data distribution sub-modules respectively correspond to the first other circuit 151 and the second other circuit 152; there are two output buffer sub-modules, which correspond to the first further circuit 151 and the second further circuit 152, respectively.
In an embodiment of the present application, each data distribution submodule is electrically connected to two output cache submodules, and is configured to determine an output cache submodule, which receives input data, of the two output cache submodules.
The data transmission circuit comprises a main communication circuit and a sideband circuit 10 connected with the main communication circuit, wherein the sideband circuit 10 comprises a register module 11, a sideband input module 12, a data processing module 13 and a sideband output module 14, the register module 11 is electrically connected with the main communication circuit and is used for receiving communication data written into the sideband circuit 10 by the main communication circuit, the sideband input module 12 is connected with other circuits 15 and is used for receiving input data input into the sideband circuit 10 by other circuits 15, the data processing module 13 is electrically connected with the sideband input module 12 and is electrically connected with the register module 11 and is used for performing data interaction with the register module 11 based on the input data so as to write data into the register module 11 or read data from the register module 11 based on the input data, and the sideband output module 14 is electrically connected with the data processing module 13, the scheme is used for outputting output data acquired by the data processing module 13 from the register module 11, the output data acquired from the register module 11 may be communication data written by a main communication circuit into the sideband circuit 10, and the output data may also be input data input by other circuits 15 into the sideband circuit 10, so that the purpose of using the sideband circuit 10 to replace the main communication circuit to transmit data in the main communication circuit or other circuits 15 connected with the sideband circuit 10 is achieved, resource waste possibly caused by using the main communication circuit to transmit data can be avoided to a certain extent, the concentration and the reusability of module functions are considered, and the design can be quickly achieved according to the scheme.
In one embodiment of the present application, the data transfer circuit of the present application may be applied to a router of the USB4 standard protocol and a retimer (re-timer), which is a connection between USB4 ports of two interconnected routers, providing initial communication and setup functions. A USB4 connection may have a maximum of 6 retimers added to it.
In one embodiment of the present application, when the data transmission circuit of the present application is applied to a re-timer (re-timer) of the USB4 standard protocol, the data transmitted by the data transmission circuit may include forwarding of link connection parameters, forwarding of other information, and forwarding after counting and marking re-timer components.
In one embodiment of the present application, the link connection parameter may be a parameter for setting a re-timer of the router, including an error correction mode, whether other speeds are supported, and the like.
In an embodiment of the application, a plurality of re-timers can be added in the USB4 link, each re-timer can be marked with a number, a plurality of re-timer components can be added in the statistical link later, and data of a certain re-timer can be forwarded independently according to needs.
Fig. 3 is a schematic diagram of a sideband circuit structure of the present application, and fig. 3 shows the connection of the sideband module of the re-timer and the adjacent components. In the USB4 connection, data has a flow direction, and for the middle component, there are two directions of data, which can come from the 0-side component 20 and the 1-side component 21. In FIG. 2, the 0-side component 20 is a component in one data direction, the 1-side component 21 is a component in another direction, and the 0-side component 20 and the 1-side component 21 may be other re-timers or routers. The re-timer22 comprises Lane module of the main communication circuit re-timer and sideband module 23 of the sideband circuit re-timer of the auxiliary function, the sideband module 23 of the re-timer can perform data interaction with the sideband module of the 0-side component 20 and the sideband module of the 1-side component 21.
Fig. 4 schematically outputs the structure of the sideband module function module and the data flow diagram of the present application, and fig. 4 shows the specific structure of the sideband module 23 of the re-timer, in which the sideband input module, the sideband output module, the decoding module and the encoding module are all the same kind of function module instantiated twice because the data transmission functions in both directions are identical. The sideband module 23 of the re-timer in fig. 4 includes an SB register, a data processing module 24, a sideband input 0 module, a decoding 0 module, an encoding 0 module, a sideband output 0 module, a sideband input 1 module, a decoding 1 module, an encoding 1 module, and a sideband output 1 module, wherein the sideband output 0 module and the sideband output 0 module are connected to a 0-side component, and the sideband output 1 module are connected to a 1-side component. The sideband input 0 module and the sideband input 1 module provide connection information and data information to the Lane module of the component to control the disconnection or connection signal underlying the Lane module of the component. The decode 0 module and decode 1 module will provide connection information to the Lane module of the component. The data processing block 24 performs bi-directional data flow with the Lane block of the component for SB register related data. The data processing block 24 reads and writes data from/to the SB register.
In an embodiment of the present application, the data processing module 24 may be further subdivided into several small modules, including a decision 0 module (corresponding to the data distribution submodule in the sideband circuit in the above-mentioned embodiment), a decision 1 module (corresponding to the data distribution submodule in the sideband circuit in the above-mentioned embodiment), a read-write register arbitration module (corresponding to the register arbitration submodule in the sideband circuit), an output buffer 0 module (corresponding to the output buffer submodule in the sideband circuit), and an output buffer 1 module (corresponding to the output buffer submodule in the sideband circuit in the above-mentioned embodiment), as shown in fig. 5, fig. 5 schematically illustrates an internal and output buffer data flow diagram of a data processing module of the present application. There is complex data processing within the module. Fig. 5 purposely indicates the data flow direction of the same output buffer, which is only a part of the data flow presentation inside the data processing module 24.
Referring to fig. 5, the data processing module 24 is to receive four data inputs in the output buffer 1 module 44, and the data processing module 24 has two functions of buffering and arbitration. The capacity of the output buffer 1 module 44 is designed according to the maximum race condition and the maximum length of the single data message, so as to ensure that the input data is not covered due to insufficient buffer capacity, because the sideband input data is input at a low speed but is not waiting. The four data inputs come from: the invalid feedback 40 of the SB register of the re-timer component is wrongly read and written; the data or feedback 41 of the SB register of the re-timer component is read and written in the correct format; a command 42 for reading the adjacent register on the 1 side required by the Lane module; decision 0 block sends forwarding data 43. Similarly, the output buffer 0 module handles similar data flow.
In one embodiment of the present application, fig. 6 schematically illustrates a data flow diagram of the data processing module 14 and the decision module of the present application, and referring to fig. 6, four flow diagrams can be generated after a sideband information is input into the decision 0 module 54. The decision 1 module on the other side also processes similar data streams, and the four data streams are respectively: the invalid feedback 50 of the SB register of the re-timer component is wrongly read and written (as 40 on the other side); the Lane module sends out data 51 received after reading the adjacent register; read-write SB register data 52 in the correct format; data to be forwarded 53.
In an embodiment of the present application, a final secondary structure diagram and data flow of the sideband module function refer to fig. 7, and fig. 7 schematically illustrates a sideband module secondary structure and data flow diagram of the present application, a sideband input 0 module, a sideband input 1 module, a sideband output 0 module, a sideband output 1 module, a decoding 0 module, a decoding 1 module, an encoding 0 module, an encoding 1 module, an SB register, a register arbitration module, a decision 0 module, a decision 1 module, an output buffer 0 module, and an output buffer 1 module.
Referring to fig. 7, the Lane module may receive data input by the sideband input 0 module, the Lane module may receive data input by the decode 0 module, the Lane module may receive data input by the decision 1 module, the Lane module may receive data input by the decode 1 module, the Lane module may receive data input by the sideband input 1 module, the Lane module may send data to the output buffer 0 module, the Lane module may send data to the output buffer 1 module, and the Lane module may send data to the SB register. The predicate 0 module may send data to the register arbitration module, the predicate 0 module may send data to the output buffer 0 module, and the predicate 0 module may send data to the output buffer 1 module. The decision 1 module may send data to the register arbitration module, the decision 1 module may send data to the output buffer 0 module, and the decision 1 module may send data to the output buffer 1 module. The register arbitration module can send data to the SB register, the register arbitration module can send data to the output cache 0 module, the register arbitration module can send data to the output cache 1 module, and the register arbitration module can receive the data sent by the SB register.
The application relates to a sideband circuit design scheme of re-timer based on USB4 protocol. This sideband functionality and requirements are not available with previous versions of the USB protocol. The scheme designs a submodule with centralized functions, which is convenient for multiplexing, and extracts definite data stream from the requirement to realize the part of functions. According to the scheme, the whole sideband structure can be built rapidly from 0 to 1, so that the sideband function is designed rapidly and clearly, and then the whole USB4 system building is completed by combining the upgraded Lane module.
While the present application has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present application may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.
Claims (10)
1. A data transmission circuit, comprising: a primary communication circuit and a sideband circuit connected with the primary communication circuit, the sideband circuit comprising:
the register module is electrically connected with the main communication circuit and used for receiving communication data written into the sideband circuit by the main communication circuit;
the sideband input module is connected with other circuits and used for receiving input data input into the sideband circuit by the other circuits;
the data processing module is electrically connected with the sideband input module, electrically connected with the register module and used for performing data interaction with the register module based on the input data;
and the sideband output module is electrically connected with the data processing module and is used for outputting the output data acquired by the data processing module from the register module.
2. The data transmission circuit of claim 1, wherein the sideband input module comprises:
a sideband input submodule for receiving the input data;
and the decoding submodule is electrically connected with the sideband input submodule, is electrically connected with the data processing module and is used for decoding the input data and transmitting the decoded input data to the data processing module.
3. The data transmission circuit of claim 1, wherein the data processing module further comprises:
and the register arbitration submodule is electrically connected with the sideband input module, electrically connected with the register module, and used for judging the sequence of the input data entering the register module and also used for judging the sequence of the output data outputting the register module.
4. The data transmission circuit of claim 3, wherein the data processing module further comprises:
and the output cache submodule is electrically connected with the register arbitration submodule and the sideband output module and is used for caching the output data and transmitting the output data to the sideband output module.
5. The data transmission circuit of claim 4,
the output cache submodule is electrically connected with the main communication circuit and used for forwarding the main communication data output by the main communication circuit.
6. The data transmission circuit of claim 5, wherein the data processing module is further electrically connected to the primary communication circuit, the data processing module further comprising:
and the data distribution submodule is connected with the sideband input module, is electrically connected with the register arbitration submodule, is electrically connected with the main communication circuit, is electrically connected with the output cache submodule and is used for inputting the input data into the register arbitration module or the main communication circuit or the output cache submodule.
7. The data transmission circuit of claim 6,
the data distribution submodule is also used for judging whether the format of the input data is wrong or not and sending the judgment result to the output cache submodule.
8. The data transmission circuit according to claim 6, wherein the other circuit includes a first other circuit and a second other circuit,
the two sideband input modules correspond to the first other circuit and the second other circuit respectively;
the two sideband output modules correspond to the first other circuit and the second other circuit respectively;
the number of the data distribution sub-modules is two, and the two data distribution sub-modules respectively correspond to the first other circuit and the second other circuit;
the number of the output cache sub-modules is two, and the two output cache sub-modules respectively correspond to the first other circuit and the second other circuit.
9. The data transmission circuit of claim 8,
each data distribution submodule is electrically connected with the two output cache submodules and is used for judging the output cache submodule which receives the input data in the two output cache submodules.
10. The data transmission circuit of claim 5, wherein the sideband output module comprises:
the encoding submodule is electrically connected with the data processing module and is used for encoding the output data or the main communication data to obtain encoded data;
and the sideband output sub-module is electrically connected with the coding sub-module and is used for outputting the coded data.
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| CN101515261A (en) * | 2008-02-19 | 2009-08-26 | Arm有限公司 | Data transfer between devices within an integrated circuit |
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| CN209980248U (en) * | 2018-03-08 | 2020-01-21 | 意法半导体股份有限公司 | Circuit and electronic device |
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| CN101515261A (en) * | 2008-02-19 | 2009-08-26 | Arm有限公司 | Data transfer between devices within an integrated circuit |
| CN103748826A (en) * | 2011-09-06 | 2014-04-23 | Nds有限公司 | Preventing data extraction by side-channel attack |
| CN104216866A (en) * | 2013-05-31 | 2014-12-17 | 深圳市海思半导体有限公司 | Data processing device |
| CN204291023U (en) * | 2014-12-11 | 2015-04-22 | 中国矿业大学 | A kind of RS232, RS485 and CAN based on FPGA turns Ethernet device |
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