CN112148291A - Instruction block processing method and device, storage medium, and electronic device - Google Patents

Abstract

The embodiment of the invention provides a method and a device for processing an instruction block, a storage medium and an electronic device, wherein the method comprises the following steps: compiling the description file of the neural network model through a compiling module to obtain a mirror image package, wherein the mirror image package comprises: the instruction block group, instruction block preface table, jump instruction mapping table, instruction block group include a plurality of instruction blocks to be processed, instruction block preface table is used for pointing out the operation order of a plurality of instruction blocks to and the execution equipment of operation instruction block, execution equipment includes: the processor, acceleration equipment, be provided with jump instruction behind each instruction block, jump instruction mapping table includes: a jump instruction and a next executed instruction block; and loading the mirror image packet, and processing the instruction block group according to the instruction block sequence table and the jump instruction mapping table.

Description

Instruction block processing method and device, storage medium, and electronic device

technical field

The present invention relates to the field of neural networks, and in particular, to a method and device for processing instruction blocks, a storage medium, and an electronic device.

Background technique

With the great improvement of computing power and the convenience of obtaining big data, great progress has been made in deep learning technology. More and more problems such as image processing and natural language analysis can be well solved by deep learning technology.

Deep neural network models solve business problems and need to perform an inference process. Devices that perform inference operations generally include a central processing unit (Central Processing Unit, referred to as CPU), graphics processing unit (Graphics Processing Unit, referred to as GPU), field programmable gate array (Field Programable Gate Array, referred to as FPGA), etc. In the process of implementing this kind of business, in order to efficiently utilize resources and obtain results quickly, it is necessary to have a deep understanding of the computing and storage architecture of inference computing devices, as well as the computing requirements described by deep neural networks. It is often more difficult and takes a long time.

In particular, some business functions often require a combination of multiple neural networks to complete. For example, in the face recognition business scenario, a deep neural network model needs to be called first to detect whether the image contains a human face image (FaceDetection face detection). ), if there is a face image of someone, then input the image into another deep neural network for inference operation, obtain the detailed feature information of the face image, perform identification (Face Idnetification, face recognition), and finally obtain the business needs the result of.

In the related art, for one or more neural network systems, how to schedule and process different instruction blocks, etc., there is currently no effective solution.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide an instruction block processing method and device, a storage medium, and an electronic device to solve the problem of how to schedule and process different instructions for one or more neural network systems in the related art.

According to an embodiment of the present invention, a method for processing instruction blocks is provided, including: compiling a description file of a neural network model through a compilation module to obtain an image package, wherein the image package includes: an instruction block group, an instruction block Block sequence table, jump instruction mapping table, the instruction block group includes multiple instruction blocks to be processed, the instruction block sequence table is used to indicate the running order of the multiple instruction blocks, and the execution device for running the instruction blocks , the execution device includes: a processor and an acceleration device, each of the instruction blocks is provided with a jump instruction, and the jump instruction mapping table includes: the jump instruction and the next executed instruction block; The image package is processed, and the instruction blocks of the instruction block group are processed according to the instruction block sequence table and the jump instruction mapping table.

In the embodiment of the present invention, compiling the description files of the neural network model by the compiling module to obtain the image package includes: compiling the description files of multiple neural network models through the compiling module to obtain the images corresponding to the multiple neural network models Bag.

In the embodiment of the present invention, processing the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table includes: instructing the execution device in the instruction block sequence table to execute the instruction block according to the instruction block. The execution order of the sequence table and the jump instruction mapping table process the instruction blocks of the instruction block group.

In the embodiment of the present invention, after the instruction blocks of the instruction block group are processed according to the instruction block sequence table and the jump instruction mapping table, the method further includes: for each instruction, according to the execution sequence After processing an instruction, cache the resulting data in a pre-allocated buffer.

According to another embodiment of the present invention, an apparatus for processing instruction blocks is also provided, including: a compilation module for compiling a description file of a neural network model to obtain an image package, wherein the image package includes: an instruction Block group, instruction block sequence table, jump instruction mapping table, the instruction block group includes multiple instruction blocks to be processed, the instruction block sequence table is used to indicate the running order of the multiple instruction blocks, and the running instruction A block execution device, the execution device includes: a processor, an acceleration device, a jump instruction is set after each of the instruction blocks, and the jump instruction mapping table includes: the jump instruction and the next executed instruction block; a processing module, configured to load the image package, and process the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table.

In the embodiment of the present invention, the compiling module is used for compiling description files of multiple neural network models through the compiling module to obtain image packages corresponding to the multiple neural network models.

In the embodiment of the present invention, the processing module is further configured to instruct the execution device in the instruction block sequence table to process the instruction block group according to the running order of the instruction block sequence table and the jump instruction mapping table .

In this embodiment of the present invention, the processing module is further configured to, for each instruction, cache the obtained data in a pre-allocated buffer area after processing an instruction according to the running order.

According to yet another embodiment of the present invention, a storage medium is also provided, wherein a computer program is stored in the storage medium, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.

According to yet another embodiment of the present invention, there is also provided an electronic device comprising a memory and a processor, wherein the memory stores a computer program, the processor is configured to run the computer program to execute any of the above Steps in Method Examples.

According to the present invention, the description file of the neural network model is compiled by the compiling module to obtain an image package, wherein the image package includes: an instruction block group, an instruction block sequence table, and a jump instruction mapping table, and the instruction block group includes Multiple instruction blocks to be processed, the instruction block sequence table is used to indicate the running order of the multiple instruction blocks, and an execution device for running the instruction blocks, the execution device includes: a processor, an acceleration device, each of which A jump instruction is provided after the instruction block, and the jump instruction mapping table includes: the jump instruction and the instruction block to be executed next; load the image package, and follow the instruction block sequence table and the jump instruction block. Converting the instruction mapping table to process the instruction blocks of the instruction block group solves the problem of how to schedule and process different instruction blocks for one or more neural network systems in the related art, and then flexibly process multiple instruction blocks in the instruction block group. instruction block.

Description of drawings

The accompanying drawings described herein are used to provide further understanding of the present invention and constitute a part of the present application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached image:

1 is a block diagram of a hardware structure of a terminal of a method for processing an instruction block according to an embodiment of the present invention;

2 is a flowchart of a method for processing an instruction block according to an embodiment of the present invention;

3 is a structural block diagram of an apparatus for processing an instruction block according to an embodiment of the present invention;

4 is a schematic diagram of a compilation module workflow according to a preferred embodiment of the present invention;

FIG. 5 is a schematic diagram of the composition of an image package according to a preferred embodiment of the present invention;

6 is a functional block diagram of a running state module according to a preferred embodiment of the present invention;

7 is a schematic diagram of input and output buffering and control information according to a preferred embodiment of the present invention;

8 is a schematic diagram of adding an acceleration device instruction block and a jump instruction according to a preferred embodiment of the present invention;

Fig. 9 is the jump position mapping table of the instruction block of the acceleration device according to the preferred embodiment of the present invention;

10 is a flow chart of the acceleration device running according to the instruction according to the preferred embodiment of the present invention;

11 is a block diagram of the internal functions of an acceleration device according to a preferred embodiment of the present invention;

FIG. 12 is a flow chart of the interaction between the host and the acceleration device according to the preferred embodiment of the present invention;

Figure 13 is an overall system block diagram according to a preferred embodiment of the present invention.

Detailed ways

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that the embodiments in the present application and the features of the embodiments may be combined with each other in the case of no conflict.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence.

Example 1

The method embodiment provided in Embodiment 1 of the present application may be executed in a terminal or a similar computing device. Taking running on a terminal as an example, FIG. 1 is a block diagram of a hardware structure of a terminal of a method for processing an instruction block according to an embodiment of the present invention. As shown in FIG. 1 , the terminal 10 may include one or more (only one is shown in FIG. 1 ) processors 102 (the processors 102 may include but are not limited to processing devices such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, optionally, the above-mentioned terminal may further include a transmission device 106 and an input/output device 108 for communication functions. Those of ordinary skill in the art can understand that the structure shown in FIG. 1 is only for illustration, which does not limit the structure of the above-mentioned terminal. For example, the terminal 10 may also include more or fewer components than those shown in FIG. 1 , or have a different configuration with equivalent or more functions than those shown in FIG. 1 .

The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as a computer program corresponding to the method for navigating a car-hailing network in the embodiment of the present invention. By running the computer program stored in the memory 104, the processor 102, Thereby, various functional applications and data processing are performed, that is, the above-mentioned method is realized. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, memory 104 may further include memory located remotely from processor 102, and these remote memories may be connected to terminal 10 through a neural network model. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

Transmission means 106 are used to receive or transmit data via a network. The specific example of the above-mentioned network may include a wireless network provided by the communication provider of the terminal 10 . In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC for short), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet in a wireless manner.

A method for processing an instruction block running on a terminal is provided in this embodiment. FIG. 2 is a flowchart of a method for processing an instruction block according to an embodiment of the present invention. As shown in FIG. 2 , the process includes the following steps:

Step S202, compiling the description file of the neural network model by the compiling module to obtain an image package, wherein the image package includes: an instruction block group, an instruction block sequence table, and a jump instruction mapping table, and the instruction block group includes a plurality of to-be-processed The instruction block, the instruction block sequence table is used to indicate the running order of multiple instruction blocks, and the execution device for running the instruction block. The execution device includes: a processor, an acceleration device, and each instruction block is provided with a jump instruction, a jump instruction The mapping table includes: jump instructions and the next executed instruction block;

Step S204: Load the image package, and process the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table.

According to the present invention, the description file of the neural network model is compiled by the compiling module to obtain an image package, wherein the image package includes: an instruction block group, an instruction block sequence table, and a jump instruction mapping table, and the instruction block group includes Multiple instruction blocks to be processed, the instruction block sequence table is used to indicate the running order of the multiple instruction blocks, and an execution device for running the instruction blocks, the execution device includes: a processor, an acceleration device, each of which A jump instruction is provided after the instruction block, and the jump instruction mapping table includes: the jump instruction and the instruction block to be executed next; load the image package, and follow the instruction block sequence table and the jump instruction block. Converting the instruction mapping table to process the instruction blocks of the instruction block group solves the problem of how to schedule and process different instruction blocks for one or more neural network systems in the related art, and then flexibly process multiple instruction blocks in the instruction block group. instruction block.

In the embodiment of the present invention, compiling the description files of the neural network model by the compiling module to obtain the image package includes: compiling the description files of multiple neural network models through the compiling module to obtain the images corresponding to the multiple neural network models Bag.

In the embodiment of the present invention, processing the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table includes: instructing the execution device in the instruction block sequence table to execute the instruction block according to the instruction block. The execution order of the sequence table and the jump instruction mapping table process the instruction blocks of the instruction block group.

In the embodiment of the present invention, after the instruction blocks of the instruction block group are processed according to the instruction block sequence table and the jump instruction mapping table, the method further includes: for each instruction, according to the execution sequence After processing an instruction, cache the resulting data in a pre-allocated buffer.

From the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is better implementation. Based on this understanding, the technical solutions of the present invention can be embodied in the form of software products in essence or the parts that make contributions to the prior art, and the computer software products are stored in a storage medium (such as ROM/RAM, magnetic disk, CD-ROM), including several instructions to make a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present invention.

In this embodiment, an apparatus for processing an instruction block is also provided, and the apparatus is used to implement the above-mentioned embodiments and preferred implementations, and what has been described will not be repeated. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, implementations in hardware, or a combination of software and hardware, are also possible and contemplated.

FIG. 3 is a structural block diagram of an apparatus for processing an instruction block according to an embodiment of the present invention. As shown in FIG. 3 , the apparatus includes:

The compiling module 30 is used for compiling the description file of the neural network model to obtain an image package, wherein the image package includes: an instruction block group, an instruction block sequence table, and a jump instruction mapping table, and the instruction block group includes an instruction block group to be processing multiple instruction blocks, the instruction block sequence table is used to indicate the execution order of the multiple instruction blocks, and an execution device for executing the instruction blocks, the execution device includes: a processor, an acceleration device, each of the A jump instruction is provided after the instruction block, and the jump instruction mapping table includes: the jump instruction and the instruction block to be executed next;

The processing module 32 is configured to load the image package, and process the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table.

According to the present invention, the description file of the neural network model is compiled by the compiling module to obtain an image package, wherein the image package includes: an instruction block group, an instruction block sequence table, and a jump instruction mapping table, and the instruction block group includes Multiple instruction blocks to be processed, the instruction block sequence table is used to indicate the running order of the multiple instruction blocks, and an execution device for running the instruction blocks, the execution device includes: a processor, an acceleration device, each of which A jump instruction is provided after the instruction block, and the jump instruction mapping table includes: the jump instruction and the instruction block to be executed next; load the image package, and follow the instruction block sequence table and the jump instruction block. Converting the instruction mapping table to process the instruction blocks of the instruction block group solves the problem of how to schedule and process different instruction blocks for one or more neural network systems in the related art, and then flexibly process multiple instruction blocks in the instruction block group. instruction block.

In the embodiment of the present invention, the compiling module 30 is configured to compile the description files of multiple neural network models through the compiling module to obtain image packages corresponding to the multiple neural network models.

In this embodiment of the present invention, the processing module 32 is further configured to instruct the execution device in the instruction block sequence table to process the instruction block according to the running order of the instruction block sequence table and the jump instruction mapping table Group.

In this embodiment of the present invention, the processing module 32 is further configured to, for each instruction, cache the obtained data in a pre-allocated buffer area after processing an instruction according to the running order.

The process of processing the above-mentioned instruction block will be roughly described below with reference to the preferred embodiment, but it is not used to limit the technical solution of the embodiment of the present invention.

Preferred Embodiment 1

The preferred embodiment of the present invention focuses on the realization of the business reasoning function of face detection. It should be noted that the neural network model 1 performs the function of face detection, identifies whether the picture contains a human face, and gives the position of the human face in the picture. ; The neural network model 2 performs face recognition, extracts the features of the face given by the neural network model 1, compares it with the database, and gives the recognition result; generally, some preprocessing is required before inputting the neural network model. After the network model runs, some post-processing work is performed.

Based on the functions completed by the above-mentioned neural network model 1 and neural network model 2, the technical solution of the preferred embodiment of the present invention includes the following steps:

Step 1: The two neural network models are input into the compilation module for compilation;

Step 1.1: Input the two neural network model description files into the encoding module for compilation;

Step 1.2: Compile the module to compile, and finally output the image package, as shown in Figure 4;

Wherein, as shown in FIG. 5 , the image package includes an instruction block group and instruction block sequence description, and an acceleration device jump mapping table.

Specifically, the instruction block group includes NET_C0, NET_D1, NET_C1, NET_D2, and NET_C2; they correspond to the CPU face detection preprocessing (NET_C0), the acceleration device performs face detection (NET_D1), and the CPU performs face detection post-processing and face recognition. Preprocessing (NET_C1), accelerating the device for face recognition processing (NET_D2), CPU for face recognition post-processing, and completing the business (NET_C2);

The instruction block sequence table gives C0-D1-C1-D2-C2, where Cx indicates that the CPU performs the calculation processing with the sequence number x; Dx indicates that the acceleration device Device performs the sequence number x segment instruction processing.

It should be noted that, in the preferred embodiment of the present invention, it is assumed that the related operations described by the neural network model 1 are processed by the acceleration device as a whole (NET_D1), and the computations described by the neural network model 2 are required to be processed by the acceleration device (NET_D2). Face detection preprocessing (NET_C0), the output results are submitted to the acceleration device for processing, and face detection is required. After the acceleration device receives the relevant input, it completes the face detection NET_D1 operation, outputs the face position and other information, and the CPU obtains it, performs the face detection post-processing and face recognition preprocessing (described in NET_C1), and submits the processed data to the acceleration device. Perform face recognition (NET_D2) processing. After the processing is completed, submit it to the CPU for neural network model face recognition post-processing (NET_C2) to complete the overall business function;

It should be noted that it is assumed here that the division of a single instruction block of a single neural network model is not loss of generality. If the acceleration device supports part of the operations described by the neural network model, it can be divided into multiple modules. For details, please refer to the preferred embodiment 2. .

Step 2 is the processing flow related to the running state;

In the compilation phase, the image package output is completed and submitted to the running state for operation.

As shown in Figure 6, the running state includes the following modules: a loading module, an acceleration device control management module, an input and output management module, an upper-layer API interface, etc., wherein,

The loading module completes the loading of the instruction block group to the corresponding device, and the acceleration device management module controls the start, stop, reset, etc. of the acceleration device; the API interface completes the interaction with the upper-layer user;

The input and output management module completes the input and output interaction with the acceleration device (as shown in Figure 11 is the internal block diagram of the acceleration device), and organizes the running items through the control information contained in the cache items, specifically: from the acceleration device side See, there is an input buffer area (InBuffer) and an output buffer area (OutBuffer); as shown in Figure 7: the buffer area has two pieces of content, a piece of control information and a piece of data information; the control information includes the picture serial number Px, the instruction block processing equipment and The instruction block serial number Tx, where x is a number, T is the device type, there are C and D, C represents the CPU on the host side, and D represents the acceleration device Device.

Step 2.1: Use the API interface to set the input and output, and complete the programming;

Step 2.2: Compile the code with a general compilation tool (such as gcc) to generate an executable file;

Step 2.3: Running the executable file: The running process is shown in Figure 12.

In the running state of the HOST side, according to the instruction block sequence table, the CPU is first scheduled to perform face detection preprocessing (NET_C0) processing. After the calculation is completed, the data is filled into InBuffer, and the filling control information is P1-Net-D1, indicating that face detection is required. Neural network model inference process.

The accelerator obtains the content in the InBuffer, and performs the command processing of the face detection (Net-D1). After the processing is completed, the data is filled into the OutBuffer, and the input control information (P1-Net-D1) is copied at the same time.

After the HOST side obtains the content from the device OutBuffer, it judges the post-processing of face detection and the pre-processing of the neural network model of face recognition (Net-C1) according to the instruction block sequence table. And fill the control information as P1-Net_D2 (face recognition neural network model operation) according to the instruction set sequence table.

The acceleration device acquires this item for face recognition calculation (Net_d2) processing, outputs the data, and copies the control information P1-Net_D2.

The CPU side obtains this item, and performs the post-processing (NET_C2) processing of the face recognition data according to the instruction block sequence table to complete the overall reasoning.

It can be seen from the above process that in the process of using the instruction block sequence table, the processing of the control information on the device side is accelerated, and only copying is performed. The host side maintains and modifies the control information according to the instruction block sequence table.

Here, the acceleration device has two different functions, face detection (NET-D1) and face recognition (NET-D2), among which the time division multiplexing is to use jump instructions and jump mapping tables to complete the neural network Model function inference switch. The relevant situations are as follows:

The first case: compiled state processing: the following four steps:

Step a: The compilation module generates the neural network model according to the equipment conditions and dispatches the instruction block NET_Tx to different equipment, (in this example, face detection processing (NET_D1) and face recognition processing (NET_D2);

Step b: The compilation module adds the jump instruction JMP 0 after the acceleration device instruction block NET_Dx;

Step c: Compile the module to generate the jump mapping table of the acceleration device (it can also be generated in runtime, and the generation of the compilation module is described here). The jump mapping table is shown in Figure 9.

Step d: The compilation module adds the buff acquisition instruction and the JMP Rj instruction before the acceleration device instruction block NET-D0; (Fig. 8)

The second case: the operation process of the acceleration device to the instruction is as follows: (Figure 10)

1) Execute the instruction, execute from the instruction base address 0;

2) Obtain data (control information + data input) from InBuffer, parse the neural network model index from the control word, look up the mapping table, obtain the base address of the execution instruction, and fill it with Rj.

3) Jump to the instruction base address to start execution;

4) Until the execution reaches the end of the neural network model processing, output the execution result to OutBuffer, and write the input control word;

5) Then execute JMP 0 and repeat.

Preferred Embodiment 2: The single neural network model needs to run together on the host and the acceleration device

Step 2.1: Input the neural network model into the compilation module, compile it, and output the image package;

Assume that the neural network model instruction block combination and instruction block sequence table are C0-D1-C1-D2-C2; it means that the neural network model needs to be preprocessed by the host CPU, then accelerated by the device, then processed by the CPU, and then processed by the accelerated device. final CPU processing;

The example of the device jumping table is the same as that of the preferred embodiment 1, and details are not repeated here.

Step 2.2: Compile and generate executable files according to the API interface code;

Step 2.3: The HOST side runs in a running state, performs image loading, and runs; the process is generally the same as Step 2 in the preferred embodiment 1;

Step 2.4: The running state continues to run, and the inference operation results are continuously given.

Preferred Embodiment 3: Combination of multiple neural network models, and a single neural network model needs multiple splits

Step 3.1: Input the multi-neural network model into the compilation module, compile it, and output the image package;

Without loss of generality, the neural network model instruction block combination and instruction block sequence table can be set as C0-D1-C1-D2-C2-D3-C3-C4-D4-C5-D5-C6;

The example of the device jump table is the same as that of the preferred embodiment 1.

Step 3.2: the same as other steps of preferred embodiment 2.

From the perspective of the preferred embodiments of the present invention, the embodiments of the present invention and the contents disclosed in the preferred embodiments are not only applicable to the combined inference business of multiple neural network models, but also can be applied to services that require a combination of HOST and acceleration devices for a single neural network model. In addition, the combination of multiple neural network models with the neural network model completed by the HOST and the acceleration device itself is also applicable; the combination of the host and multiple acceleration devices is also applicable; these are all within the protection scope of the present invention.

Further, the technical solutions of the above-mentioned embodiments and preferred embodiments of the present invention, aiming at the problem that business reasoning related to the combination of multiple neural network models is difficult to implement, provide a two-stage compilation and running, using jump instructions and mapping. The table and the instruction block sequence table realize the method, device and system for combining business reasoning of multi-neural neural network models.

In an optional embodiment of the present invention, there is provided a method for compiling and generating a sequence table of used instruction blocks, and performing multi-device scheduling and cooperative operation according to the table at runtime;

In an optional embodiment of the present invention, there is provided a method and a device for an acceleration device to use a simple jump instruction based on a jump map to perform time division multiplexing to complete different computing functions;

In an optional embodiment of the present invention, a neural network model acceleration device is provided, including: an instruction cache for storing related instructions; a functional unit set module for implementing a neural network model related calculation module; a jump instruction, Jump mapping table, used to realize the jump of neural network model function group; register group, etc.;

In an optional embodiment of the present invention, a compiling module for a deep neural network model is provided, which compiles and converts the deep neural network model into a relevant instruction set; and generates a relevant instruction block sequence table and a jump mapping table;

In an optional embodiment of the present invention, a running state module for the inference operation of a neural network model is provided: including a loading module, which loads a relevant image to a specific location; device control, which controls the start, stop, reset, etc. of the acceleration device; Input and output management of equipment, provide data to be processed and requirements to equipment, and obtain processing results of equipment; including programming interface (API) provided to business users;

To sum up, through the method and device for processing instruction blocks in the embodiment of the present invention and the preferred embodiment, the compiling and running state system (as shown in FIG. 13 ) can be used to conveniently, quickly and efficiently complete the reasoning of the multi-neural network model Landing, easy to complete related business functions.

An embodiment of the present invention further provides a storage medium, where a computer program is stored in the storage medium, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.

Optionally, in this embodiment, the above-mentioned storage medium may be configured to store a computer program for executing the following steps:

S1, the description file of the neural network model is compiled by the compilation module to obtain an image package, wherein the image package includes: an instruction block group, an instruction block sequence table, a jump instruction mapping table, and the instruction block group includes a plurality of instructions to be processed Block, the instruction block sequence table is used to indicate the running order of multiple instruction blocks, and the execution device for running the instruction block. The execution device includes: a processor, an acceleration device, and each instruction block is provided with a jump instruction, and the jump instruction mapping The table includes: jump instructions and the next executed instruction block;

S2: Load the image package, and process the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table.

Optionally, in this embodiment, the above-mentioned storage medium may include but is not limited to: a USB flash drive, a read-only memory (Read-Only Memory, referred to as ROM), a random access memory (Random Access Memory, referred to as RAM), Various media that can store computer programs, such as removable hard disks, magnetic disks, or optical disks.

An embodiment of the present invention further provides a storage medium, where a computer program is stored in the storage medium, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.

An embodiment of the present invention also provides an electronic device, comprising a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

Optionally, the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.

Optionally, in this embodiment, the above-mentioned processor may be configured to execute the following steps through a computer program:

S1, the description file of the neural network model is compiled by the compilation module to obtain an image package, wherein the image package includes: an instruction block group, an instruction block sequence table, a jump instruction mapping table, and the instruction block group includes a plurality of instructions to be processed Block, the instruction block sequence table is used to indicate the running order of multiple instruction blocks, and the execution device for running the instruction block. The execution device includes: a processor, an acceleration device, and each instruction block is provided with a jump instruction, and the jump instruction mapping The table includes: jump instructions and the next executed instruction block;

S2: Load the image package, and process the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table.

Optionally, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementation manners, and details are not described herein again in this embodiment.

An embodiment of the present invention also provides an electronic device, comprising a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

Optionally, the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.

Optionally, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementation manners, and details are not described herein again in this embodiment.

Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general-purpose computing device, and they can be centralized on a single computing device, or distributed in a neural network composed of multiple computing devices. On the network model, they can optionally be implemented in program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, in a different The illustrated or described steps are performed in order, either by fabricating them separately into individual integrated circuit modules, or by fabricating multiple modules or steps of them into a single integrated circuit module. As such, the present invention is not limited to any particular combination of hardware and software.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A method for processing an instruction block, comprising:

compiling the description file of the neural network model through a compiling module to obtain a mirror image package, wherein the mirror image package comprises: the instruction block group comprises a plurality of instruction blocks to be processed, the instruction block sequence table is used for indicating the operation sequence of the instruction blocks and executing equipment of the instruction blocks, and the executing equipment comprises: the processor, acceleration equipment, be provided with jump instruction behind each instruction block, jump instruction mapping table includes: the jump instruction and the next executed instruction block;

and loading the mirror image packet, and processing the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table.

2. The method of claim 1, wherein compiling the description file of the neural network model by the compiling module to obtain a mirror package comprises:

and compiling the description files of the plurality of neural network models through a compiling module to obtain mirror image packages corresponding to the plurality of neural network models.

3. The method of claim 1, wherein processing the instruction blocks of the group of instruction blocks according to the instruction block order table and the jump instruction mapping table comprises:

and instructing the execution equipment in the instruction block sequence table to process the instruction blocks of the instruction block group according to the running sequence of the instruction block sequence table and the jump instruction mapping table.

4. The method according to any of claims 1 to 3, wherein after processing the instruction blocks of the group of instruction blocks according to the instruction block order table and the jump instruction mapping table, the method further comprises:

and for each instruction, after one instruction is processed according to the running sequence, caching the obtained data into a pre-allocated cache region.

5. An apparatus for processing an instruction block, comprising:

the compiling module is used for compiling the description file of the neural network model to obtain a mirror image package, wherein the mirror image package comprises: the instruction block group comprises a plurality of instruction blocks to be processed, the instruction block sequence table is used for indicating the operation sequence of the instruction blocks and executing equipment of the instruction blocks, and the executing equipment comprises: the processor, acceleration equipment, be provided with jump instruction behind each instruction block, jump instruction mapping table includes: the jump instruction and the next executed instruction block;

and the processing module is used for loading the mirror image packet and processing the instruction blocks of the instruction block group according to the instruction block sequence table and the jump instruction mapping table.

6. The apparatus of claim 5, wherein the compiling module is configured to compile the description files of the plurality of neural network models through the compiling module to obtain the mirror image packages corresponding to the plurality of neural network models.

7. The apparatus of claim 5, wherein the processing module is further configured to instruct an execution device in the instruction block ordered table to process the instruction block groups according to the operation order of the instruction block ordered table and the jump instruction mapping table.

8. The apparatus of any of claims 5 to 7, wherein the processing module is further configured to, for each instruction, cache the obtained data in a pre-allocated cache area after processing one instruction according to the execution order.

9. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 4 when executed.

10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 4.

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