CN112135385B - A flow-type dynamic display light control circuit - Google Patents
A flow-type dynamic display light control circuit Download PDFInfo
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- CN112135385B CN112135385B CN202011141025.5A CN202011141025A CN112135385B CN 112135385 B CN112135385 B CN 112135385B CN 202011141025 A CN202011141025 A CN 202011141025A CN 112135385 B CN112135385 B CN 112135385B
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- 239000003990 capacitor Substances 0.000 claims description 23
- 230000004044 response Effects 0.000 claims description 8
- 230000000694 effects Effects 0.000 abstract description 12
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 42
- 101100464779 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CNA1 gene Proteins 0.000 description 27
- 238000010586 diagram Methods 0.000 description 21
- 101100464782 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CMP2 gene Proteins 0.000 description 14
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 12
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 9
- 230000003068 static effect Effects 0.000 description 6
- 102100040844 Dual specificity protein kinase CLK2 Human genes 0.000 description 5
- 101000749291 Homo sapiens Dual specificity protein kinase CLK2 Proteins 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000007599 discharging Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 230000001795 light effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 1
- 108010001267 Protein Subunits Proteins 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/30—Driver circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
- H05B47/155—Coordinated control of two or more light sources
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
本发明公开了一种流水式动态显示灯控制电路，包括：控制信号生成单元，用于生成时钟信号组；驱动控制单元，包括结构相同、且级联的多级驱动控制子单元，每一级驱动控制子单元对应控制一级LED灯组的点亮。本发明通过优化电路结构，利用外部输入的时钟信号以及与所述时钟信号有时序关系的控制信号、或电路内部产生的下拉控制信号，控制各级驱动控制子单元顺序工作，从而控制相应的LED灯组顺序点亮，实现流光效果，无需采用多路D触发器，有效节省了成本，优化了产品的性价比，具有推广价值。
The present invention discloses a flow-type dynamic display light control circuit, comprising: a control signal generating unit for generating a clock signal group; a driving control unit, comprising a plurality of driving control subunits with the same structure and cascaded, each driving control subunit corresponding to a first-level LED light group lighting. The present invention optimizes the circuit structure, utilizes an externally input clock signal and a control signal having a timing relationship with the clock signal, or a pull-down control signal generated inside the circuit, controls the driving control subunits of each level to work sequentially, thereby controlling the corresponding LED light groups to light up sequentially, and realizing a streamer effect, without the need to use a multi-channel D flip-flop, effectively saving costs, optimizing the product's cost performance, and having promotion value.
Description
Technical Field
The invention relates to the technical field of control, in particular to a low-power-consumption and low-cost running water type dynamic display lamp control circuit.
Background
With the development of national economy, automobiles are emerging in more and more families. With the rapid development of the automobile industry, the requirements of people on automobiles are also increasing. In an automotive lighting system, automotive display lamps can be classified into two types, an indicator lamp and a decorative lamp. The indicator lamp can indicate the driving state of the automobile, such as a steering lamp, and the decorative lamp plays a role in improving the aesthetic degree of the automobile and can be arranged at a plurality of parts of the automobile, such as a door handle.
With the development of LED lighting technology, LEDs are also widely used in automotive lighting systems, people are pursuing more glaring display effects, and continuous-flow dynamic display lamps are gradually applied to indicator lamps and decorative lamps. At present, a sequential running light steering lamp function similar to the running light effect is already available on an automobile tail lamp. In order to be unified with the display effect of the running light turn signal lamp on the taillight, the turn signal lamp on the outer rearview mirror needs to be made into the running light turn signal lamp.
Referring to fig. 1, a schematic diagram of a conventional flow-through dynamic display lamp control circuit is shown. The control circuit comprises a clock generation oscillation unit 11, a data shift unit 12, a driving unit 13 and an LED light source group 14. The clock generation oscillation unit 11 adopts a 555 cycle pulse generation chip for generating a clock signal and a data signal. The data shift unit 12 employs an 8-bit integrated D flip-flop chip (e.g., 74HC273 or 74HC 595) for generating the driving control signal according to the period of the clock signal. The driving unit 13 adopts a triode, and is used for driving corresponding LED lamps in the LED light source group 14 to be dynamically lighted according to the driving control signal. That is, each D trigger is controlled in turn according to the period of the clock signal, and each D trigger controls a triode to drive an LED lamp, thereby realizing the flowing water display effect that the LED lamps are sequentially lighted one by one.
In most of the current automobile bodies, the standard of the power supply voltage is generally 9V-16V. The on voltage drop of one LED is generally 1.9V-2.7V, taking the intermediate value of 2.3V, the on voltage drop of 4 LEDs will be 2.3×4=9.2V, which is greater than the lower limit 9V of the power supply voltage of the vehicle body. Therefore, in a 9V-16V powered vehicle body system, a maximum of 3 LEDs can be connected in series, i.e., the output of one D flip-flop can drive a maximum of 3 LEDs. For a running-water type dynamic display lamp with more LED lamps, for example, 9-24 LED lamps, a plurality of 8-way D trigger chips are needed, and the required cost is high. And 8 way D trigger chips own occupy certain space, and its eight delivery outlets need alone to lead to on the triode that every LED lamp corresponds, and when circuit board space is than less, can't provide required space that takes up for chip and eight delivery outlet leads, brings the difficulty for circuit layout design.
Therefore, how to adopt a relatively simple circuit structure to realize the control of the streamer steering lamp, optimize the control effect and reduce the control cost becomes a technical problem to be solved urgently in the development of the streamer steering lamp.
Disclosure of Invention
The invention aims to solve the technical problems in the prior art and provide a running water type dynamic display lamp control circuit which can realize dynamic control of a dynamic display lamp by adopting a relatively simple circuit structure, optimize the control effect and reduce the control cost.
The invention provides a running water type dynamic display lamp control circuit which comprises a control signal generation unit, a driving control unit and a first-stage driving control subunit, wherein the control signal generation unit is used for generating a clock signal group, the clock signal group comprises a clock signal and a control signal which is in time sequence relation with the clock signal, the driving control unit comprises a plurality of driving control subunits which are identical in structure and are in cascade connection, each driving control subunit correspondingly controls the lighting of one-stage LED lamp group, the first-stage driving control subunit is used for driving the corresponding LED sub-lamp group in the corresponding first-stage LED lamp group according to a first power supply voltage and the clock signal group, the first-stage driving control subunit is used for dynamically lighting the corresponding LED sub-lamp group in the corresponding first-stage LED lamp group according to a second power supply voltage and the lighting result of the last LED sub-lamp group in the first-stage LED lamp group, maintaining the lighting state of all LED sub-lamp groups in the first-stage LED lamp group, and providing a pull-down control signal to the next-stage driving control subunit so that the corresponding LED sub-lamp group in the corresponding LED sub-stage lamp group in the first-stage LED lamp group supports dynamic lighting, and the pull-down control subunit is provided according to the first power supply voltage and the pull-down control subunit and the corresponding LED sub-stage driving control subunit in the first-stage driving control unit.
The invention has the advantages that the dynamic lighting function of the dynamic display lamp can be realized by adopting simple components and circuit architecture without adopting a multipath D trigger through optimizing the circuit structure, the cost is effectively saved, the cost performance of the product is optimized, and the invention has popularization value. The dynamic display lamp can replace the traditional static display lamp and is applied to indication or decoration. For example, the dynamic display lamp can replace the static indicator lamp of the existing automobile to indicate the running state of the automobile and realize the running light steering effect, and the dynamic display lamp can also replace the static decorative lamp of the existing automobile to be arranged at the positions of the door handle and the like of the automobile to realize the running light decorative effect and improve the aesthetic degree of the automobile.
Drawings
FIG. 1 is a schematic diagram of a conventional flow-through dynamic display lamp control circuit;
FIG. 2 is a schematic diagram of a flow-through dynamic display lamp control circuit according to the present invention;
FIG. 3 is a circuit diagram of an embodiment of a control signal generating unit according to the present invention;
FIG. 4 is a circuit diagram of a first embodiment of a flow-through dynamic display lamp control circuit of the present invention;
FIG. 5 is a circuit diagram of a second embodiment of a flow-through dynamic display lamp control circuit of the present invention;
FIG. 6 is a circuit diagram of a third embodiment of a flow-through dynamic display lamp control circuit of the present invention;
FIG. 7 is a circuit diagram of a fourth embodiment of a flow-through dynamic display lamp control circuit of the present invention;
FIG. 8 is a circuit diagram of a fifth embodiment of a flow-through dynamic display lamp control circuit of the present invention;
FIG. 9 is a schematic diagram of an embodiment of an LED lamp set according to the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention. Furthermore, the present invention in various examples repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Referring to fig. 2, a schematic diagram of a running water type dynamic display lamp control circuit according to the present invention is shown. The circuit includes a control signal generation unit 21 and a drive control unit 22.
The control signal generating unit 21 is configured to generate a clock signal group, where the clock signal group includes a clock signal and a control signal having a timing relationship with the clock signal. Because the control signals have a strict timing relationship with the clock signals, the control signals can be derived from the clock signals, and the control signals and the clock signals together form a clock signal group. The clock signal group can be formed by a 555 chip plus a resistor-capacitor element, or can be formed by a voltage comparator plus a resistor-capacitor element. Specifically, the clock signal may be generated first, and then the other control signals may be derived.
The drive control unit 22 comprises cascade multi-stage drive control subunits (221, 222, 22 n) which are identical in structure, and each of the multi-stage drive control subunits correspondingly controls the lighting of one-stage LED lamp groups (231, 232, 23 n).
Specifically, the 1 st stage driving control subunit 221 is configured to drive the corresponding LED sub-lamp groups in the corresponding 1 st stage LED lamp group 231 to dynamically light according to the first power voltage V1 and the clock signal group, and maintain the lighting states of all the LED sub-lamp groups in the 1 st stage LED lamp group 231 according to the second power voltage V2 and the lighting result of the last group LED sub-lamp group in the 1 st stage LED lamp group 231, and provide a pull-down control signal to the next stage driving control subunit 222 to enable the corresponding LED sub-lamp groups in the corresponding next stage LED lamp group 232 to support dynamic lighting. The first power voltage V1 is greater than the second power voltage V2, for example, the first power voltage V1 is 12V, and the second power voltage V2 is 5V.
Specifically, the 2 nd stage driving control subunit 222 is configured to drive the corresponding LED sub-lamp group in the corresponding 2 nd stage LED lamp group 232 to be dynamically turned on according to the first power voltage V1, the clock signal group, and the pull-down control signal provided by the previous stage driving control subunit 221, and maintain the on state of all LED sub-lamp groups in the 2 nd stage LED lamp group according to the second power voltage V2 and the on result of the last group of LED sub-lamp groups in the 2 nd stage LED lamp group 232, and provide the pull-down control signal to the next stage driving control subunit.
Specifically, the nth stage driving control subunit 22n (n is greater than 1) is configured to drive the corresponding LED sub-lamp group in the corresponding nth stage LED lamp group 23n to be dynamically turned on according to the first power voltage V1, the clock signal group, and the pull-down control signal provided by the previous stage driving control subunit, and maintain the on state of all LED sub-lamp groups in the nth stage LED lamp group according to the second power voltage V2 and the on result of the last group LED sub-lamp group in the nth stage LED lamp group 23n, and provide the pull-down control signal to the next stage driving control subunit. It should be noted that, for the last stage driving control subunit, after the last group of LED sub-lamp groups in the last stage LED lamp group is turned on, the on state of all LED sub-lamp groups in the last stage LED lamp group is maintained, and since there is no next stage driving control subunit, there is no need to provide a pull-down control signal to the next stage driving control subunit.
The invention provides a running water type dynamic display lamp control circuit, which adopts a cascade multistage driving control subunit with the same structure through optimizing a circuit structure, wherein each stage driving control subunit correspondingly controls the lighting of a stage of LED lamp group, utilizes an externally input clock signal and a control signal with a time sequence relation with the clock signal or a pull-down control signal generated in the circuit to control each stage driving control subunit to sequentially work, thereby controlling the corresponding LED lamp group to sequentially light so as to realize a running light effect. The dynamic display lamp can replace the traditional static display lamp and is applied to indication or decoration. For example, the dynamic display lamp can replace the static indicator lamp of the existing automobile to indicate the running state of the automobile and realize the running light steering effect, and the dynamic display lamp can also replace the static decorative lamp of the existing automobile to be arranged at the positions of the door handle and the like of the automobile to realize the running light decorative effect and improve the aesthetic degree of the automobile.
Referring to fig. 3, a circuit diagram of an embodiment of the control signal generating unit of the present invention is shown. In this embodiment, the control signal generating unit 21 includes a first voltage comparator CMP1 and a control transistor Q0. The positive input end of the first voltage comparator CMP1 is configured to receive the reference voltage Vref, the negative input end thereof is connected to the charging capacitor C1, and the output end thereof outputs the clock signal CLK. The control transistor Q0 has a control terminal coupled to the output terminal of the first voltage comparator CMP1, a first terminal for receiving the reference voltage Vref and outputting a second control signal CE2 having a timing opposite to the clock signal CLK, and a second terminal grounded. Note that, for the control circuit using the D flip-flop, the second control signal CE2 may also be an enable signal for controlling the D flip-flop. By reversing the control transistor Q0, the second control signal CE2 is inverted in timing to the clock signal CLK. The clock signal CLK may be a signal with the same pulse width of high and low levels, or may be a signal with asymmetric high and low levels.
In a further embodiment, the control signal generating unit 21 further includes a first resistor R1 and a first diode D1 connected in series, and a second resistor R2 and a second diode D2 connected in series. The first resistor R1 and the first diode D1 which are connected in series are electrically connected between the negative input end and the output end of the first voltage comparator CMP1, and the second resistor R2 and the second diode D2 which are connected in series are electrically connected between the negative input end and the output end of the first voltage comparator CMP 1. The connection direction of the first diode D1 and the second diode D2 is opposite, and the first voltage comparator CMP1 outputs the high-level and low-level asymmetric clock signal by configuring the resistance values of the first resistor R1 and the second resistor R2. Specifically, the charging capacitor C1 is charged by the second resistor R2 and the second diode D2, and is discharged by the first diode D1 and the first resistor R1, and the clock signal CK can be enabled to meet the requirement that the high-level pulse width is twice the low-level pulse width by configuring the resistance value of the second resistor R2 to be twice the resistance value of the first resistor R1.
In a further embodiment, the control signal generating unit 21 further comprises a second voltage comparator CMP2. The positive input end of the first voltage comparator CMP1 is coupled to the output end of the reference voltage Vref through a third resistor R3, the output end of the first voltage comparator is electrically connected to the positive input end of the reference voltage Vref through a fourth resistor R4, the positive input end of the second voltage comparator CMP2 is connected with the charging capacitor C1, the negative input end of the second voltage comparator is electrically connected to the positive input end of the first voltage comparator CMP1 through a fifth resistor R5, and the output end of the second voltage comparator is grounded through a sixth resistor R6, and outputs a first control signal CE1. By configuring the resistances of the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6, the pulse width of the first control signal CE1 is smaller than the pulse width of the clock signal CLK. Specifically, the high level pulse width of the clock signal CLK may be made twice the low level pulse width of the first control signal CE1.
The working principle of the embodiment shown in fig. 3 is further described below. After power-up (switch S1 is closed), since the charging capacitor C1 is not yet charged, the positive input terminal voltage of the first voltage comparator CMP1 is higher than the negative input terminal voltage thereof, the first voltage comparator CMP1 outputs a high level, and the negative input terminal of the second voltage comparator CMP2 is higher than the positive input terminal thereof, and the second voltage comparator CMP2 outputs a low level. Then, the charging capacitor C1 is charged with the second diode D2 through the second resistor R2, and when the voltage on the charging capacitor C1 (i.e., the voltage at the positive input terminal of the second voltage comparator CMP 2) is higher than the negative input terminal level of the second voltage comparator CMP2, the second voltage comparator CMP2 inverts and outputs a high level. However, at this time, the voltage on the charging capacitor C1 is not higher than the voltage at the forward input end of the first voltage comparator CMP1, the charging capacitor C1 continues to be charged until the voltage is higher than the voltage at the forward input end of the first voltage comparator CMP1, the first voltage comparator CMP1 inverts and outputs a low level, and the voltage at the forward input end of the first voltage comparator CMP1 becomes the voltage drop U1 at the fourth resistor R4 after the reference voltage Vref passes through the third resistor R3 and the fourth resistor R4. At this time, the charging capacitor C1 is discharged through the first diode D1 and the first resistor R1, and the voltage at the negative input terminal of the second voltage comparator CMP2 is zero, and the output of the second voltage comparator CMP2 remains at a high level. When the discharging level of the charging capacitor C1 is lower than the voltage of the positive input terminal of the first voltage comparator CMP1, the first voltage comparator CMP1 inverts and outputs a high level. At this time, the voltage of the negative input end of the second voltage comparator CMP2 suddenly changes to a voltage drop U2 on the sixth resistor R6 after the reference voltage Vref passes through the third resistor R3 and the fourth resistor R4 connected in parallel and the fifth resistor R5 and the sixth resistor R6 connected in series, and the voltage of the negative input end of the second voltage comparator CMP2 is higher than the voltage of the positive input end (i.e., the voltage after discharging on the charging capacitor C1), and the second voltage comparator CMP2 turns over and outputs a low level. The high level output by the first voltage comparator CMP1 starts to charge the charging capacitor C1 through the second resistor R2 and the second diode D2, and starts the next cycle.
The control signal generating unit 21 controls the current direction of charging and discharging the charging capacitor C1 by using two diodes D1, D2 of different directions. The charge-discharge time is determined by the capacitance of the charge capacitor C1 and the resistances of the second resistor R2 and the first resistor R1. Since the clock signal CLK output from the first voltage comparator CMP1 is at a high level when the charging capacitor C1 is charged and the clock signal CLK output from the first voltage comparator CMP1 is at a low level when the charging capacitor C1 is discharged, the resistance of the second resistor R2 is twice the resistance of the first resistor R1 since the time required to satisfy the high level of the clock signal CLK is twice the time required to satisfy the low level thereof. The time of charging and discharging also depends on the voltage at the positive input of the first voltage comparator CMP1, since the negative input is connected across the charging capacitor C1, and when the voltage across the charging capacitor C1 is charged or discharged to a voltage higher or lower than the voltage at the positive input of the first voltage comparator CMP1, the output of the first voltage comparator CMP1 will be inverted. When the output of the first voltage comparator CMP1 is zero, the voltage at the positive input terminal is the voltage drop U1 of the reference voltage Vref across the third resistor R3 and the fourth resistor R4, i.e., u1=vref×r4/(r4+r3). When the first voltage comparator CMP1 outputs a high level, the voltage at the positive input end is approximately equal to the voltage of the reference voltage Vref (r5+r6)/(r4// r3+r5+r6) after passing through the third resistor R3 and the fourth resistor R4 in parallel, and the fifth resistor R5 and the sixth resistor R6 in series, and then the voltage is divided by U1' across the fifth resistor R5 and the sixth resistor R6 in series. When the first voltage comparator CMP1 outputs a high level, the voltage at the negative input terminal of the second voltage comparator CMP2 is u2=vref×r6/(r4// r3+r5+r6), and the voltage at the negative input terminal of the second voltage comparator CMP2 is lower than the voltage at the positive input terminal of the first voltage comparator CMP1, so that the output of the second voltage comparator CMP2 is inverted before the output of the first voltage comparator CMP1, and a first control signal CE1 with a narrower pulse than the clock signal CLK output by the first voltage comparator CMP1 is generated. By reasonably setting and adjusting the resistance values of the resistors R3, R4, R5 and R6, the clock signal CLK with the required pulse width and the first control signal CE1 with the pulse width half of the pulse width of the clock signal CLK can be generated. The second control signal CE2 may be obtained from the clock signal CLK through inversion. In the embodiment, components such as a voltage comparator and an external resistor-capacitor are adopted to generate the clock signal group, so that the circuit cost is effectively saved.
Referring to fig. 4, a circuit diagram of a first embodiment of a running water type dynamic display lamp control circuit according to the present invention is shown. In this embodiment, the driving control subunit includes a first pull-up transistor (e.g., the first pull-up transistor Q10 of the level 1 driving control subunit 221, the first pull-up transistor Q20 of the level 2 driving control subunit 222 are illustrated), a first switch transistor (e.g., the first switch transistor M10 of the level 1 driving control subunit 221, the first switch transistor M20 of the level 2 driving control subunit 222 are illustrated), and a pull-down transistor (e.g., the pull-down transistor Q19 of the level 1 driving control subunit 221, the pull-down transistor Q29 of the level 2 driving control subunit 222 are illustrated). Each stage of LED lamp group comprises a first LED sub-lamp group (such as a first LED sub-lamp group LED1 of a1 st stage LED lamp group and a first LED sub-lamp group LED4 of a 2 nd stage LED lamp group in the diagram), a second LED sub-lamp group (such as a second LED sub-lamp group LED2 of the 1 st stage LED lamp group and a second LED sub-lamp group LED5 of the 2 nd stage LED lamp group in the diagram) and a third LED sub-lamp group (such as a third LED sub-lamp group LED3 of the 1 st stage LED lamp group and a third LED sub-lamp group LED6 of the 2 nd stage LED lamp group in the diagram) which are sequentially connected.
The control terminal of the first pull-up transistor (Q10, Q20) is coupled to the output terminal of the first power voltage V1, the first terminal thereof is electrically connected to the first LED sub-lamp group (LED 1, LED 4) in the current LED lamp group, and the second terminal thereof is coupled to the output terminal of the first power voltage V1. The control ends of the first switch tubes (M10, M20) are coupled to the output ends of the clock signal CLK and are electrically connected to the first LED sub-lamp group (LED 1, LED 4) in the current LED lamp group through a feedback resistor (R4, R18), the first ends of the first switch tubes are coupled to the output ends of the first power supply voltage V1, and the second ends of the first switch tubes are grounded (aiming at the 1 st stage driving control subunit) or used for receiving pull-down control signals (aiming at the driving control subunit after the 1 st stage) provided by the previous stage driving control subunit. The control terminals of the pull-down transistors (Q19, Q29) are coupled to the input terminals (LED 3, LED 6) of the last LED sub-lamp group of the current LED lamp group, the first terminals thereof are coupled to the output terminal of the second power supply voltage V2, and the second terminals thereof are electrically connected to the second terminals of the first switch transistors of the next stage driving control sub-unit to provide pull-down control signals (for the last stage 1 driving control sub-unit, the control terminals of the corresponding pull-down transistors are coupled only to the output terminal of the second power supply voltage V2), and the second terminals thereof are grounded. Wherein the first pull-up transistor (Q10, Q20) and the pull-down transistor (Q19, Q29) are operated in different electrode current directions. Specifically, the first pull-up transistor (Q10, Q20) is turned on and maintained on in response to the first power supply voltage V1, the first switching transistor (M10, M20) is turned on and maintained on in response to the clock signal (for the 1 st stage drive control subunit), or is turned on and maintained on in response to a pull-down control signal provided by a previous stage drive control subunit and the clock signal (for the drive control subunit after the 1 st stage), and the pull-down transistor (Q19, Q29) is turned on and maintained on in response to the lighting of the last LED sub-lamp group (LED 3, LED 6) of the current LED lamp group. The first power voltage V1 is greater than the second power voltage V2, for example, the first power voltage V1 is 12V, and the second power voltage V2 is 5V.
In this embodiment, the first ends of the first pull-up transistors (Q10, Q20) are electrically connected to the anodes of the first LED sub-lamp groups (LED 1, LED 4), the cathodes of the third LED sub-lamp groups (LED 3, LED 6) are grounded, and the driving control sub-unit further includes a first transistor (e.g., a first transistor Q11 of the stage 1 driving control sub-unit 221, a first transistor Q21 of the stage 2 driving control sub-unit 222 are illustrated), and a second transistor (e.g., a second transistor Q12 of the stage 1 driving control sub-unit 221, a second transistor Q22 of the stage 2 driving control sub-unit 222 are illustrated).
The control terminal of the first transistor (Q11, Q21) is coupled to the output terminal of the second power voltage V2 and the first terminal of the pull-down transistor (Q19, Q29), the first terminal of which is electrically connected to the negative electrode of the first LED sub-lamp group (LED 1, LED 4), and the second terminal of which is for receiving the first control signal CE1. Wherein, the high level pulse width of the clock signal CLK is twice the low level pulse width thereof, the first control signal CE1 is derived from the clock signal CLK, and the low level thereof has a hold time half of the high level duration of the clock signal CLK.
The control terminal of the second transistor (Q12, Q22) is coupled to the output terminal of the second power voltage V2 and the first terminal of the pull-down transistor (Q19, Q29), the first terminal of which is electrically connected to the negative electrode of the second LED sub-lamp group (LED 2, LED 5), and the second terminal of which is for receiving the second control signal CE2. Wherein the second control signal CE2 is derived from the clock signal CLK and is opposite in timing to the clock signal CLK.
In this embodiment, the control terminals of the pull-down transistors (Q19, Q29) are coupled to the positive electrode of the third LED sub-lamp group (LED 3, LED 6) and simultaneously to ground. In this embodiment, each stage of LED lamp group sequentially works, and the first LED sub-lamp group (LED 4), the second LED sub-lamp group (LED 2, LED 5) and the third LED sub-lamp group (LED 3, LED 6) in each stage of LED lamp group sequentially light up.
Specifically, in the present embodiment, the first pull-up transistors (Q10, Q20), the pull-down transistors (Q19, Q29), the first transistors (Q11, Q21), and the second transistors (Q12, Q22) are all transistors. The base electrode of the triode is used as a control end of the corresponding transistor, the collector electrode of the triode is used as a first end of the corresponding transistor, and the emitter electrode of the triode is used as a second end of the corresponding transistor. In this embodiment, the first switching tube (M10, M20) is an NMOS tube, a gate of the NMOS tube is used as a control end of the first switching tube, a drain of the NMOS tube is used as a first end of the first switching tube, and a source of the NMOS tube is used as a second end of the first switching tube. The current directions of electrodes of the first pull-up transistor (Q10, Q20) and the pull-down transistor (Q19, Q29) are different when in operation, and the current directions of the electrodes of the first transistor, the second transistor and the pull-down transistor are the same when in operation. For example, PNP type triodes are adopted as the first pull-up transistors (Q10, Q20), and NPN type triodes are adopted as the pull-down transistors (Q19, Q29), the first transistors (Q11, Q21) and the second transistors (Q12, Q22). One or more of the first pull-up transistors (Q10, Q20), the pull-down transistors (Q19, Q29), the first transistors (Q11, Q21) and the second transistors (Q12, Q22) may also use corresponding MOS transistors, and the first switching transistors (M10, M20) may also use corresponding transistors.
The working principle of the embodiment shown in fig. 4 is further described below. The circuit is divided into two identical parts (stage 1, stage 2 as shown), the operation of stage 2 depending on whether M20 is on or not, and whether M20 is on or not depending on whether Q19 is on or not in stage 1. I.e. stage 1 works first, stage 2 works then, stage 1 works sequentially with stage 2, and the three LED sub-lamp groups in each stage are also sequentially lighted. Specifically, in the T1-T2 stage, CLK is high, CE1 and CE2 are low, Q10, M10, Q11 and Q12 in the 1 st stage are on, LED1 is lighted, in the T2-T3 stage, CE1 becomes high, Q11 is off, CE2 is low, so that Q12 remains on, LED1 and LED2 are lighted, in the T3-T4 stage, CLK becomes low, CE2 becomes high, but because of the feedback resistor R4, M10 remains on, Q12 is off, and LEDs 1,2 and 3 are turned on. Since the voltage drop is generated after the LED3 is turned on, the voltage drop acts on R7 and R25, Q19 is also conducted, and M20 in the 2 nd stage has a conducting condition, since the CLK is low, M20 cannot be conducted, and M20 is conducted after the CLK becomes high again and starts the next period, and the 2 nd stage starts the process of sequentially turning on the LEDs 4, 5 and 6 in the same order as the 1 st stage. The conduction of the Q19 can not lead the Q11 and the Q12 to be conducted again, so that the LEDs 2 and 3 can not be extinguished after being lightened, and the LED lightening process is ensured to be a unidirectional sequential lightening process. In the figure, six LED sub-lamp groups are sequentially lighted, and if the LED sub-lamp groups are required to be added, the same cascade circuit can be added after the 2 nd stage. According to the embodiment, the sequential lighting flowing effect of all LED sub-lamp groups can be realized under the control of the three pulse signals CLK, CE1 and CE2, a plurality of paths of D triggers are not needed, the circuit design is simplified, and the circuit cost is saved.
In this embodiment, the voltage between the base (B) and the emitter (E) of the transistor or between the gate (G) and the source (S) of the MOS transistor is changed by using an externally input clock control signal (clock signal or a derivative control signal thereof) or by using voltage level conversion inside the circuit, so as to control the conduction of the transistor or the MOS transistor. In this embodiment, after stage 1, the emitter (E) of the transistor or the source (S) of the MOS transistor, which is usually fixed to the reference ground of the circuit, is designed to float, and the corresponding level changes according to the externally input clock control signal or the voltage change of the internal circuit, and when the emitter (E) of the transistor or the source (S) of the MOS transistor is set to a high level, the transistor is not turned on even if the base (B) of the transistor or the gate (G) of the MOS transistor is set to a high level. Based on the improvement, the voltage of the emitter electrode (E) or the source electrode (S) of the transistor can be controlled by using a clock control signal in the same-stage circuit so as to control the conduction of the transistor, and the base electrode (B) or the grid electrode (G) of the transistor with the variable voltage of the emitter electrode (E) or the source electrode (S) can be locked into a low level by the last transistor after all transistors of the driving control subunit of the same stage are conducted, so that the state of the transistor in the stage is locked into the non-conduction state, and the lighting state of all LED sub-lamp groups in the same stage is always kept after the LED sub-lamp groups are lighted. The sequential lighting between the stages is also realized by controlling the voltages of the emitters of the corresponding transistors or the sources of the MOS transistors. When the last transistor of the previous stage is not conducted, the emitter of the transistor or the drain of the MOS transistor of the next stage is at a high level, and at this time, the change of the clock signal cannot conduct the transistor or the MOS transistor of the next stage. And after the last transistor of the previous stage is conducted, the emitter or the source of the first transistor or the MOS transistor of the following stage is pulled down, so that the first transistor or the MOS transistor of the following stage has a conducting condition. At this time, a clock signal is added to sequentially turn on the transistors of the following stage, so that the LED sub-lamp groups in the circuit are sequentially turned on to generate the effect of flowing water.
Referring to fig. 5, a circuit diagram of a second embodiment of the running water type dynamic display lamp control circuit of the present invention is shown, which shows all circuits of level 1 and part of circuits of level 2, wherein the structures of level 1 and level 2 are the same, and undescribed details of level 2 can be shown by referring to level 1. Unlike the embodiment shown in fig. 4, in this embodiment, each stage of LED lamp group includes a first LED sub-lamp group LED1, a second LED sub-lamp group LED2, a third LED sub-lamp group LED3, and a fourth LED sub-lamp group LED4, a fifth LED sub-lamp group LED5, and a sixth LED sub-lamp group LED6, which are sequentially connected, and the driving control subunit includes a first transistor (Q10, Q20), a first switching transistor (M10, M20), and a pull-down transistor (Q19 only) which are the same as those shown in fig. 4, and further includes a first transistor (Q11 only, Q18 only, M12 only, and Q12 only) in the drawing.
In this embodiment, the control terminal of the first transistor Q11 is coupled to the output terminal of the second power voltage V2 and the first terminal of the pull-down transistor Q19, and the first terminal thereof is electrically connected to the negative electrode of the second LED sub-lamp group LED2 and the second terminal thereof is for receiving the first control signal CE1. Wherein, the high level pulse width of the clock signal CLK is twice the low level pulse width thereof, the first control signal CE1 is derived from the clock signal CLK, and the low level thereof has a hold time half of the high level duration of the clock signal CLK.
The control terminal of the second pull-up transistor Q18 is coupled to the output terminal of the first power voltage V1, the first terminal thereof is electrically connected to the anode of the fourth LED sub-lamp group LED4, and the second terminal thereof is coupled to the output terminal of the first power voltage V1 (similar to the connection of the first pull-up transistor Q11).
The gate of the second NMOS transistor M12 is coupled to the negative electrode of the second LED sub-lamp set LED2 and is coupled to the ground, the drain thereof is coupled to the output terminal of the first power voltage V1, and the source thereof is grounded.
The control terminal of the second transistor Q12 is coupled to the output terminal of the second power voltage V2 and the first terminal of the pull-down transistor Q19, and the first terminal thereof is electrically connected to the negative electrode of the fourth LED sub-light group LED4, and the second terminal thereof is for receiving the second control signal CE2. Wherein the second control signal CE2 is derived from the clock signal CLK and is opposite in timing to the clock signal CLK.
In this embodiment, the control terminal of the pull-down transistor Q19 is coupled to the positive electrode of the fifth LED sub-lamp group LED5 and is also coupled to the ground terminal. In this embodiment, each stage of LED lamp sets sequentially works, and the first LED sub-lamp set LED1 and the second LED sub-lamp set LED2 in each stage of LED lamp set are simultaneously turned on, the third LED sub-lamp set LED3 and the fourth LED sub-lamp set LED4 are simultaneously turned on, the fifth LED sub-lamp set LED5 and the sixth LED sub-lamp set LED6 are simultaneously turned on, and the three LED sub-lamp sets sequentially turn on. That is, in the present embodiment, in the LED lamp groups of the same stage, two LED sub-lamp groups are simultaneously lighted as one group.
Specifically, in this embodiment, the first pull-up transistor Q10, the pull-down transistor Q19, the first transistor Q11, the second pull-up transistor Q18, and the second transistor Q12 all use transistors. The base electrode of the triode is used as a control end of the corresponding transistor, the collector electrode of the triode is used as a first end of the corresponding transistor, and the emitter electrode of the triode is used as a second end of the corresponding transistor. In this embodiment, the first switching tube (M10, M20) is an NMOS tube, a gate of the NMOS tube is used as a control end of the first switching tube, a drain of the NMOS tube is used as a first end of the first switching tube, and a source of the NMOS tube is used as a second end of the first switching tube. The first pull-up transistor Q10 and the second pull-up transistor Q18 are PNP type triodes, and the pull-down transistor Q19, the first transistor Q11 and the second transistor Q12 are NPN type triodes.
The working principle of the embodiment shown in fig. 5 is further described below. The circuit is divided into two identical parts (stage 1, stage 2 as shown), the operation of stage 2 depending on whether M20 is on or not, and whether M20 is on or not depending on whether Q19 is on or not in stage 1. The 1 st stage works first, the 2 nd stage works then, the 1 st stage and the 2 nd stage work sequentially, and two groups of six LED sub-lamps in each stage are sequentially lighted. Specifically, in the T1-T2 stage, CLK is high, CE1 and CE2 are low, Q10, M10 and Q11 in the 1 st stage are on, LED1 and LED2 are on, in the T2-T3 stage, CE1 is high, Q11 is off, LED3 is on, M12 is on after LED3 is on, since CE2 is still kept low, Q12 is on, LED4 is on, in the T3-T4 stage, CLK is low, CE2 is high, but because of the feedback resistor R4, M10 is kept on, Q12 is off, and LEDs 5 and 6 are on. Since the voltage drop is generated after the LEDs 5 and 6 are lighted, the Q19 is also conducted, so that the M20 in the 2 nd stage has a conducting condition, and since the CLK is at a low level, the M20 cannot be conducted, and after the CLK becomes high again and starts the next period, the M20 is conducted, and the 2 nd stage starts the same sequence lighting process as the 1 st stage. Q19 is conducted, and meanwhile Q11 and Q12 are not conducted again, so that LEDs 3-6 are not extinguished after being lightened, and the LED is lightened in a unidirectional sequential mode.
Referring to fig. 6, a circuit diagram of a third embodiment of the flow-through dynamic display lamp control circuit of the present invention is shown. The difference from the embodiment shown in fig. 4 is that in this embodiment, the drive control subunit includes only the first pull-up transistors (Q10, Q20), the first switching transistors (M10, M20), and the pull-down transistors (Q19, Q29) that are the same as those shown in fig. 4. In this embodiment, the three LED sub-lamp groups are simultaneously lighted, that is, in the figure, LED1, LED2, and LED3 are in one group, and LED4, LED5, and LED6 are in one group, and one group is sequentially lighted. In this case the clock control signal and the drive control circuit for each group of LED lamps becomes much simpler.
In this embodiment, the control terminal of the first switching transistor M10 of the current driving control subunit is coupled to the output terminal of the clock signal CLK1, and the control terminal of the first switching transistor M20 of the next driving control subunit is coupled to the first control signal CLK2. Wherein, the high and low level pulse widths of the clock signal CLK1 are the same, and the first control signal CLK2 is derived from the clock signal CLK1 and is opposite to the clock signal CLK1 in timing.
In this embodiment, the control terminal of the pull-down transistor Q19 of the current stage driving control subunit is coupled to the positive electrode of the third LED sub-lamp group LED3 or the positive electrode of the second LED sub-lamp group LED2, and is also coupled to the ground terminal. In this embodiment, the first LED sub-lamp group LED1, the second LED sub-lamp group LED2, and the third LED sub-lamp group LED2 are simultaneously turned on. That is, in the present embodiment, in the LED lamp groups of the same stage, 3 LED sub-lamp groups are simultaneously lighted as a group.
Specifically, in this embodiment, the first pull-up transistors (Q10, Q20) and the pull-down transistors (Q19, Q29) are all transistors. The base electrode of the triode is used as a control end of the corresponding transistor, the collector electrode of the triode is used as a first end of the corresponding transistor, and the emitter electrode of the triode is used as a second end of the corresponding transistor. In this embodiment, the first switching tube (M10, M20) is an NMOS tube, a gate of the NMOS tube is used as a control end of the first switching tube, a drain of the NMOS tube is used as a first end of the first switching tube, and a source of the NMOS tube is used as a second end of the first switching tube. The first pull-up transistors (Q10, Q20) are PNP type triodes, and the pull-down transistors (Q19, Q29) are NPN type triodes.
The working principle of the embodiment shown in fig. 6 is further described below. The circuit is divided into two identical parts (stage 1, stage 2 as shown), the operation of stage 2 depending on whether M20 is on or not, and whether M20 is on or not depending on whether Q19 is on or not in stage 1. I.e. stage 1 works first, stage 2 works then, stage 1 works sequentially with stage 2, and 3 LED sub-lamp groups in each stage are lighted at the same time. Specifically, when CLK1 is high, Q10 and M10 in stage 1 are turned on, and M10 is kept in a locked on state by feedback of feedback resistor R4, and LED1, LED2, and LED3 are turned on, and at the same time, Q19 is turned on due to voltage drop generated after LED2 and LED3 are turned on, and the source of M20 in stage 2 is pulled low, so that M20 in stage 2 has a conduction condition, and since CLK2 is low, M20 cannot be turned on yet because the source of M20 is pulled down by Q19, ready for conduction when CLK2 is high. While Q29 in stage 2 is not conductive, the gate of M30 in stage 3 of the next cascade is connected to CLK1, but since Q29 in stage 2 is not conductive, M30 in stage 3 is also not conductive. Likewise, if there are other stages in the cascade following stage 3, they will not be turned on. Then CLK1 goes low and CLK2 goes high, M10 in stage 1 gets feedback voltage by means of feedback resistor R4 to keep on, thereby keeping LEDs 1-3 on, and stage 2 repeats the stage 1 on process and prepares for stage 3 on after CLK1 goes high again. Each of the cascaded drive control subcircuits is thus turned on sequentially under the control of CLK1, CLK 2.
Because the LED sub-lamp groups in each stage are connected in series, and the LED lamps have forward conduction voltage drop when being lighted. If only one current limiting resistor is used at the second end of the first pull-up transistor of each stage driving control subunit, the current flowing through each LED sub-lamp group when being lighted is different, and the brightness of each LED sub-lamp group is different. Preferably, a constant current control transistor is configured at the pull-up transistor of each stage to form a constant current source module, so that the current of each LED sub-lamp group which is sequentially conducted in each stage is equal, and the current of each LED sub-lamp group when being sequentially lighted is approximately equal by configuring current limiting resistors with different resistance values at the output end of each LED sub-lamp group.
Referring to fig. 7, a circuit diagram of a fourth embodiment of the flow-through dynamic display lamp control circuit of the present invention is shown. In this embodiment, a constant current control transistor Q17 is added to each driving control subunit (for example, the driving control subunit 221 shown in the drawing), the control end of the constant current control transistor Q17 is electrically connected to the second end of the first pull-up transistor Q10, the first end of the constant current control transistor Q17 is electrically connected to the control end of the first pull-up transistor Q10, and the second end of the constant current control transistor Q10 is electrically connected to the output end of the first power supply voltage V1, where the current directions of the electrodes of the first pull-up transistor Q10 and the constant current control transistor Q17 are the same when they work.
Specifically, the constant current control transistor Q17 also adopts a triode, the base electrode of the triode is used as the control end of the corresponding transistor, the collector electrode of the triode is used as the first end of the corresponding transistor, and the emitter electrode of the triode is used as the second end of the corresponding transistor. For example, the first pull-up transistor Q10 and the constant current control transistor Q17 are NPN transistors, and the base electrode of the constant current control transistor Q17 is electrically connected to the emitter electrode of the first pull-up transistor Q10, the collector electrode thereof is electrically connected to the base electrode of the first pull-up transistor Q10, and the emitter electrode thereof is electrically connected to the output terminal of the first power supply voltage V1.
By adding the constant current control transistor Q17, a constant current source module can be formed with the corresponding first pull-up transistor Q10, so that when the LED sub-lamp groups controlled by the drive control sub-unit in the circuit are sequentially turned on, the current flowing through each LED sub-lamp group is equal (i1=i2=i3), that is, the brightness of all the LED sub-lamp groups is consistent after the LED sub-lamp groups are sequentially turned on.
Referring to fig. 8, a circuit diagram of a fifth embodiment of a running water type dynamic display lamp control circuit according to the present invention is shown. In this embodiment, in each driving control subunit (for example, the driving control subunit 221 is shown in the drawing), current limiting resistors R101, R102, R103 with different resistance values are configured at the output end of each LED sub-lamp group, so as to implement constant current. Specifically, a first end of the first transistor Q11 is electrically connected to a negative electrode of the first LED sub-lamp group LED1 through a corresponding first current limiting resistor R101, first ends of the second transistors Q12 and Q are electrically connected to a negative electrode of the second LED sub-lamp group LED2 through a corresponding second current limiting resistor R102, and a negative electrode of the third LED sub-lamp group LED3 is electrically connected to a ground through a corresponding third current limiting resistor R103. The resistances of the first current limiting resistor R101, the second current limiting resistor R102, and the third current limiting resistor R103 are configured, so that when the first LED sub-lamp group LED1, the second LED sub-lamp group LED2, and the third LED sub-lamp group LED3 are sequentially turned on in turn, the currents flowing through each LED sub-lamp group are equal (i1=i2=i3), that is, the brightness of all LED sub-lamp groups is uniform after being sequentially turned on.
Referring to fig. 9, a schematic diagram of an embodiment of an LED lamp set according to the present invention is shown. In this embodiment, each stage of LED lamp group includes a plurality of LED sub-lamp groups connected in series, and each LED sub-lamp group includes a plurality of LED lamps connected in parallel with each other. That is, each LED sub-lamp group in the circuit can be regarded as an LED sub-lamp group formed by connecting one or more LED lamps in parallel, each LED sub-lamp group is connected in series, and the number of the LED sub-lamp groups connected in series is determined by the working voltage range provided by the vehicle body and the forward conduction voltage drop of the LEDs. If the working voltage range provided by the vehicle body is 9V-16V and the forward conduction voltage drop of the LED sub-lamp group (single LED lamp or a plurality of LED lamps connected in parallel) is 2.3V, three LED sub-lamp groups can be connected in series. The transistors in the figure are used to sequentially illuminate the transistors of the individual LED sub-lamp groups as switches. In the above circuit example of the present invention, only one LED lamp is schematically shown in one LED sub-lamp group, but each LED sub-lamp group may be regarded as being formed by connecting one or several LED lamps in parallel, and each LED sub-lamp group may be simultaneously lighted. The design can lead the cost of the control circuit to be unchanged, increase the number of the LED lamps which can be lightened, and save the cost of the circuit.
The foregoing is merely illustrative of the preferred embodiments of this invention, and it will be appreciated by those skilled in the art that variations and modifications may be made without departing from the principles of the invention, and such variations and modifications are to be regarded as being within the scope of the invention.
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