CN112134043A - PCIE connectors and electronic equipment - Google Patents
PCIE connectors and electronic equipment Download PDFInfo
- Publication number
- CN112134043A CN112134043A CN202010885864.1A CN202010885864A CN112134043A CN 112134043 A CN112134043 A CN 112134043A CN 202010885864 A CN202010885864 A CN 202010885864A CN 112134043 A CN112134043 A CN 112134043A
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- routing
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- pairs
- pcie connector
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- 238000013461 design Methods 0.000 abstract description 9
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000002699 waste material Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/02—Contact members
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/70—Coupling devices
- H01R12/71—Coupling devices for rigid printing circuits or like structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
- H01R13/40—Securing contact members in or to a base or case; Insulating of contact members
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R2201/00—Connectors or connections adapted for particular applications
- H01R2201/06—Connectors or connections adapted for particular applications for computer periphery
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- Details Of Connecting Devices For Male And Female Coupling (AREA)
Abstract
The invention provides a PCIE connector and electronic equipment, belonging to the technical field of electronic equipment, wherein the connector comprises two routing layers, and an insulating layer is formed on two sides of each routing layer; each routing layer is provided with 2n rows of routing lines, and each row of routing lines comprises a plurality of groups of routing line pairs; a plurality of pairs of pins are formed on the surface of the insulating layer, and each routing pair is connected with one pair of pins. The invention can effectively reduce the number of stacked boards, reduce the volume of the connector and adjust the volume of the connector according to the space between the board cards, thereby realizing more full utilization of the space between the board cards, solving the technical problem of waste of design cost and greatly reducing the production cost of the connector.
Description
Technical Field
The present invention relates to the field of electronic devices, and in particular, to a PCIE connector and an electronic device.
Background
With the continuous development of computer technology, cloud computing technology is applied to more and more scenes, and a large number of servers are needed for work. In the high-speed signal interconnection topological link design of the server, the board card density is increased along with the increase of the signal rate, and the application of high-density connectors in the board card interconnection design is more and more.
In practical application, the width and the depth of the existing high-density connector are fixed, the balance of stacking and space of the server cannot be considered, the space between the board cards cannot be effectively utilized, the design scheme of the server board card is often required to be changed to meet the application of the high-density connector, and the technical problem of waste of design cost is caused.
Disclosure of Invention
The invention aims to provide a high-speed serial computer expansion bus (PCIE) connector, which solves the technical problem that the space between board cards cannot be fully utilized to cause the waste of design cost.
In a first aspect, the PCIE connector provided in the present invention is applied to connection between boards, and the PCIE connector includes:
two wiring layers, wherein an insulating layer is formed on two sides of each wiring layer;
each routing layer is provided with 2n rows of routing lines, and each row of routing lines comprises a plurality of groups of routing line pairs;
a plurality of pairs of pins are formed on the surface of the insulating layer, and each routing pair is connected with one pair of pins.
Further, a null pin is formed between each pair of pins in the same column.
Furthermore, each routing layer is provided with two rows of routing lines, and each row of routing lines comprises eight groups of routing line pairs.
Furthermore, the distance between two wires in each wire pair is more than 20 mils, and the distance between the same row of pin pairs is more than 70 mils.
Further, the size of the PCIE connector is 900 mils by 700 mils.
Furthermore, each routing layer is provided with four rows of routing wires, and each row of routing wires comprises four groups of routing wire pairs.
Furthermore, the distance between two wires in each wire pair is more than 20 mils, and the distance between the same row of pin pairs is more than 150 mils.
Further, the size of the PCIE connector is 650mil by 1400 mil.
In a second aspect, the present invention further provides an electronic device, including the PCIE connector in the first aspect.
The PCIE connector provided by the invention comprises two routing layers, wherein each routing layer comprises 2n routing lines, and each routing line comprises a plurality of groups of routing line pairs. All high-speed lines are arranged on the two routing layers, so that the number of stacked plates can be effectively reduced, the manufacturing cost is reduced, meanwhile, the size of the connector can be effectively reduced, the size of the connector can be adjusted according to the distance between the plate cards, the space between the plate cards can be fully utilized, the technical problem of waste of design cost is solved, and the production cost of the connector is greatly reduced.
Accordingly, the electronic device provided by the embodiment of the invention also has the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic view of a connector according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another connector according to an embodiment of the present invention.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "comprising" and "having," and any variations thereof, as referred to in embodiments of the present invention, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The first embodiment is as follows:
the invention provides a PCIE connector which is applied to the connection between board cards, and comprises:
two wiring layers, wherein an insulating layer is formed on two sides of each wiring layer;
each routing layer has 2n rows of routing lines, and each row of routing lines comprises a plurality of groups of routing line pairs, such as routing line pair 14 in fig. 1, such as routing line pair 24 in fig. 2;
a plurality of pairs of pins are formed on the surface of the insulating layer, and each routing pair is connected with one pair of pins.
PCIE belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, and connected equipment distributes independent channel bandwidth and does not share bus bandwidth, and the PCIE supports the functions of active power management, error report, end-to-end reliable transmission, hot plug, service quality and the like. The 2n rows of routing lines and the multiple groups of routing line pairs in each row can expand the number of high-speed lines on each routing line layer, and the number of stacked plates can be effectively reduced by the two routing line inner layers, so that the size and the production cost of the connector are reduced.
As shown in fig. 1, a null pin 12 is formed between each pair of pins in the same column, and a null pin 23 is also formed between none of the pairs of pins in fig. 2.
And a certain distance is kept between each pair of routing pairs, so that the signal crosstalk between the routing pairs is reduced, and the processing is more convenient. The method ensures the signal integrity of the link and avoids signal failure caused by crosstalk; meanwhile, the routing space on the board card is reasonably utilized, and the cost waste caused by over-design is avoided; the method is simple, efficient and easy to implement, and meanwhile, the reliability of system design is improved.
Each routing layer is provided with two rows of routing lines, and each row of routing lines comprises eight groups of routing line pairs.
The distance between two wires in each wire pair is more than 20 mils, and the distance between the pin pairs in the same row is more than 70 mils.
The size of the PCIE connector is 900 mils by 700 mils.
The connector with internal routing of 2 × 8pair is described above, as shown in fig. 1, the connector includes two routing layers inside, a first routing layer 11 with a solid line of 2 × 8pair, and a second routing layer 13 with a dotted line of 2 × 8pair, each routing layer has two rows of routing lines, each row of routing line includes eight routing line pairs, the number of high-speed lines on each routing layer can be effectively expanded, the thickness of the connector is reduced, and the size is reduced.
In another possible embodiment, as shown in fig. 2, each routing layer has four rows of traces, and each row of traces includes four sets of trace pairs.
The distance between two wires in each wire pair is more than 20 mils, and the distance between the pin pairs in the same row is more than 150 mils.
The size of the PCIE connector is 650 mils by 1400 mils.
The connector with internal routing of 2 × 4pair is described above, as shown in fig. 2, the connector internally includes two routing layers, a first routing layer 21 with a solid line of 2 × 4pair, and a second routing layer 22 with a dotted line of 2 × 4pair, each routing layer has four rows of routing lines, each row of routing line includes four routing line pairs, the number of high-speed lines on each routing layer can be effectively expanded, the width of the connector is reduced, and the depth of the connector is increased, so that the volume of the connector is reduced, and the production cost of the connector is reduced.
Example two:
an embodiment of the present invention provides an electronic device, which may be a server, a switch, or the like, where the electronic device includes a PCIE connector provided in the foregoing embodiment.
The electronic device provided by the embodiment of the present invention has the same technical features as the PCIE connector provided by the above embodiment, so that the same technical problems can be solved, and the same technical effects can be achieved.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; and the modifications, changes or substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention. Are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. The PCIE connector is characterized in that the PCIE connector is applied to connection between boards and comprises:
two wiring layers, wherein an insulating layer is formed on two sides of each wiring layer;
each routing layer is provided with 2n rows of routing lines, and each row of routing lines comprises a plurality of groups of routing line pairs;
a plurality of pairs of pins are formed on the surface of the insulating layer, and each routing pair is connected with one pair of pins.
2. The PCIE connector of claim 1, wherein a null pin is formed between each pair of pins in the same column.
3. The PCIE connector of claim 1, wherein each routing layer has two rows of traces, each row of traces comprising eight sets of trace pairs.
4. The PCIE connector of claim 3, wherein the pitch of two traces in each trace pair is 20 mils or more, and the pitch between pin pairs in the same row is 70 mils or more.
5. The PCIE connector of claim 3, wherein the PCIE connector has a size of 900 mils by 700 mils.
6. The PCIE connector of claim 1, wherein each routing layer has four rows of traces, each row of traces comprising four sets of trace pairs.
7. The PCIE connector of claim 6, wherein the pitch of two traces in each trace pair is more than 20 mils, and the pitch between pin pairs in the same row is more than 150 mils.
8. The PCIE connector of claim 6, wherein the PCIE connector has a size of 650 mils 1400 mils.
9. An electronic device comprising a PCIE connector of any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010885864.1A CN112134043A (en) | 2020-08-28 | 2020-08-28 | PCIE connectors and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010885864.1A CN112134043A (en) | 2020-08-28 | 2020-08-28 | PCIE connectors and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112134043A true CN112134043A (en) | 2020-12-25 |
Family
ID=73847100
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010885864.1A Pending CN112134043A (en) | 2020-08-28 | 2020-08-28 | PCIE connectors and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112134043A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719605A (en) * | 2010-02-01 | 2010-06-02 | 曙光信息产业(北京)有限公司 | Connector based on large-current transmission among multiple circuit boards |
| CN110831318A (en) * | 2018-08-13 | 2020-02-21 | 中兴通讯股份有限公司 | PCB and electronic equipment |
| CN111244652A (en) * | 2020-01-09 | 2020-06-05 | 珠海格力电器股份有限公司 | Paster connector and driving and controlling integrated equipment |
-
2020
- 2020-08-28 CN CN202010885864.1A patent/CN112134043A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719605A (en) * | 2010-02-01 | 2010-06-02 | 曙光信息产业(北京)有限公司 | Connector based on large-current transmission among multiple circuit boards |
| CN110831318A (en) * | 2018-08-13 | 2020-02-21 | 中兴通讯股份有限公司 | PCB and electronic equipment |
| CN111244652A (en) * | 2020-01-09 | 2020-06-05 | 珠海格力电器股份有限公司 | Paster connector and driving and controlling integrated equipment |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201225 |
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| RJ01 | Rejection of invention patent application after publication |