CN112133715B - Image sensor structure - Google Patents

Abstract

The invention discloses an image sensor structure, which comprises the following components from bottom to top: a substrate and a dielectric layer; the substrate is provided with a first photosensitive device, the dielectric layer is provided with a metal interconnection layer and a second photosensitive device, the second photosensitive device is arranged in a groove, the groove is positioned in the dielectric layer above the first photosensitive device, and the second photosensitive device is coupled with the first photosensitive device through the groove and led out through the metal interconnection layer; wherein the second photosensitive device comprises a plurality of pn junctions which are horizontally distributed and are coupled. The invention can effectively improve the light absorption efficiency, the performance of the sensor such as full well capacity and the like, and can greatly improve the absorption efficiency of near infrared light.

Description

Image sensor structure

Technical Field

The invention relates to the technical field of semiconductor integrated circuits and sensors, and in particular to a high-performance CMOS image sensor structure with high absorption efficiency.

Background technique

The photosensitive device of a traditional CMOS image sensor is usually a pn junction. The photosensitive pn junction manufactured using conventional processes generally has a strong absorption rate and quantum efficiency only for visible light, and some light will pass through the photosensitive area and cause loss.

In addition, for near-infrared light, a depletion region with a thickness of several microns to more than ten microns or even thicker is required for effective absorption, but it is difficult to achieve this structure with the injection process of the existing CMOS process.

Summary of the invention

The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide an image sensor structure.

To achieve the above object, the technical solution of the present invention is as follows:

An image sensor structure comprises, from bottom to top: a substrate and a dielectric layer; a first photosensitive device is arranged on the substrate, a metal interconnection layer and a second photosensitive device are arranged on the dielectric layer, the second photosensitive device is arranged in a groove, the groove is located in the dielectric layer above the first photosensitive device, the second photosensitive device is coupled to the first photosensitive device through the groove, and is led out through the metal interconnection layer; wherein the second photosensitive device contains a plurality of horizontally distributed and coupled pn junctions.

Further, the first photosensitive device is provided with a first N-type photosensitive region, a first P-type region is provided on the substrate above the first N-type photosensitive region, the second photosensitive device is alternately provided with a plurality of second N-type photosensitive regions and second P-type regions to form a plurality of pn junctions, each of the second N-type photosensitive regions is connected as a whole from its upper end and covers the surface of the pn junction, each of the second P-type regions is connected as a whole from its lower end and covers the bottom surface of the groove, an isolation layer is provided between the first photosensitive device and the second photosensitive device, and the second P-type region is connected to the first P-type region through the isolation layer.

Furthermore, a third P-type region is provided on the substrate on one side of the first N-type photosensitive region, and a shallow trench isolation is provided in the third P-type region for isolating the first N-type photosensitive region used for photosensitivity from other external regions, and the second P-type region is connected to the third P-type region through the isolation layer, and the third P-type region extends along the bottom and sidewalls of the shallow trench isolation to be connected to the first P-type region.

Furthermore, a silicide region is provided on the third P-type region, and the third P-type region is connected to the metal interconnection layer through the silicide region.

Furthermore, the second P-type region is connected to the third P-type region and the silicide region through an open region provided in the isolation layer.

Furthermore, the surfaces of the second N-type photosensitive region and the dielectric layer are covered with a fourth P-type region, a fifth P-type region is provided on one side of the fourth P-type region, the lower end of the fifth P-type region extends from the fourth P-type region and is connected to the metal interconnection layer located in the dielectric layer.

Furthermore, the fourth P-type region is covered with a dielectric protection layer.

Further, the substrate is a P ^- type doped substrate, the first P-type region, the third P-type region and the fifth P-type region are P ⁺ -type doped regions, the fourth P-type region is a P ^- type doped region, the portion of the second P-type region located in the pn junction is a P-type doped region, the portion of the second P-type region located on the bottom surface of the groove is a P ⁺ -type doped region, and the second N-type photosensitive region is an N-type doped region; the material of the second N-type photosensitive region, the second P-type region and the fourth P-type region is amorphous silicon.

Furthermore, the second P-type region also extends from the bottom of the trench to the sidewall of the trench, and extends from above one sidewall of the trench to the surface of the dielectric layer, and is connected to the fourth P-type region and the fifth P-type region.

Furthermore, the second N-type photosensitive region sequentially passes through the second P-type region, the isolation layer and the first P-type region to connect with the first N-type photosensitive region.

Furthermore, a first transfer transistor is provided on the substrate, and the first light sensitive device is coupled to the first transfer transistor.

Furthermore, the second N-type photosensitive region is separated from the first P-type region and the first N-type photosensitive region by the isolation layer.

Furthermore, a first transfer transistor is disposed on the substrate, the first light-sensitive device is coupled to the first transfer transistor, a second transfer transistor is disposed on the fourth P-type region, and the second light-sensitive device is coupled to the second transfer transistor.

Furthermore, the second transfer transistor is arranged on the other side of the fourth P-type region, the second transfer transistor is formed with a gate electrode on the dielectric protection layer outside the trench, and a drain is formed in the fourth P-type region, the second N-type photosensitive region extends outward from the upper end of the trench and forms a partial overlap under the gate electrode to form a source of the second transfer transistor, and the fourth P-type region located between the source and the drain forms a channel of the second transfer transistor.

Furthermore, the pn junction completely fills the trench.

Furthermore, the pn junction partially fills the trench, forming a recessed structure on the surface of the second N-type photosensitive region located in the trench.

Furthermore, the upper end of the fifth P-type region is led out from the surface of the dielectric protection layer through an electrode.

It can be seen from the above technical solutions that the present invention forms an additional light absorption layer (second light sensitive device) containing multiple pn junctions by using the gap of the dielectric layer above the photosensitive area (first light sensitive device area) of the traditional image sensor structure through a groove filling method, and couples with the light absorption layer of the existing photosensitive device (first light sensitive device), thereby effectively improving the efficiency of light absorption and sensor performance such as full well capacity, and can greatly improve the absorption efficiency of near-infrared light. In addition, the light absorption layer can be formed using low-temperature amorphous silicon materials, which will not affect the thermal budget of existing devices and effectively control costs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of the structure of an image sensor according to a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram of the structure of an image sensor according to a second preferred embodiment of the present invention.

FIG. 3 is a schematic diagram of the structure of an image sensor according to a third preferred embodiment of the present invention.

FIG. 4 is a schematic diagram of the structure of an image sensor according to a fourth preferred embodiment of the present invention.

Detailed ways

The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

It should be noted that in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly represent the structure of the present invention for the convenience of explanation, the structures in the accompanying drawings are not drawn according to general proportions, and are partially enlarged, deformed and simplified. Therefore, it should be avoided to understand this as a limitation of the present invention.

In the following specific implementation of the present invention, please refer to FIG1, which is a schematic diagram of an image sensor structure of a preferred embodiment of the present invention. As shown in FIG1, an image sensor structure of the present invention can adopt, for example, a back-illuminated (BSI) structure, which includes from bottom to top: a substrate 1 and a dielectric layer 11, and the incident light irradiates the image sensor from the back side of the substrate 1 (the lower surface of the substrate 1 shown in the figure).

Please refer to FIG. 1. The substrate 1 may be, for example, a silicon substrate 1, but is not limited thereto. The substrate 1 may be a P ^- type doped substrate (P-(sub)) 1, and a first photosensitive device is disposed on the front surface of the substrate 1. The dielectric layer 11 may be an interlayer dielectric layer 11, and a metal interconnection layer 6 and a second photosensitive device are disposed on the dielectric layer 11.

A groove is provided on the dielectric layer 11, the groove is located in the dielectric layer 11 above the first photosensitive device, and the second photosensitive device is provided in the groove. The second photosensitive device is coupled to the first photosensitive device through the groove, and the second photosensitive device and the first photosensitive device are led out through the metal interconnection layer 6.

Please refer to Fig. 1. The first photosensitive device may have a first N-type photosensitive region (PD) 18; a first P-type region 17 may be provided on the substrate 1 above the first N-type photosensitive region 18, and the first P-type region 17 may be a thin layer of P ⁺ doped region.

The second photosensitive device contains a plurality of horizontally distributed and coupled pn junctions. For example, the second photosensitive device may be provided with a plurality of second N-type photosensitive regions 9 and second P-type regions 15 alternately to form a plurality of pn junctions, that is, the second P-type region 15 serves as the p-region of the pn junction, and the second N-type photosensitive region 9 serves as the n-region of the pn junction. Among them, each second N-type photosensitive region 9 is connected as a whole from its upper end and covers the upper surface of each pn junction. At the same time, each second P-type region 15 is connected as a whole from its lower end, located on the lower surface of each pn junction, and covers the bottom surface of the groove, thereby forming a plurality of pn junction structures in the shape of comb teeth.

The part of the second P-type region located in the pn junction (p-region) is a P-type doped region, and the part of the second P-type region located on the bottom surface of the trench is a P ⁺ -type doped region. The second N-type photosensitive region is an N-type doped region.

The portion of the second P-type region 15 located on the bottom surface of the trench may be a thin layer of P ⁺ -type doped region, and may extend from the bottom of the trench to the sidewall of the trench to surround the pn junction in the trench.

The second N-type photosensitive region 9 and the second P-type region 15 may be made of amorphous silicon (amorphous-Si) or the like.

An isolation layer 16 is provided between the first photosensitive device and the second photosensitive device, that is, the isolation layer 16 is provided on the front surface of the substrate 1. The isolation layer 16 can be made of conventional dielectric materials, such as silicon dioxide.

Please refer to FIG. 1. In this embodiment, the isolation layer 16 may be provided with two open areas 5 and 14. Among them, the second N-type photosensitive region 9 in a pn junction may sequentially pass through the second P-type region 15 and a right open area 14 on the isolation layer 16, enter the substrate 1 downward, and continue to pass through the first P-type region 17 to connect with the first N-type photosensitive region 18. In addition, on the area where the second N-type photosensitive region 9 passes through the surface of the substrate 1, that is, on the open area 14, the first P-type region 17 should have a necessary opening so that the second N-type photosensitive region 9 is isolated from the first P-type region 17 when passing through the first P-type region 17.

The second N-type photosensitive regions 9 in the plurality of pn junctions may also be introduced into the substrate 1 through different open areas in the above manner to be connected to the first N-type photosensitive regions 18 .

A third P-type region 2 is provided on the substrate 1 on the left side of the first N-type photosensitive region 18, and a shallow trench isolation (STI) 3 is provided in the third P-type region 2. The shallow trench isolation (STI) 3 is used to isolate the first N-type photosensitive region 18 used for light sensing from other external regions. The third P-type region 2 can be a P ⁺ -type doped region. The lower end of the third P-type region 2 extends upward along the bottom and sidewall of the shallow trench isolation 3 to connect with one end of the first P-type region 17. The second P-type region 15 covering the bottom of the trench can sequentially pass through the bottom of the trench and an open area 5 on the left side of the isolation layer 16, enter the substrate 1 downward, and connect the upper end of the third P-type region 2.

The second P-type regions 15 in the plurality of pn junctions may also be introduced into the substrate 1 through different open areas in the above manner to be connected to the third P-type region 2 .

Furthermore, a metal silicide region 4 may be provided on the third P-type region 2 , and the third P-type region 2 is connected to the bottom metal layer of the metal interconnection layer 6 located in the dielectric layer 11 through the metal silicide region 4 .

Furthermore, the second P-type region 15 can be connected to the third P-type region 2 and the silicide region 4 through the open region 5 provided in the isolation layer 16 (the open region 5 is, for example, located between the silicide region 4 and a shallow trench isolation 3 on the left), thereby realizing the lead-out of the photosensitive device.

Please refer to Figure 1. As an optional implementation, the pn junction can completely fill the trench. At this time, the second N-type photosensitive region 9 in each pn junction is connected from its upper end to form a whole, extends from the upper end of the trench to the outside of the trench, and at least partially covers the surface of the dielectric layer 11.

The surface of the second N-type photosensitive region 9 connected as one body may be further covered with a fourth P-type region 10, which may be a P ^- type doped region. The material of the fourth P-type region 10 may also be amorphous silicon.

A fifth P-type region 7 may be provided on the left side of the fourth P-type region 10, and the fifth P-type region 7 may be a P ⁺ -type doped region. The lower end of the fifth P-type region 7 extends from the fourth P-type region 10 and is connected to the uppermost metal layer of the metal interconnection layer 6 in the dielectric layer 11. In addition, the thin layer portion of the second P-type region 15 located on the bottom surface of the groove may also extend from the left side wall of the groove and further extend to the surface of the dielectric layer 11, that is, the extension portion of the second P-type region 15 is between the fifth P-type region 7 and the dielectric layer 11, thereby forming a connection with the fourth P-type region 10 and the fifth P-type region 7 at the same time.

The lateral pn junction structure of the second photosensitive device can be realized by in-situ doping during film formation or by ion implantation, wherein the activation of impurities after ion implantation can be achieved in whole or in part by laser annealing.

For example, p ⁺ amorphous silicon can be first deposited in the trench as the part of the second P-type region 15 located on the bottom surface of the trench; then N-type amorphous silicon is deposited; then, a vertical p-type region is formed by implantation, that is, the part of the second P-type region 15 located in the pn junction (p region), and connected to the P ⁺ region at the bottom of the trench; then N-type amorphous silicon is deposited, so that the N-type amorphous silicon below is connected from its upper end as a whole. Finally, shallowly doped P-type amorphous silicon is deposited to form the fourth P-type region 10.

Optionally, p ⁺ amorphous silicon may be deposited in the groove first, and then N-type amorphous silicon may be deposited; then, a through groove may be formed in the N-type amorphous silicon by etching; then, p-type amorphous silicon may be deposited in the through groove and connected to the P ⁺ amorphous silicon at the bottom; then, excess p-type amorphous silicon on the surface of the N-type amorphous silicon may be etched away, and then N-type silicon crystal and lightly doped P-type amorphous silicon may be deposited.

Alternatively, p ⁺ amorphous silicon may be deposited in the trench first, followed by a thinner layer of N-type amorphous silicon; then, a vertical p-type region is formed by implantation, and connected to the p ⁺ amorphous silicon at the bottom of the trench to form the first pn junction layer; then, a thinner layer of N-type amorphous silicon is deposited, and a vertical p-type region is formed by implantation, and connected to the P-type region in the first pn junction layer below to form the second pn junction layer. This process is repeated until the trench is filled. Then, N-type silicon crystal and lightly doped P-type amorphous silicon are deposited.

Furthermore, a dielectric protection layer 8 may be covered on the fourth P-type region 10. The dielectric protection layer 8 may be made of conventional dielectric materials, such as silicon dioxide.

The upper end of the fifth P-type region 7 can be led out from the surface of the dielectric protection layer 8 through the electrode 21 .

Please refer to FIG1. On the substrate 1 on the right side of the first N-type photosensitive region 18, a first transmission transistor (TX) and an N-type floating diffusion region (FD) 12 may also be provided. The gate 13 of the first transmission transistor may also be made of amorphous silicon, and the floating diffusion region 12 may be an N ⁺ type doped region. The first photosensitive device may be coupled to the source of the first transmission transistor in a conventional manner.

In the above state, a fully connected structure is formed between the first photosensitive device on the substrate 1 and the second photosensitive device on the dielectric layer 11 , and signals of the first photosensitive device and the second photosensitive device can be output through the shared first transfer transistor and the N-type suspended diffusion region 12 .

A shallow trench isolation (STI) may be further provided on the right side of the floating diffusion region 12 as shown in the figure.

Please refer to FIG. 2. In another embodiment of the present invention, only one open area 5 is provided in the isolation layer 16. In this state, only the second P-type region 15 is connected to the third P-type region 2 and the silicide region 4 through the open area 5 provided in the isolation layer 16. The second N-type photosensitive region 9 is separated from the first P-type region 17 and the first N-type photosensitive region 18 by the isolation layer 16. That is, the first photosensitive device located on the substrate 1 and the second photosensitive device located on the dielectric layer 11 are in an incompletely connected state.

At this time, the signal in the second light-sensitive device will be outputted through a second transmission transistor alone.

Specifically, the second transfer transistor may be disposed on the other side of the fourth P-type region 10 and located outside the trench.

As an optional embodiment, the second transfer transistor can use the extension of the dielectric protection layer 8 toward the right side as the gate dielectric 81, and form a gate electrode 19 on the dielectric protection layer outside the trench. The gate electrode 19 can be made of amorphous silicon. In addition, the second transfer transistor can use the extension of the fourth P-type region 10 toward the right side to form a channel 101 below the gate electrode 19, and form an N ⁺ region 20 by ion implantation in the extension of the fourth P-type region 10 on the right side of the channel 101, and this N ⁺ region 20 partially overlaps with the gate electrode 19 to form the drain (suspended diffusion region) 20 of the second transfer transistor. At the same time, the second N-type photosensitive region 9 extends from the upper end of the trench to the right side, and its extension 91 partially overlaps below the gate electrode 19 to form the source 91 of the second transfer transistor.

Please refer to Figures 3 and 4. As a further optional implementation, when the first photosensitive device and the second photosensitive device form a fully connected state (Figure 1) or an incompletely connected state (Figure 2), the pn junction can also be partially filled in the groove (for example, half-filled), so as to form a recess 22 structure on the surface of the second N-type photosensitive region 9 connected as one in the groove. In this state, the fourth P-type region 10 and the dielectric protection layer 8 will conformally cover the surface of the recess 22 of the second N-type photosensitive region 9.

The advantage of the above implementation is that it can avoid the problem that when the second light-sensitive device has a thick structure, a large high voltage needs to be applied to form a depletion region. However, applying a high voltage requires special processes and devices, which increases complexity and cost.

Other aspects of the image sensor structure in the embodiments of FIGS. 2 to 4 may be the same as the image sensor structure in the embodiment of FIG. 1 , and will not be described in detail.

The above are only preferred embodiments of the present invention, and the embodiments are not intended to limit the protection scope of the present invention. Therefore, all equivalent structural changes made using the description and drawings of the present invention should be included in the protection scope of the present invention.

Claims (16)

1. An image sensor structure comprising, from bottom to top: a substrate and a dielectric layer; the substrate is provided with a first photosensitive device, the dielectric layer is provided with a metal interconnection layer and a second photosensitive device, the second photosensitive device is arranged in a groove, the groove is positioned in the dielectric layer above the first photosensitive device, and the second photosensitive device is coupled with the first photosensitive device through the groove and led out through the metal interconnection layer; wherein the second photosensitive device comprises a plurality of pn junctions which are horizontally distributed and coupled;

the first light-sensitive device is provided with a first N-type light-sensitive region, a first P-type region is arranged on the substrate above the first N-type light-sensitive region, the second light-sensitive device is alternately provided with a plurality of second N-type light-sensitive regions and second P-type regions to form a plurality of pn junctions, and an isolation layer is arranged between the first light-sensitive device and the second light-sensitive device;

The substrate on one side of the first N-type photosensitive region is provided with a third P-type region, shallow trench isolation is arranged in the third P-type region and used for isolating the first N-type photosensitive region used for sensitization from other external regions, the second P-type region is connected with the third P-type region through the isolation layer, and the third P-type region extends to be connected with the first P-type region along the bottom and the side wall of the shallow trench isolation.

2. The image sensor structure of claim 1 wherein each of said second N-type photosensitive regions is integral from an upper end thereof and overlies a surface of said pn junction, and each of said second P-type regions is integral from a lower end thereof and overlies a bottom surface of said trench.

3. The image sensor structure of claim 1, wherein a silicide region is disposed on the third P-type region, and the third P-type region is connected to the metal interconnection layer through the silicide region.

4. The image sensor structure of claim 3, wherein the second P-type region connects the third P-type region and the silicide region through an opening region provided in the isolation layer.

5. The image sensor structure of claim 2, wherein a fourth P-type region is covered on the surfaces of the second N-type photosensitive region and the dielectric layer, a fifth P-type region is disposed in one side of the fourth P-type region, and a lower end of the fifth P-type region extends from the fourth P-type region and is connected to the metal interconnection layer in the dielectric layer.

6. The image sensor structure of claim 5, wherein the fourth P-type region is covered with a dielectric protection layer.

7. The image sensor structure of claim 5, wherein the substrate is a P ^- -doped substrate, the first, third, and fifth P-type regions are P ⁺ -doped regions, the fourth P-type region is a P ^- -doped region, a portion of the second P-type region in the pn junction is a P-doped region, a portion of the second P-type region on the bottom surface of the trench is a P ⁺ -doped region, and the second N-type photosensitive region is an N-doped region; the second N-type photosensitive region, the second P-type region and the fourth P-type region are made of amorphous silicon.

8. The image sensor structure of claim 5 wherein the second P-type region further extends from above the bottom of the trench to above the sidewalls of the trench and from above one side of the trench to above the surface of the dielectric layer, and is connected to the fourth P-type region and the fifth P-type region.

9. The image sensor structure of claim 2 or 6, wherein the second N-type photosensitive region is connected to the first N-type photosensitive region through the second P-type region, the isolation layer and the first P-type region in sequence.

10. The image sensor structure of claim 9, wherein a first transfer transistor is disposed on the substrate, the first photosensitive device being coupled to the first transfer transistor.

11. The image sensor structure of claim 6, wherein the second N-type photosensitive region is separated from the first P-type region and the first N-type photosensitive region by the isolation layer.

12. The image sensor structure of claim 11, wherein a first transfer transistor is disposed on the substrate, the first photosensitive device is coupled to the first transfer transistor, a second transfer transistor is disposed on the fourth P-type region, and the second photosensitive device is coupled to the second transfer transistor.

13. The image sensor structure of claim 12, wherein the second transfer transistor is disposed on the other side of the fourth P-type region, the second transfer transistor has a gate electrode formed on the dielectric protection layer outside the trench, and a drain electrode formed in the fourth P-type region, the second N-type photosensitive region extends outward from the trench upper end and partially overlaps under the gate electrode to form a source electrode of the second transfer transistor, and the fourth P-type region between the source electrode and the drain electrode forms a channel of the second transfer transistor.

14. The image sensor structure of claim 2 or 8, wherein the pn junction completely fills the trench.

15. The image sensor structure of claim 2 or 8, wherein the pn junction partially fills the trench, forming a recessed structure on a surface of the second N-type photosensitive region located in the trench.

16. The image sensor structure of claim 6, wherein an upper end of the fifth P-type region is led out from the surface of the dielectric protection layer through an electrode.