CN112131828B - Data processing method, device and equipment and readable storage medium - Google Patents

Abstract

The application discloses a data processing method, a data processing device, data processing equipment and a readable storage medium. The method disclosed by the application is applied to an FPGA verification platform and comprises the following steps: receiving a data frame to be processed by utilizing at least one data interface; storing the data frame into a memory in the FPGA verification platform according to the storage starting and stopping address; performing matching verification on the data frame, and if the matching verification fails, reserving the storage start-stop address so as to store a new data frame to the memory in an overlay manner according to the storage start-stop address; and counting the residual space of the memory in real time, and if the residual space is smaller than a preset threshold, reading the stored data frame in the memory according to the read start-stop address, and updating the read start-stop address and the storage start-stop address. The data processing device, the data processing equipment and the readable storage medium have the technical effects that the same memory is managed by using the storage starting and stopping address and the reading starting and stopping address, and more storage resources can be prevented from being occupied by data.

Description

A data processing method, apparatus, device and readable storage medium

technical field

The present application relates to the field of computer technology, and in particular, to a data processing method, apparatus, device, and readable storage medium.

Background technique

The verification platform based on FPGA (Field Programmable Gate Array) can flexibly modify the code for testing. The host computer sends the test-related data to the FPGA verification platform through the data interface on the FPGA verification platform, so that the FPGA verification platform can use the data to perform code testing.

Before the processor in the FPGA verification platform processes the data, the data will be stored in the cache first. After filtering out redundant frames or error frames in the data, the valid data will be stored in another cache. Therefore, in the FPGA verification platform, set If the second-level cache is installed, the test-related data will be written to different caches, occupying more storage resources and reducing the performance of the FPGA verification platform.

Therefore, in the FPGA verification platform, how to prevent data from occupying more storage space is a problem that needs to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present application is to provide a data processing method, apparatus, device and readable storage medium, so as to avoid data occupying more storage space in the FPGA verification platform. Its specific plan is as follows:

In the first aspect, the present application provides a data processing method, which is applied to an FPGA verification platform, including:

Receive data frames to be processed using at least one data interface;

According to the storage start and end addresses, the data frame is stored in the memory in the FPGA verification platform;

Perform a matching check on the data frame, and if the data frame matching check fails, the storage start and end addresses are reserved, so that when a new data frame is received by using the data interface, the storage start and end addresses are stored according to the storage start and end addresses. overwriting the new data frame to the memory;

Count the remaining space of the memory in real time, if the remaining space is less than the preset threshold, after reading the stored data frame in the memory according to the read start and end addresses, update the read start and end addresses and the storage start and end address.

Preferably, the performing matching check on the data frame includes:

According to preset matching rules, feature value matching is performed on the data frame, and a CRC check is performed on the data frame;

If the feature value matches and passes the CRC check, it is determined that the data frame matching check passes; otherwise, it is determined that the data frame matching check fails.

Preferably, it also includes:

If the data frame matching check is passed, the storage start and end addresses are updated to obtain the update start and end addresses, so that when the new data frame is received by using the data interface, the new data frame is stored according to the update start and end addresses. data frame.

Preferably, the updating of the storage start and end addresses to obtain the update start and end addresses includes:

The update start and end addresses are calculated according to the storage start and end addresses and the address length occupied by the data frame.

Preferably, before reading the stored data frame in the memory according to the read start and end addresses, the method further includes:

Control the data interface to be disabled.

Preferably, after updating the read start and end addresses and the storage start and end addresses, the method further includes:

Control the data interface enable.

Preferably, before storing the data frame to the memory in the FPGA verification platform according to the storage start and end addresses, the method further includes:

Performing bit width conversion on the data frame to adapt to the bus bit width in the FPGA verification platform;

The data frame is encapsulated according to a preset format.

In a second aspect, the present application provides a data processing device, which is applied to an FPGA verification platform, including:

a receiving module for receiving the data frame to be processed by using at least one data interface;

a storage module, configured to store the data frame in the memory in the FPGA verification platform according to the storage start and end addresses;

A matching verification module is used to perform matching verification on the data frame. If the data frame matching verification fails, the storage start and end addresses are reserved, so that when a new data frame is received using the data interface , overwriting the new data frame to the memory according to the storage start and end addresses;

The management module is used to count the remaining space of the memory in real time. If the remaining space is less than a preset threshold, after reading the stored data frames in the memory according to the read start and end addresses, update the read start and end addresses and the storage start and end addresses.

In a third aspect, the present application provides a data processing device, including:

memory for storing computer programs;

A processor for executing the computer program to implement the data processing method disclosed above.

In a fourth aspect, the present application provides a readable storage medium for storing a computer program, wherein when the computer program is executed by a processor, the data processing method disclosed above is implemented.

It can be seen from the above solutions that the present application provides a data processing method, which is applied to an FPGA verification platform, including: receiving a data frame to be processed by using at least one data interface; storing the data frame to the FPGA verification according to the storage start and end addresses The memory in the platform; the data frame is checked for matching, and if the matching check of the data frame fails, the storage start and end addresses are reserved, so that when a new data frame is received by using the data interface, according to The storage start and end addresses are overlaid to store the new data frame to the memory; the remaining space of the memory is counted in real time, and if the remaining space is less than a preset threshold, the memory is read according to the read start and end addresses. After the stored data frame, the read start and end addresses and the storage start and end addresses are updated.

It can be seen that after receiving the data frame to be processed by using at least one data interface, the present application first stores the data frame memory according to the storage start and end addresses, and the stored data frame may be valid or invalid at this time. The data frame is subsequently matched and checked. If the data frame does not pass the match check, it means that the stored data frame is invalid. Therefore, the storage start and end addresses are reserved. When a new data frame is received through the data interface, the storage start and end addresses are used. Overwrite stores new data frames to the same memory, overwriting invalid data frames already stored in memory. In addition, the present application counts the remaining space of the memory in real time. If the remaining space is less than the preset threshold, after reading the stored data frame in the memory according to the read start and end addresses, update the read start and end addresses and the storage start and end addresses, and then follow the new data frames. The start and end addresses of the storage are overwritten to store new data frames, thereby improving the utilization of storage space. The application effectively manages the same storage space by using the storage start and end addresses and the read start and end addresses, improves the utilization rate of the memory, saves the storage space during storage, and after reading the data in it, the storage start and end addresses can be updated in time, so that the next time When a new data frame is stored, the new data frame is overwritten, thereby improving the performance of the FPGA verification platform. Moreover, there is no need to set up multi-level caches in the FPGA verification platform, and it can be implemented using one cache space. Using a buffer space also saves the hardware circuit layout space of the FPGA verification platform, and provides convenience for the design and implementation of the FPGA verification platform.

Correspondingly, a data processing apparatus, device and readable storage medium provided by the present application also have the above technical effects.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only It is an embodiment of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without any creative effort.

1 is a flowchart of a data processing method disclosed in the application;

2 is a schematic diagram of a data frame structure disclosed in the application;

FIG. 3 is a schematic framework diagram of a data processing solution disclosed in the application;

Fig. 4 is the method flow chart of carrying out data processing in the frame shown in Fig. 3;

5 is a schematic diagram of a data processing device disclosed in the application;

FIG. 6 is a schematic diagram of a data processing device disclosed in this application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

At present, before the processor in the FPGA verification platform processes the data, the data will be stored in the cache first. After filtering out redundant frames or error frames in the data, the valid data will be stored in another cache. Therefore, in the FPGA verification platform , the test-related data will be written multiple times, occupying more storage resources and reducing the performance of the FPGA verification platform. To this end, the present application provides a data processing solution, which can prevent data from occupying more storage space of the FPGA verification platform.

Referring to FIG. 1 , an embodiment of the present application discloses a data processing method, which is applied to an FPGA verification platform, including:

S101. Use at least one data interface to receive a data frame to be processed.

It should be noted that the data interface is a peripheral interface of the FPGA verification platform, and the interface may be EMAC (Ethernet Media Access Controller, Ethernet Media Access Controller) or the like. Multiple data interfaces can be set in the FPGA verification platform, and each data interface can be regarded as a data channel.

S102, store the data frame in the memory in the FPGA verification platform according to the storage start and end addresses.

The storage start and end addresses include a storage start address and a storage end address. The storage start address is used to mark the start position of the available space in the memory, and the storage end address is used to mark the end position of the stored data frame in the memory. The memory is specifically the memory in the FPGA verification platform. In the initial state, both the storage start address and the storage end address can be set to 0. During normal use, storage start address = storage end address + 1.

In a specific implementation manner, before storing the data frame in the memory in the FPGA verification platform according to the storage start and end addresses, the method further includes: performing bit width conversion on the data frame to adapt to the bus bit width in the FPGA verification platform; Format encapsulates the data frame. For the specific bit width conversion method, reference may be made to the prior art, and details are not described herein again in this specification.

After the data frame is encapsulated according to the preset format, the encapsulated data frame is stored, which is convenient for the processor to distinguish different data frames when reading the data frames. Specifically, reference can be made to FIG. 2 for the preset format. The channel number in FIG. 2 is the channel identification code, that is, the identification code of the data interface. Frame data is the received valid data frame. The frame length is divided into two types: the unit of byte and the unit of storage bit width (such as 32 bits), which are used for data extraction and data transmission. The frame header checksum is a 16-bit checksum of the channel number and the above two frame lengths. The frame header and frame trailer can be customized, and the frame header, frame trailer, frame structure, and checksum can effectively distinguish different data frames. The frame end checksum is the 32-bit checksum of the frame data part. Generally, the frame end checksum can be obtained by accumulating the first data of the frame data part to the last data. The preset format can be flexibly modified according to the actual application.

S103, performing a matching check on the data frame, if the data frame matching check fails, the storage start and end addresses are reserved, so that when a new data frame is received by using the data interface, the new data frame is overwritten according to the storage start and end addresses to memory.

In a specific implementation manner, performing a matching check on the data frame includes: matching the data frame with eigenvalues according to a preset matching rule, and performing CRC checking on the data frame; if the eigenvalue matching passes and the CRC check passes , it is determined that the data frame matching check has passed; otherwise, it is determined that the data frame matching check has not passed.

Among them, the preset matching rule may preset characteristic values to be matched, such as: frame header, frame type, frame length, etc. of the received data frame. The feature value matching on the data frame can detect whether the data frame includes the data to be processed by the processor in the FPGA verification platform, and can also detect whether the data frame is the data frame to be processed by the processor in the FPGA verification platform. For details of the CRC check, reference may be made to the prior art, and details are not described herein again in this specification.

In a specific embodiment, if the data frame matching check passes, it indicates that the data frame is valid, so the storage start and end addresses are updated to obtain the update start and end addresses, so that when a new data frame is received by using the data interface, the update start and end addresses are Store the new data frame to memory. Wherein, updating the storage start and end addresses to obtain the update start and end addresses includes: calculating the update start and end addresses according to the storage start and end addresses and the address length occupied by the data frame. For example: the storage start address in the storage start and end addresses is: 0, and the storage end address is: 0. Assuming that a data frame occupies 3 address lengths, after storing the first data frame, update the storage start address in the start and end addresses. It is: 0+3+1=4, and the storage end address is: 0+3=3. If you want to store a new data frame later, start from the fourth address.

If the data frame matching check is passed, while updating the storage start and end addresses, it is also necessary to update the read start and end addresses at the same time, so that the processor can read the data.

S104. Count the remaining space of the memory in real time, and if the remaining space is less than the preset threshold, after reading the stored data frame in the memory according to the read start and end addresses, update the read start and end addresses and the storage start and end addresses.

It should be noted that the read start and end addresses include a read start address and a read end address. The read start address is used to mark the start position of the first data frame to be read by the processor, and the read end address is used to mark the end position of the stored data frame in the memory. Generally, the read end address - the read start address = the total amount of all data frames to be read by the current processor (assuming that the read end address is greater than the read start address).

Updating the read start and end addresses can be performed according to the following process: Assuming that the read end address is 10, the read start address is 5, and the data frame read by the processor occupies 3 address lengths, then after the processor reads the data frame , the read start address is updated to 5+3=8, and the read end address remains unchanged (assuming no valid data frame is stored in this process). If there is a valid data frame stored in this process, then the current read end address plus the address length occupied by the currently stored data frame is the updated read end address.

In a specific implementation manner, before reading the stored data frame in the memory according to the read start and end addresses, the method further includes: controlling the data interface to be disabled. In a specific implementation manner, after updating the read start and end addresses and the storage start and end addresses, the method further includes: controlling data interface enable.

In order to avoid memory overflow, the remaining space of the memory in the FPGA verification platform can be counted in real time. If the remaining space is less than the preset threshold, it means that the memory is about to be filled. In order to ensure the writing of subsequent data frames, you can first control the data interface to enable Enabled, that is, the data interface is prohibited from continuing to receive data frames. When the stored data frame in the memory is read according to the read start and end addresses, and the read start and end addresses and the storage start and end addresses are updated, the data interface can be controlled to be enabled.

After the processor in the FPGA verification platform processes the stored data frame in the memory in time, the read start and end addresses and the storage start and end addresses can be updated in time, thereby facilitating the writing of subsequent data frames. The memory may be RAM (Random Access Memory, random access memory).

It can be seen that, after receiving the data frame to be processed by using at least one data interface, the embodiment of the present application first stores the data frame memory according to the storage start and end addresses, and the stored data frame may be valid or invalid at this time. The data frame is subsequently matched and checked. If the data frame does not pass the match check, it means that the stored data frame is invalid. Therefore, the storage start and end addresses are reserved. When a new data frame is received through the data interface, the storage start and end addresses are used. Overwrite stores new data frames to the same memory, overwriting invalid data frames already stored in memory. In addition, the present application counts the remaining space of the memory in real time. If the remaining space is less than the preset threshold, after reading the stored data frame in the memory according to the read start and end addresses, update the read start and end addresses and the storage start and end addresses, and then follow the new data frames. The start and end addresses of the storage are overwritten to store new data frames, thereby improving the utilization of storage space. The application effectively manages the same storage space by using the storage start and end addresses and the read start and end addresses, improves the utilization rate of the memory, saves the storage space during storage, and after reading the data in it, the storage start and end addresses can be updated in time, so that the next time When a new data frame is stored, the new data frame is overwritten, thereby improving the performance of the FPGA verification platform. Moreover, there is no need to set up multi-level caches in the FPGA verification platform, and it can be implemented using one cache space. Using a buffer space also saves the hardware circuit layout space of the FPGA verification platform, and provides convenience for the design and implementation of the FPGA verification platform.

The embodiment of the present application discloses a data processing solution applied to an FPGA verification platform. For a schematic diagram of the framework of the solution, please refer to FIG. 3 .

Figure 3 shows only one data channel (corresponding to a data interface). On this data channel, a matching verification module, a storage module, a storage address maintenance module, and a flow control management module can be configured. These modules can directly communicate with the processor for data processing. interact.

Of course, multiple data channels can also be set, and a matching verification module, a storage module, a storage address maintenance module, and a flow control management module can be configured on each data channel. Multiple data channels can also share the matching verification module, storage module, storage address maintenance module, and flow control management module.

The matching verification module, storage module, storage address maintenance module, and flow control management module can also be packaged into a reusable whole, so as to design and implement an FPGA verification platform.

Specifically, the matching verification module performs feature value matching and CRC verification on the received data frame in real time, and the matching and verification results directly control the storage process of the data frame.

The storage address maintenance module maintains the storage start and end addresses and the read start and end addresses of the RAM memory in the FPGA verification platform in real time, and can manage the storage space of the memory.

The flow control management module can calculate the information such as the amount of stored data and the space margin according to the start and end addresses of storage and the start and end addresses of reading, and determine whether to generate an interruption according to these information to control the data transmission flow. You can also configure matching rules, storage thresholds, timing interrupt thresholds, data reception enable, and so on.

The storage module (ie RAM memory) is the only storage space in the FPGA verification platform. It is a true dual-port RAM and supports asynchronous read and write clocks. The data bit width and the total memory capacity vary with the bus characteristics and application environment in the FPGA verification platform. configuration.

Referring to Figure 4, the specific process of data processing based on the above framework includes:

After the data interface receives the data frame, the data frame will be transmitted to the matching verification module, the storage module, and the storage address maintenance module, so that the matching verification module, the storage module, and the storage address maintenance module can work in parallel as much as possible.

Wherein, the storage address maintenance module realizes the control of the storage space of the memory by maintaining the storage start and end addresses. Initially, the storage start and end addresses (including the start address stt_addr and the end address end_addr) are 0. After receiving the data frame, regardless of whether the data frame is valid or not, the data frame is stored first. When the storage ends, the last ram_addr (the RAM storage address in the RAM memory) of the stored data frame is obtained as end_addr. At this time, if the storage address maintenance module receives a signal that the data frame is valid (the signal is output by the matching check module), the value of stt_addr is updated to end_addr+1, thereby obtaining the update start and end addresses. If the storage address maintenance module receives a signal that the data frame is invalid at this time, stt_addr and end_addr remain unchanged, so that when a new data frame is received, the data frame is stored from the original stt_addr, so that the invalid data can be overwritten frame. In this way, the receiving processing and buffering of data frames are implemented in the same storage space. Each update of the storage start and end addresses marks the completion of the entire frame storage of a valid data frame.

In order to ensure the integrity and accuracy of the data frame storage, the flow control management module calculates the memory space margin (free_len) in real time, and compares it with the margin threshold (free_thrhd, which can be set to the maximum frame length of the data frame). When free_len is less than or equal to the margin threshold, the data interface is prohibited from receiving data after the current frame is stored until free_len is greater than the margin threshold. If free_len is greater than the margin threshold, an overflow risk alarm is generated to indicate the risk of frame loss.

At this time, the processor in the FPGA verification platform can be controlled to read and process the data in the memory in time to free up the storage space of the memory. Specifically, the following two data reading mechanisms can be used: first, the processor reads the data in the memory regularly, and the specific interval can be set according to the actual application; second, configure the storage threshold (ram_thrhd), when the memory has been When the amount of stored data is greater than the storage threshold, an interrupt is generated to prompt the processor to read the stored data in the memory. Before each time the processor reads data, it first determines the total length (data_len) of the data frame stored in the memory, and reads the data according to the total length. The length of each stored data frame is fixed, so after the total length of the stored data frames is determined, the number of data frames to be read can be calculated accordingly, so as to read the data frames one by one. After the processor reads and processes the stored data in the memory, it can control the data interface to continue to receive data.

It should be noted that, in the process of the processor reading the stored data in the memory, the read start and end addresses need to be updated accordingly. Specifically, when the processor reads data regularly, or when a storage threshold interrupt occurs, the processor first determines the total length of the stored data frame. Specifically, the record read start address (ram_stt_addr) is the start position of the first data frame to be read currently, and the read end address (ram_end_addr) is the end position of the currently stored last data frame. According to ram_stt_addr The deviation from ram_end_addr can be calculated to obtain the total length of the stored data frame, that is, the total length of data that can be read this time, data_len (the address cycle of the storage unit needs to be considered, and the calculation method is selected according to the binary size). After that, the ram_stt_addr value can be incremented with the data read by the processor, or updated to the original ram_end_addr value temporarily stored after the read is completed. In this way, the processor reads the previously stored frame data, and the ram_stt_addr is shifted accordingly. As the data is received, it waits for the next data read, and so on. The deviation of the addresses ram_addr and ram_stt_addr occupied when the current data frame is stored, the real-time space occupation can be calculated (the address cycle of the storage unit needs to be considered, and the calculation method is selected according to the size of the binary value). The total memory capacity minus this value is Get the space allowance free_len.

Among them, because the RAM address is recycled, when calculating the length of the stored data frame, it is necessary to consider the address cycle of the storage unit. For example, if the depth of RAM is 8192 (the total number of addresses), the address range is 0 to 8191, and the next address loops to 0 after the data is stored in 8191. Therefore, when calculating data_len, you need to consider the size of the read start address and read end address.

Specifically, before storing the received data frame, the data frame can also be encapsulated according to a preset format. During the encapsulation process, redundant data in the original received data frame can be discarded, and different received data frames with the same feature value can also be After fusion, it is encapsulated in a frame to improve the proportion of effective data in a frame.

In this embodiment, the FPGA verification platform can also be used as a verification platform for an ASIC (Application Specific Integrated Circuit). The processor may be a BOOM processor, and the processor may be used in combination with a RISC-V instruction set, a BSD (Berkeley Software Distribution) protocol, and the like.

It can be seen that this embodiment can manage the data storage process based on one storage space, and realize the matching, verification, storage, flow control, and data statistics of data frames, and different processes can also be executed in parallel based on actual conditions. At the same time, it also supports channel expansion, with high real-time performance, low resource occupation, and simple usage, which is suitable for complex data interfaces with large amounts of data.

The following describes a data processing apparatus provided by an embodiment of the present application, and a data processing apparatus described below and a data processing method described above can be referred to each other.

Referring to FIG. 5 , an embodiment of the present application discloses a data processing apparatus, which is applied to an FPGA verification platform, including:

a receiving module 501, configured to receive a data frame to be processed by using at least one data interface;

The storage module 502 is used to store the data frame in the memory in the FPGA verification platform according to the storage start and end addresses;

The matching verification module 503 is used to perform matching verification on the data frame. If the matching verification of the data frame fails, the storage start and end addresses are reserved, so that when a new data frame is received by the data interface, the storage start and end addresses are covered according to the Store the new data frame to memory;

The management module 504 is used to count the remaining space of the memory in real time. If the remaining space is less than the preset threshold, after reading the stored data frame in the memory according to the read start and end addresses, update the read start and end addresses and the storage start and end addresses.

In a specific embodiment, the matching verification module is specifically used for:

Carry out feature value matching on the data frame according to the preset matching rule, and perform CRC check on the data frame; if the feature value matches and passes the CRC check, it is determined that the data frame matches the check; otherwise, It is determined that the data frame matching check fails.

In a specific embodiment, it also includes:

an update module, configured to update the storage start and end addresses if the data frame matching check is passed, to obtain the update start and end addresses, so that when the new data frame is received by the data interface, the update start and end addresses are The address stores the new data frame.

In a specific embodiment, the update module is specifically used for:

The update start and end addresses are calculated according to the storage start and end addresses and the address length occupied by the data frame.

In a specific embodiment, it also includes:

A disabling module, configured to control the data interface to be disabled.

In a specific embodiment, it also includes:

The enabling module is used to control the enabling of the data interface.

In a specific embodiment, it also includes:

a bit-width conversion module for performing a bit-width conversion on the data frame to adapt to the bus bit-width in the FPGA verification platform;

An encapsulation module, configured to encapsulate the data frame according to a preset format.

For the more specific working process of each module and unit in this embodiment, reference may be made to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

It can be seen that this embodiment provides a data processing apparatus, which can cover the stored invalid data frames, thereby saving storage space and resources and improving the performance of the FPGA verification platform. There is also no need to set up multi-level caches in the FPGA verification platform, and it can be achieved using one cache space. Using a buffer space also saves the hardware circuit layout space of the FPGA verification platform, and provides convenience for the design and implementation of the FPGA verification platform.

The following describes a data processing device provided by an embodiment of the present application. The data processing device described below and the data processing method and apparatus described above can be referred to each other.

Referring to FIG. 6 , an embodiment of the present application discloses a data processing device, including:

memory 601, used to save computer programs;

The processor 602 is configured to execute the computer program to implement the method disclosed in any of the foregoing embodiments.

A readable storage medium provided by an embodiment of the present application is introduced below. A readable storage medium described below and a data processing method, apparatus, and device described above can be referred to each other.

A readable storage medium for storing a computer program, wherein when the computer program is executed by a processor, the data processing methods disclosed in the foregoing embodiments are implemented. For the specific steps of the method, reference may be made to the corresponding content disclosed in the foregoing embodiments, which will not be repeated here.

References in this application to "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that data so used may be interchanged under appropriate circumstances so that the embodiments described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method or apparatus comprising a series of steps or elements is not necessarily limited to those steps or elements expressly listed , but may include other steps or elements not expressly listed or inherent to these processes, methods or apparatus.

It should be noted that the descriptions involving "first", "second", etc. in this application are only for the purpose of description, and should not be construed as indicating or implying their relative importance or implying the number of indicated technical features . Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In addition, the technical solutions between the various embodiments can be combined with each other, but must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that the combination of such technical solutions does not exist. , is not within the scope of protection claimed in this application.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other.

The steps of a method or algorithm described in conjunction with the embodiments disclosed herein may be directly implemented in hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other in the technical field. in any other form of readable storage medium that is well known.

The principles and implementations of the present application are described herein by using specific examples. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. There will be changes in the specific implementation and application scope. To sum up, the content of this specification should not be construed as a limitation on the application.

Claims (8)

1. A data processing method is applied to an FPGA verification platform and comprises the following steps:

receiving a data frame to be processed by utilizing at least one data interface;

storing the data frame to a memory in the FPGA verification platform according to a storage starting and stopping address;

performing matching check on the data frame, if the data frame matching check is not passed, reserving the storage start-stop address so as to store a new data frame to the memory in an overlay manner according to the storage start-stop address when the data interface is used to receive the new data frame;

counting the residual space of the memory in real time, and if the residual space is smaller than a preset threshold, updating the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address;

wherein, still include:

if the data frame matching check is passed, updating the storage starting and stopping address to obtain an updated starting and stopping address, so that when the new data frame is received by using the data interface, the new data frame is stored according to the updated starting and stopping address;

wherein the updating the storage start-stop address to obtain an updated start-stop address includes:

and calculating the updating start-stop address according to the storage start-stop address and the address length occupied by the data frame.

2. The data processing method of claim 1, wherein the performing the match check on the data frame comprises:

performing characteristic value matching on the data frame according to a preset matching rule, and performing CRC (cyclic redundancy check) on the data frame;

if the characteristic value matches and the CRC passes, determining that the data frame matches and checks; otherwise, determining that the data frame matching check is not passed.

3. The data processing method of claim 1, wherein before reading the stored data frame in the memory according to the read start-stop address, further comprising:

controlling the data interface to be disabled.

4. The data processing method according to claim 3, wherein after the updating the read start-stop address and the store start-stop address, further comprising:

controlling the data interface to be enabled.

5. The data processing method according to claim 3, wherein before storing the data frame to the memory in the FPGA verification platform according to the storage start-stop address, the method further comprises:

performing bit width conversion on the data frame to adapt to the bus bit width in the FPGA verification platform;

and packaging the data frame according to a preset format.

6. A data processing device is applied to an FPGA verification platform and comprises:

the receiving module is used for receiving a data frame to be processed by utilizing at least one data interface;

the storage module is used for storing the data frame to a memory in the FPGA verification platform according to the storage starting and stopping address;

the matching check module is used for carrying out matching check on the data frame, and if the matching check of the data frame fails, the storage starting and ending address is reserved so that when a new data frame is received by using the data interface, the new data frame is stored to the memory in an overlapping manner according to the storage starting and ending address;

the management module is used for counting the residual space of the memory in real time, and if the residual space is smaller than a preset threshold, the management module updates the read start-stop address and the storage start-stop address after reading the stored data frame in the memory according to the read start-stop address;

wherein, still include:

the updating module is used for updating the storage starting and stopping address to obtain an updated starting and stopping address if the data frame matching check is passed, so that the new data frame is stored according to the updated starting and stopping address when the new data frame is received by using the data interface;

wherein, the update module is specifically configured to:

and calculating the updating start-stop address according to the storage start-stop address and the address length occupied by the data frame.

7. A data processing apparatus, characterized by comprising:

a memory for storing a computer program;

a processor for executing the computer program to implement the data processing method of any one of claims 1 to 5.

8. A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the data processing method of any one of claims 1 to 5.

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