CN112118028A - Method for realizing automatic measurement of low-speed serial data bit rate - Google Patents

Abstract

The invention discloses a method for realizing automatic measurement of low-speed serial data bit rate. The method filters burrs or jitters of input data by an input data passing jitter removal module, dynamically and automatically measures and identifies the bit width of input serial data by a bit width identification module, utilizes a bit counting accumulation module to accumulate and count data edges based on the identified bit width, utilizes a clock period counting accumulation module to accumulate and count a main clock, resets if the bit width identification module dynamically identifies a new bit width, and calculates and outputs a measurement result by adopting a result calculation module according to a bit accumulation counting result and a clock accumulation counting result. The method realizes the automatic measurement of the bit rate of the low-speed serial data based on the FPGA, and can obtain the precision superior to the common clock frequency error in a short time. The device can monitor and measure the real-time rate of the unknown bit rate access low-speed serial data.

Description

Method for realizing automatic measurement of low-speed serial data bit rate

Technical Field

The invention relates to the field of communication, in particular to a method for realizing automatic measurement of bit rate of low-speed serial data; and more particularly to automatic bit rate measurement of low speed digital serial communication signals.

Background

When a communication device accesses a low-speed (below 10 Mbps) digital serial signal (such as an RS232 serial port, E1, etc.), if the bit rate of the access signal is unknown, the device is required to automatically measure the bit rate of the access signal. In the prior art, a receiving end and a transmitting end are generally required to negotiate to determine a certain communication protocol (for example, to determine serial communication), and then the bit rate of the receiving end and the transmitting end can be negotiated, so that the receiving end and the transmitting end are not strong in universality and universality due to the dependence on the protocol, and cannot access any low-speed digital serial signal of an unknown protocol.

Disclosure of Invention

The present invention is to solve the above problems in practical applications, and provide a method for implementing automatic measurement of low-speed serial data bit rate.

The technical scheme adopted by the invention is as follows: a method for realizing low-speed serial data bit rate automatic measurement is characterized in that the method comprises the steps of firstly filtering burrs or jitters of input data of accessed low-speed serial input data through a jitter passing module, then dynamically and automatically measuring and identifying the bit width of the input serial data through a bit width identification module, carrying out accumulated counting on data edges through a bit counting accumulation module based on the identified bit width, simultaneously carrying out accumulated counting on a main clock not less than 100MHz through a clock period counting accumulation module, resetting the bit counting accumulation module and the clock period counting accumulation module if the bit width identification module dynamically identifies a new bit width, and calculating and outputting a measurement result through a result calculation module based on the bit accumulated counting result and the clock accumulated counting result.

The method comprises the following specific steps:

firstly, carrying out debouncing processing on low-speed serial input data, and filtering out burr dithering in the low-speed serial input data through a debouncing module; the debouncing module firstly carries out multistage cascade register sampling on low-speed serial input data by using a main clock, judges the data edge of the change of the low-speed serial input data, judges and filters burrs if the change of two adjacent data edges is less than two clock periods, namely, keeps the data height unchanged at the position and outputs the data height to the bit width identification module; and if the change of the two adjacent data edges is not less than two clock cycles, the normal data is judged not to be processed and is transmitted to the bit width identification module.

And secondly, the bit width identification module dynamically and automatically identifies the bit width of the data, firstly, the minimum data edge change period is dynamically identified, if a new minimum data edge change period is found dynamically, a reset signal is output to the bit counting accumulation module and the clock period counting accumulation module, and the currently identified bit width is output to the bit counting accumulation module.

And thirdly, the bit counting accumulation module analyzes the input data edges, identifies a plurality of bit widths between two adjacent data edges, namely judges the bit widths into a plurality of bit numbers, accumulates and counts the bit numbers, if a reset signal is received, proves that the previous-stage bit width identification module dynamically identifies a new bit width, and therefore the accumulated counts need to be reset and cleared and then accumulation is restarted, and accumulated count results are output to the result calculation output module.

And fourthly, the clock period counting and accumulating module counts the clock period, namely, each rising edge of the clock adds one to the accumulated count, if a reset signal is received, the former-stage bit width identification module is proved to dynamically identify a new bit width, so that the accumulated count needs to be reset and cleared and then is accumulated again, and the accumulated count result is output to the result calculation and output module.

Fifthly, the result calculation output module calculates the received bit accumulation counting result, the clock accumulation counting result and the given invariable main clock frequency to obtain a final measuring result, and the calculation formula is as follows: input data bit rate measurement = master clock frequency × bit accumulated count result ÷ clock accumulated count result;

wherein: inputting a data bit rate measurement in bps; the master clock frequency is in Hz.

The invention has the beneficial effects that: by adopting the method, the automatic measurement of the bit rate of the low-speed serial data based on the FPGA is realized, and the precision superior to the common clock frequency error can be obtained in a short time. The device can monitor and measure the real-time rate of the unknown bit rate access low-speed serial data.

Drawings

FIG. 1 is a schematic diagram of the present invention;

FIG. 2 is a waveform diagram illustrating the results of measuring 1ms data according to the present invention;

FIG. 3 is a waveform diagram illustrating the results of 20ms data measured according to the present invention.

Detailed Description

The invention is further illustrated by the following figures and examples.

Based on a KU040 development board of Xilinx corporation, the scheme can realize automatic measurement of the bit rate of input low-speed serial data. Assuming that the master clock adopts 100MHz (the higher the master clock is, the better the measurement accuracy is), and assuming that the bit rate of the input serial data is not higher than 10Mbps, the result accuracy can be automatically measured within 1 second and is better than 1bps (the accuracy error of the master clock is not counted).

The specific method implemented as a block-by-block introduction follows, as shown in fig. 1.

(1) Debouncing module

In order to avoid an abnormality such as jitter of signal glitches due to a factor such as channel noise interference, it is necessary to first perform a debounce process on input data. The debouncing module firstly uses a main clock to carry out multi-stage cascade register sampling on input data, judges a data edge of input data change, judges and filters burrs if the change of two adjacent data edges is less than two clock periods, namely, the data height is kept unchanged at the position and the burrs are output to a next-stage module, namely a bit width identification module; if the change of the two adjacent data edges is not less than two clock cycles, the normal data is judged to be not processed and transmitted to a next-stage module, namely a bit width identification module. Meanwhile, the debounce module sends the data edge change after filtering the burr to the bit counting accumulation module.

(2) Bit width identification module

The bit width identification module dynamically and automatically identifies the bit width of the data, firstly, the minimum data edge change period is dynamically identified, if a new minimum data edge change period is found dynamically, a reset signal is output to the bit counting accumulation module and the clock period counting accumulation module, and the currently identified bit width is output to the bit counting accumulation module.

(3) Bit counting accumulation module

The bit counting and accumulating module analyzes the input data edges, identifies that a plurality of bit widths exist between two adjacent data edges, namely, judges the bit widths to be a plurality of bit numbers, accumulates and counts the bit numbers, and proves that the previous-stage bit width identification module dynamically identifies a new bit width if a reset signal is received, so that the accumulated count needs to be reset and cleared and then begins to be accumulated again. And the accumulated counting result is output to a lower result calculation output module.

(4) Clock period counting accumulation module

The clock period counting and accumulating module counts the period of the clock, namely, each rising edge of the clock adds one to the accumulated count, and if a reset signal is received, the former-stage bit width identification module is proved to dynamically identify a new bit width, so that the accumulated count needs to be reset and cleared and then is accumulated again. And the accumulated counting result is output to a lower result calculation output module.

(5) Result calculation output module

And the result calculation output module calculates the received bit accumulation counting result, the clock accumulation counting result and the given invariable main clock frequency to obtain a final measuring result. The calculation formula is as follows: input data bit rate measurement = master clock frequency × bit accumulated count result ÷ clock accumulated count result.

The measured data results are illustrated:

the master clock is 100MHz and the bit rate of the measured low speed digital signal is 666 kbps.

When measured for 1 millisecond time, the output measurement =100MHz × 643 ÷ 96547 =665.99687kbps with an error of approximately 4 bps. The measurement signals and the resulting output are shown in fig. 2.

When the time was measured at 0.2 seconds, the output measurement =100MHz × 13303 ÷ 1997446 =666.00048kbps was obtained with an error of approximately 0.5 bps. The measurement signals and the results output are shown in fig. 3.

Claims (1)

1. A method for realizing low-speed serial data bit rate automatic measurement is characterized in that the method comprises the steps that accessed low-speed serial input data are subjected to burr or jitter filtering of the input data through a jitter removing module, then dynamic automatic measurement and identification are carried out on the bit width of the input serial data through a bit width identification module, a bit counting accumulation module is used for carrying out accumulation counting on data edges based on the identified bit width, meanwhile, a clock period counting accumulation module is used for carrying out accumulation counting on a main clock which is not less than 100MHz, if the bit width identification module dynamically identifies a new bit width, the bit counting accumulation module and the clock period counting accumulation module are reset, and a measurement result can be calculated and output by adopting a result calculation module based on a bit accumulation counting result and a clock accumulation counting result;

the method comprises the following specific steps:

firstly, carrying out debouncing processing on low-speed serial input data, and filtering out burr dithering in the low-speed serial input data through a debouncing module; the debouncing module firstly carries out multistage cascade register sampling on low-speed serial input data by using a main clock, judges the data edge of the change of the low-speed serial input data, judges and filters burrs if the change of two adjacent data edges is less than two clock periods, namely, keeps the data height unchanged at the position and outputs the data height to the bit width identification module; if the change of the two adjacent data edges is not less than two clock cycles, the normal data is judged not to be processed and is transmitted to the bit width identification module;

the bit width identification module dynamically and automatically identifies the bit width of the data, firstly, the minimum data edge change period is dynamically identified, if a new minimum data edge change period is dynamically found, a reset signal is output to the bit counting accumulation module and the clock period counting accumulation module, and the currently identified bit width is output to the bit counting accumulation module;

thirdly, the bit counting accumulation module analyzes the input data edges, identifies a plurality of bit widths between two adjacent data edges, namely judges the bit widths into a plurality of bit numbers, accumulates and counts the bit numbers, if a reset signal is received, proves that the previous-stage bit width identification module dynamically identifies a new bit width, and therefore the accumulated count needs to be reset and cleared and then starts accumulation again, and the accumulated count result is output to the result calculation output module;

the clock period counting and accumulating module counts the clock period, namely, each rising edge of the clock adds one to the accumulated count, if a reset signal is received, the former-stage bit width identification module is proved to dynamically identify a new bit width, so that the accumulated count needs to be reset and cleared and then begins to be accumulated again, and the accumulated count result is output to the result calculation and output module;

fifthly, the result calculation output module calculates the received bit accumulation counting result, the clock accumulation counting result and the given invariable main clock frequency to obtain a final measuring result, and the calculation formula is as follows: input data bit rate measurement = master clock frequency × bit accumulated count result ÷ clock accumulated count result;

wherein: inputting a data bit rate measurement in bps;

the master clock frequency is in Hz.

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