CN112117999B

CN112117999B - Driving circuit and household appliance

Info

Publication number: CN112117999B
Application number: CN202010865074.7A
Authority: CN
Inventors: 刘利书
Original assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd
Current assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd
Priority date: 2020-08-25
Filing date: 2020-08-25
Publication date: 2024-07-26
Anticipated expiration: 2040-08-25
Also published as: CN112117999A; WO2022041625A1

Abstract

The application discloses a driving circuit and a household appliance, wherein the driving circuit comprises a signal processing circuit, a signal processing circuit and a control circuit, wherein the signal processing circuit is configured to process an input signal to obtain an intermediate signal; a first output circuit; a second output circuit; and the selection circuit is connected with the signal processor and is configured to control the signal processing circuit to select one of the first output circuit and the second output circuit according to the input signal so as to enable the first output circuit or the second output circuit to process the intermediate signal and obtain an output signal. Through the mode, the driving circuit can improve the matching degree of the high-low voltage control signals of the driving circuit, and meanwhile, the through short circuit phenomenon in the driving circuit is avoided.

Description

Driving circuit and household appliance

Technical Field

The application relates to the technical field of circuits, in particular to a driving circuit and a household appliance.

Background

With the rapid development of electronic technology, especially the application of high-frequency self-turn-off components such as IGBTs and MOSFETs is increasingly wide, the design of the driving circuit is particularly important. The driving circuit with good performance can enable the electronic device to work in an ideal switching state, shortens the switching time, reduces the switching loss, realizes the overcurrent protection of the electronic device, and has important significance on the efficiency, the reliability and the safety of the power converter.

However, in the existing driving circuit, the high-low voltage control signals are respectively processed and output through the respective processing circuits, so that the problem of mismatching of the high-low voltage control signals exists, the matching of upper bridge power device switches and lower bridge power device switches is affected, and the reliability of the system is reduced.

Disclosure of Invention

The application provides a driving circuit and a household appliance, which are used for solving the problem of mismatching of high-low voltage control signals in the prior art.

In order to solve the above-mentioned technical problem, the present application proposes a driving circuit, which includes a signal processing circuit configured to process an input signal to obtain an intermediate signal; a first output circuit; a second output circuit; and the selection circuit is connected with the signal processing circuit and is configured to control the signal processing circuit to select one of the first output circuit and the second output circuit according to the input signal so as to enable the first output circuit or the second output circuit to process the intermediate signal and obtain an output signal.

In order to solve the technical problems, the application provides a household appliance, which comprises the driving circuit.

The application discloses a driving circuit, which comprises a signal processing circuit, a driving circuit and a driving circuit, wherein the signal processing circuit is configured to process an input signal to obtain an intermediate signal; a first output circuit; a second output circuit; and the selection circuit is connected with the signal processing circuit and is configured to control the signal processing circuit to select one of the first output circuit and the second output circuit according to the input signal so as to enable the first output circuit or the second output circuit to process the intermediate signal and obtain an output signal. Through the mode, the driving circuit can process the input signal through the same signal processing circuit, and the high-low voltage control signal is obtained through processing through different output circuits, so that the problem of mismatching of the high-low voltage control signal caused by different signal processing circuits is solved; meanwhile, the safety of the driving circuit can be improved, and the problem that high and low voltage control signals penetrate is prevented.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a driving circuit according to an embodiment of the present application;

FIG. 2 is a schematic circuit diagram of an embodiment of the rectifying and filtering circuit in FIG. 1;

FIG. 3 is a schematic circuit diagram of an embodiment of the level shift circuit of FIG. 1;

FIG. 4 is a schematic circuit diagram of an embodiment of the edge triggered circuit of FIG. 1;

FIG. 5 is a schematic circuit diagram of an embodiment of the pulse generating circuit of FIG. 1;

FIG. 6 is a schematic circuit diagram of an embodiment of the high voltage output circuit of FIG. 1;

FIG. 7 is a schematic circuit diagram of an embodiment of the low voltage output circuit of FIG. 1;

Fig. 8 is a schematic structural view of an embodiment of the home appliance of the present application.

Detailed Description

In order to make those skilled in the art better understand the technical scheme of the present application, the driving circuit and the household electrical appliance provided by the present application are further described in detail below with reference to the accompanying drawings and the detailed description.

Referring to fig. 1, fig. 1 is a schematic diagram of a driving circuit according to an embodiment of the application. The driving circuit 100 may include a signal processing circuit 110, a first output circuit 120, a second output circuit 130, a selection circuit 140, a first input terminal 150, and a second input terminal 160.

Wherein the signal processing circuit 110 may be configured to process the input signal to obtain an intermediate signal. The selection circuit 140 may be connected to the signal processing circuit, and the selection circuit 140 may be configured to control the signal processing circuit 110 to selectively connect the first output circuit 120 or the second output circuit 130 according to the input signal, so that the first output circuit 120 or the second output circuit 130 processes the intermediate signal to obtain an output signal, so as to implement circuit driving.

Wherein the first output circuit 120 and the second output circuit 130 may perform different circuit processes on the intermediate signal; the input signal may include a first signal or a second signal, wherein a voltage value of the first signal may be higher than a voltage value of the second signal. The first signal may be a relatively high voltage signal in the driving circuit 100 and the second signal may be a relatively low voltage signal in the driving circuit 100.

The first input terminal 150 may be configured to input a first signal, and the second input terminal 160 may be configured to input a second signal. The selection circuit 140 may be connected to the first input terminal 150 and the second input terminal 160, respectively.

Specifically, the signal processing circuit 110 may include a rectifying and filtering circuit 111 and a level shifting circuit 112. The rectifying and filtering circuit 111 may be connected to the first input terminal 150 and the second input terminal 160, respectively, and may be configured to receive an input signal from the first input terminal or the second input terminal, perform rectifying and filtering processing on the input signal, and output a rectifying and filtering signal. The level shift circuit 112 may be connected to an output terminal of the rectifying and filtering circuit, and receives the rectifying and filtering signal, performs level shift processing on the rectifying and filtering signal, and outputs an intermediate signal.

Referring to fig. 2, fig. 2 is a schematic circuit diagram of an embodiment of the rectifying and filtering circuit in fig. 1. In the present embodiment, the rectifying-and-filtering circuit 111 may include thirteen transistors. Specifically, the control terminal of the first transistor Q1 may be used to receive an input signal, the first terminal of the first transistor Q1 may be used to connect to the power source VCC, and the first terminal of the first transistor Q1 may be connected to the third terminal of the first transistor Q1.

The control terminal of the second transistor Q2 may be connected to the control terminal of the first transistor Q1, the control terminal of the second transistor Q2 may be used to receive an input signal, the first terminal of the second transistor Q2 may be used to connect to the second terminal of the first transistor Q1, the second terminal of the second transistor Q2 may be grounded to VSS, and the second terminal of the second transistor Q2 may be connected to the third terminal of the second transistor Q2.

A first terminal of the first capacitor C1 may be connected between the first terminal of the second transistor Q2 and the second terminal of the first transistor Q1 through the first resistor R1, and a second terminal of the first capacitor C1 may be grounded VSS.

A first terminal of the third transistor Q3 may be connected to the power source VCC, and a first terminal of the third transistor Q3 may be connected to a third terminal of the third transistor Q3. The first terminal of the fourth transistor Q4 may be connected to the second terminal of the third transistor Q3, and the third terminal of the fourth transistor Q4 may be connected to the third terminal of the third transistor Q3.

The first terminal of the fifth transistor Q5 may be connected to the second terminal of the fourth transistor Q4. The first terminal of the sixth transistor Q6 may be connected to the second terminal of the fifth transistor Q5, the second terminal of the sixth transistor Q6 may be grounded to VSS, the second terminal of the sixth transistor Q6 may be connected to the third terminal of the sixth transistor Q6, and the third terminal of the sixth transistor Q6 may be connected to the third terminal of the fifth transistor Q5.

The control terminal of the third transistor Q3, the control terminal of the fourth transistor Q4, the control terminal of the fifth transistor Q5, and the control terminal of the sixth transistor Q6 may be connected, and a node thereof may be connected between the first resistor R1 and the first terminal of the first capacitor C1.

A first terminal of the seventh transistor Q7 may be connected between the second terminal of the third transistor Q3 and the first terminal of the fourth transistor Q4, and a third terminal of the seventh transistor Q7 may be connected to the power VCC. A second terminal of the eighth transistor Q8 may be connected between the second terminal of the fifth transistor Q5 and the first terminal of the sixth transistor Q6, and a third terminal of the eighth transistor Q8 may be grounded VSS.

Wherein, the control terminal of the seventh transistor Q7 and the control terminal of the eighth transistor Q8 may be connected, and a node thereof may be connected between the first terminal of the fifth transistor Q5 and the second terminal of the fourth transistor Q4.

A control terminal of the ninth transistor Q9 may be connected to the second terminal of the seventh transistor Q7 and the ground VSS, a first terminal of the ninth transistor Q9 may be connected to the power source VCC, a first terminal of the ninth transistor Q9 may be connected to the third terminal of the ninth transistor Q9, and a second terminal of the ninth transistor Q9 may be connected to the first terminal of the eighth transistor Q8.

A first terminal of the tenth transistor Q10 may be connected to the power source VCC, and a first terminal of the tenth transistor Q10 may be connected to a third terminal of the tenth transistor Q10. A first terminal of the eleventh transistor Q11 may be connected to the second terminal of the tenth transistor Q10, a second terminal of the eleventh transistor Q11 may be grounded VSS, and a first terminal of the eleventh transistor Q11 may be connected to the third terminal of the eleventh transistor Q11.

Wherein, the control terminal of the tenth transistor Q10 and the control terminal of the eleventh transistor Q11 may be connected, and a node thereof may be connected between the control terminal of the seventh transistor Q7 and the control terminal of the eighth transistor Q8.

A first terminal of the twelfth transistor Q12 may be connected to the power VCC, and a first terminal of the twelfth transistor Q12 may be connected to a third terminal of the twelfth transistor Q12. A first terminal of the thirteenth transistor may be connected to the second terminal of the twelfth transistor Q12, a node thereof may be used as an output terminal of the rectifying and filtering circuit 111 to output a rectifying and filtering signal, a second terminal of the thirteenth transistor Q13 may be grounded VSS, and a second terminal of the thirteenth transistor Q13 is connected to a third terminal of the thirteenth transistor Q13.

Wherein a control terminal of the twelfth transistor Q12 may be connected to a control terminal of the thirteenth transistor Q13, and a node thereof may be connected between a second terminal of the tenth transistor Q10 and a first terminal of the eleventh transistor Q11.

In the present embodiment, the first, third, fourth, and seventh transistors Q1, Q3, Q4, and Q7, the ninth, tenth, and twelfth transistors Q9, Q10, and Q12 may be PMOS transistors.

The second, fifth, sixth, eighth, eleventh, and thirteenth transistors Q2, Q5, Q6, Q8, Q11, and Q13 may be NMOS transistors. In addition, in the first transistor Q1 to the thirteenth transistor Q13, the control end may be a gate of the MOS transistor, the first end may be a source drain of the MOS transistor, the second end may be a source drain of the MOS transistor, and the third end may be a substrate electrode of the MOS transistor.

The rectification filter circuit 111 can realize a hysteresis control function, and avoid the occurrence of false operations. Meanwhile, the noise signals in the waveform shaping and filtering circuit are realized, and the interference is reduced.

Optionally, the rectifying and filtering circuit 111 may further include a protection circuit 1111, where the protection circuit 1111 may be formed by five logic gates, respectively: a first NOT gate G5, a first AND gate G6, a second NOT gate G7, a second AND gate G8 and a first OR gate G9.

The input of the first not gate G5 may receive the first signal HIN; a first input terminal of the first and gate G6 may be connected to an output terminal of the first not gate G5, and a second input terminal of the first and gate G6 may receive the second signal LIN; the input of the second not gate G7 may receive the second signal LIN; the first input end of the second and gate G8 may be connected to the output end of the second not gate G7, and the second input end of the second and gate G8 may receive the first signal HIN; the first input terminal of the first or gate G9 may be connected to the output terminal of the first and gate G6, the second input terminal of the first or gate G9 may be connected to the output terminal of the second and gate G8, and the output terminal of the first or gate G9 is connected between the control terminal of the first transistor and the control terminal of the second transistor.

When the protection circuit 1111 operates, only one signal can pass through at the same time, for example, when the protection circuit 1111 receives the first signal, it is equivalent to the first not gate G5 receiving the high voltage and outputting the low voltage; a first input end of the first AND gate G6 receives the low voltage, a second input end of the first AND gate G6 receives the low voltage, and the first AND gate G6 outputs the low voltage; the second NOT gate G7 receives the low voltage, outputs the high voltage, the first end of the second AND gate G8 receives the high voltage, the second end of the second AND gate G8 receives the high voltage, and the second end of the second AND gate G8 outputs the high voltage; the first input terminal of the first or gate G9 receives the low voltage, the second output terminal of the first or gate G9 receives the high voltage, and the first or gate G9 outputs the high voltage to the control terminals of the first transistor Q1 and the second transistor Q2, so that the first signal can be subjected to rectifying and filtering processing.

The protection circuit 1111 operates in a similar manner to that of the first signal when it receives the second signal, and will not be described again.

When a special situation occurs, for example, when the protection circuit 1111 receives the first signal and the second signal at the same time, the first not gate G5 receives the high voltage and outputs the low voltage; a first input end of the first AND gate G6 receives the low voltage, a second input end of the first AND gate G6 receives the low voltage, and the first AND gate G6 outputs the low voltage; the second NOT gate G7 receives the high voltage and outputs the low voltage; the first input end of the second AND gate G8 receives the low voltage, the second input end of the second AND gate G8 receives the low voltage, and the second AND gate G8 outputs the low voltage; the first input end of the first or gate G9 receives the low voltage, the second output end of the first or gate G9 receives the low voltage, the first or gate G9 outputs the low voltage to the control ends of the first transistor Q1 and the second transistor Q2, and at this time, the first transistor Q1 and the second transistor Q2 cannot work normally, thereby realizing a protection function and avoiding circuit abnormality caused by the simultaneous existence of the first signal and the second signal in the rectifying and filtering circuit 111.

Referring to fig. 3, fig. 3 is a schematic circuit diagram of an embodiment of the level shift circuit in fig. 1. In the present embodiment, the level shift circuit 112 may include transistors Q14 to Q25.

Specifically, the control terminal of the fourteenth transistor Q14, the control terminal of the fifteenth transistor Q15, the control terminal of the sixteenth transistor Q16, and the control terminal of the seventeenth transistor Q17 are connected and receive the rectifying-and-filtering signal.

A first terminal of the fourteenth transistor Q14 may be connected to the reference power source VREG, and a first terminal of the fourteenth transistor Q14 may be connected to a third terminal of the fourteenth transistor Q14.

A first terminal of the fifteenth transistor Q15 may be connected to a first terminal of the fourteenth transistor Q14, and a third terminal of the fifteenth transistor Q15 may be connected to a third terminal of the fourteenth transistor Q14.

A first terminal of the sixteenth transistor Q16 may be connected to a second terminal of the fifteenth transistor Q15. A first terminal of the seventeenth transistor Q17 may be connected to the second terminal of the sixteenth transistor Q16, and a third terminal of the seventeenth transistor Q17 may be connected to the third terminal of the sixteenth transistor Q16.

A first terminal of the eighteenth transistor Q18 may be connected between the second terminal of the fourteenth transistor Q14 and the first terminal of the fifteenth transistor Q15, the second terminal of the eighteenth transistor Q18 may be grounded VSS, and a third terminal of the eighteenth transistor Q18 may be connected to the reference power supply VREG.

A control terminal of the nineteenth transistor Q19 may be connected to a control terminal of the eighteenth transistor Q18, a first terminal of the nineteenth transistor Q19 may be connected to the reference power supply VREG, and a second terminal of the nineteenth transistor Q19 may be connected between a second terminal of the sixteenth transistor Q16 and a first terminal of the seventeenth transistor Q17.

A first terminal of the twentieth transistor Q20 may be connected to the reference power supply VREG, and a third terminal of the twentieth transistor Q20 may be connected to the first terminal of the twentieth transistor Q20. A first terminal of the twenty-first transistor Q21 may be connected to a second terminal of the twentieth transistor Q20, a second terminal of the twenty-first transistor Q21 may be connected to a third terminal of the twenty-first transistor Q21, and a control terminal of the twenty-first transistor Q21 may be connected to a control terminal of the twentieth transistor Q20.

Wherein the second terminal of the seventeenth transistor Q17, the third terminal of the nineteenth transistor Q19, and the second terminal of the twenty-first transistor Q21 may be connected.

A first terminal of the twenty-second transistor Q22 may be connected to the power supply VCC, and a third terminal of the twenty-second transistor Q22 may be connected to the first terminal of the twenty-second transistor Q22. A first terminal of the twenty-third transistor Q23 may be connected to the second terminal of the twenty-third transistor Q22, a second terminal of the twenty-third transistor Q23 may be grounded to VSS, and a third terminal of the twenty-third transistor Q23 may be connected to the second terminal of the twenty-third transistor Q23.

Wherein a connection node of the second terminal of the fifteenth transistor Q15 and the first terminal of the sixteenth transistor Q16, a connection node of the control terminal of the eighteenth transistor Q18 and the control terminal of the nineteenth transistor Q19, a connection node of the control terminal of the twentieth transistor Q20 and the control terminal of the twenty first transistor Q21, and a control terminal of the twenty third transistor Q23 may be connected.

A first terminal of the twenty-fourth transistor Q24 may be connected to the power supply VCC, a third terminal of the twenty-fourth transistor Q24 may be connected to the first terminal of the twenty-fourth transistor Q24, and a control terminal of the twenty-fourth transistor Q24 may be connected between the second terminal of the twenty-transistor Q22 and the first terminal of the twenty-third transistor Q23.

A first terminal of the twenty-fifth transistor Q25 may be connected to a second terminal of the twenty-fourth transistor Q24, and a node thereof serves as an output terminal of the level shift circuit 112 to output an intermediate signal; a second terminal of the twenty-fifth transistor Q25 may be grounded VSS, and a second terminal of the twenty-fifth transistor Q25 may be connected to a third terminal of the twenty-fifth transistor Q25. A control terminal of the twenty-fifth transistor Q25 may be connected between the second terminal of the twentieth transistor Q20 and the first terminal of the twenty-first transistor Q21.

In the present embodiment, the fourteenth transistor Q14, the fifteenth transistor Q15, the eighteenth transistor Q18, the twentieth transistor Q20, the twenty-second transistor Q22, and the twenty-fourth transistor Q24 may be PMOS transistors.

The sixteenth transistor Q16, seventeenth transistor Q17, nineteenth transistor Q19, twenty first transistor Q21, twenty third transistor Q23, and twenty fifth transistor Q25 may be NMOS transistors. In addition, in the fourteenth transistor Q14 to the twenty-fifth transistor Q25, the control end may be a gate of the MOS transistor, the first end may be a source/drain of the MOS transistor, the second end may be a source/drain of the MOS transistor, and the third end may be a substrate electrode of the MOS transistor.

The level shift circuit 112 may adjust the amplitude range of the rectified and filtered signal to a voltage value corresponding to VSS to VCC according to the design requirement of the user.

With continued reference to fig. 1, the selection circuit 140 may be configured to control the signal processing circuit 110 to connect the first output circuit 120 in response to receiving the first signal; or in response to the second signal, the control signal processing circuit 110 is connected to the second output circuit 130.

The selection circuit 140 may include an edge trigger circuit 141 and a switching circuit 142. The edge trigger circuit 141 may be connected to the first input terminal and the second input terminal, and may be used to generate a trigger signal according to the first signal or the second signal.

The switching circuit 142 may include a first connection terminal, a second connection terminal, and a control terminal, and the first connection section may be connected to the signal processing circuit 110 to receive the intermediate signal; the control terminal may be used to connect to the edge trigger circuit 141 to input a trigger signal; the second connection terminal may be a mobile connection terminal, and may be selectively connected to the first output circuit 120 or the second output circuit 130 according to the trigger signal.

Referring to fig. 4, fig. 4 is a schematic circuit diagram of an embodiment of the edge triggered circuit in fig. 1. In this embodiment, the edge trigger circuit 141 may include a JK flip-flop. The JK flip-flop may include a J signal input, a K signal input, and a signal output.

The J signal input may be coupled to the first input 150 to receive a first signal, the K signal input may be coupled to the second input 160 to receive a second signal, and the signal output may include Q andThe control terminal of the switch circuit 142 may be connected, and the second connection terminal of the switch circuit 142 is used for selectively connecting the first output circuit or the second output circuit according to the trigger signal output by the JK trigger.

Specifically, as shown in fig. 2, the JK flip-flop may include four nand gates, namely, a first nand gate G1, a second nand gate G2, a third nand gate G3, and a fourth nand gate G4.

The first input end of the first nand gate G1 is used as a J signal input end, the first input end of the second nand gate G2 is not used as a K signal input end, and the second input end of the first nand gate G1 is connected with the second input end of the second nand gate G2 and receives the clock signal CP. The output end of the first NAND gate G1 is connected with the first input end of the third NAND gate G3, and the output end of the second NAND gate G2 is connected with the first input end of the fourth NAND gate G4.

The third input end of the second NAND gate G2 and the second input end of the fourth NAND gate G4 are connected with the output end of the third NAND gate G3, and the node of the third NAND gate G3 outputs Q; the third input end of the first NAND gate G1 and the second input end of the third NAND gate G3 are connected with the output end of the fourth NAND gate G4, and the nodes thereof output

The JK flip-flop has the functions of set 0, set 1, hold and flip, as shown in the following figures:

In this embodiment, when the JK flip-flop receives the first signal, Q outputs a high level; when the JK flip-flop receives the second signal, Q outputs a low level. When the switch circuit 142 may use the high level or the low level of the Q output of the JK flip-flop as the trigger signal, the first output circuit 120 or the second output circuit 130 is selectively connected to: when Q outputs a high level, the first output circuit 120 may be selectively connected; the second output circuit 130 may be selectively connected when the Q output level.

With continued reference to fig. 1, the first output circuit 120 may include a pulse generating circuit 121 and a high voltage output circuit 122. The pulse generating circuit 121 may be configured to receive the intermediate signal and generate a pulse signal according to the intermediate signal; the high voltage output circuit 122 may be configured to receive the pulse signal and generate a high voltage output signal based on the pulse signal.

Referring to fig. 5, fig. 5 is a schematic circuit diagram of an embodiment of the pulse generating circuit in fig. 1. In the present embodiment, the pulse generating circuit 121 may include the following:

A first terminal of the twenty-sixth transistor Q26 may be connected to the power supply VCC, and a third terminal of the twenty-sixth transistor Q26 may be connected to the first terminal of the twenty-sixth transistor Q26. A first terminal of the twenty-seventh transistor Q27 is connected to the second terminal of the twenty-sixth transistor Q26, a second terminal of the twenty-seventh transistor may be grounded to VSS, a control terminal of the twenty-sixth transistor Q26 may be connected to a control terminal of the twenty-seventh transistor Q27, and a node thereof is used as an input terminal of the pulse generating circuit 1221 to receive the intermediate signal.

A first terminal of the twenty-eighth transistor Q28 may be connected to the power supply VCC, and a third terminal of the twenty-eighth transistor Q28 may be connected to the first terminal of the twenty-eighth transistor Q28. The first terminal of the twenty-ninth transistor Q29 may be connected to the second terminal of the twenty-eighth transistor Q28 through the second resistor R2, the second terminal of the twenty-ninth transistor Q29 may be grounded VSS, and the third terminal of the twenty-ninth transistor Q29 may be connected to the second terminal of the twenty-ninth transistor Q29.

Wherein the control terminal of the twenty-eighth transistor Q28 may be connected to the control terminal of the twenty-ninth transistor Q29, and a node thereof may be connected between the control terminal of the twenty-sixth transistor Q26 and the control terminal of the twenty-seventh transistor Q27.

A first terminal of the thirty-third transistor Q30 may be connected to the power supply VCC, and a third terminal of the thirty-third transistor Q30 may be connected to the first terminal of the thirty-third transistor Q30. A first terminal of the thirty-first transistor Q31 may be connected to a second terminal of the thirty-first transistor Q30, and a third terminal of the thirty-first transistor Q31 may be connected to a third terminal of the thirty-first transistor Q30.

A first terminal of the thirty-first transistor Q32 may be connected to a first terminal of the thirty-first transistor Q31. A first terminal of the thirty-third transistor Q33 may be connected to the second terminal of the thirty-third transistor Q32, a second terminal of the thirty-third transistor Q33 may be grounded to VSS, a third terminal of the thirty-third transistor Q33 may be connected to the second terminal of the thirty-third transistor Q33, and a third terminal of the thirty-third transistor Q33 may be connected to the third terminal of the thirty-third transistor Q32.

The control terminal of the thirty-first transistor Q30, the control terminal of the thirty-first transistor Q31, the control terminal of the thirty-second transistor Q32, and the control terminal of the thirteenth transistor Q33 may be connected, and the nodes thereof are connected to the second resistor R2 and the second terminal of the twenty-eighth transistor Q28. A first terminal of the second capacitor C2 may be connected between the second terminal of the twenty-eighth transistor Q28 and the control terminal of the thirty-first transistor Q31.

A first terminal of the thirty-fourth transistor Q34 may be connected between the second terminal of the thirty-first transistor Q31 and the second terminal of the thirty-third transistor Q30. A second terminal of the thirty-fifth transistor Q35 may be connected between the second terminal of the thirty-third transistor Q32 and the first terminal of the thirty-third transistor Q33, and a third terminal of the thirty-fifth transistor Q35 may be grounded to VSS.

A control terminal of the thirty-fourth transistor Q34 may be connected to a control terminal of the thirty-fifth transistor Q35, and a node thereof may be connected to a second terminal of the thirty-third transistor Q30 and a first terminal of the thirty-third transistor Q32.

A first terminal of the thirty-sixth transistor Q36 may be connected to the power supply VCC, a second terminal of the thirty-sixth transistor Q36 may be connected to a first terminal of the thirty-fifth transistor Q35, a third terminal of the thirty-sixth transistor Q36 may be connected to the first terminal of the thirty-sixth transistor Q36, and a control terminal of the thirty-sixth transistor Q36 may be connected to a second terminal of the thirty-fourth transistor Q34.

A first terminal of the thirty-seventh transistor Q37 may be connected to the power supply VCC and a third terminal of the thirty-seventh transistor Q37 may be connected to the first terminal of the thirty-seventh transistor Q37. A first terminal of the thirty-eighth transistor Q38 may be connected to a second terminal of the thirty-seventh transistor Q37, a second terminal of the thirty-eighth transistor Q38 may be grounded, and a third terminal of the thirty-eighth transistor Q38 may be connected to a second terminal of the thirty-eighth transistor Q38.

Wherein the control terminal of the thirty-seventh transistor Q37 and the control terminal of the thirty-eighth transistor Q38 may be connected, and a node thereof may be connected between the control terminal of the thirty-fourth transistor Q34 and the control terminal of the thirty-fifth transistor Q35.

A first terminal of the thirty-ninth transistor Q39 may be connected to the power supply VCC and a third terminal of the thirty-ninth transistor Q39 may be connected to the first terminal of the thirty-ninth transistor Q39. A first terminal of forty-first transistor Q40 may be connected to a second terminal of thirty-ninth transistor Q39. A second terminal of the forty transistor Q40 may be grounded VSS, and a third terminal of the forty transistor Q40 may be connected to the second terminal of the forty transistor Q40.

A control terminal of the thirty-ninth transistor Q39 may be connected to the control terminal of the thirty-ninth transistor Q39, and a node thereof may be connected between the second terminal of the thirty-seventh transistor Q37 and the first terminal of the thirty-eighth transistor Q38.

A second terminal of the forty-first transistor Q41 may be grounded VSS, and a third terminal of the forty-first transistor Q41 may be connected to the second terminal of the forty-first transistor Q41.

A first terminal of the forty-second transistor Q42 may be connected to the power supply VCC, and a third terminal of the forty-second transistor Q42 may be connected to the first terminal of the forty-second transistor Q42. A first terminal of the forty-third transistor Q43 may be connected to a second terminal of the forty-transistor Q42.

A first terminal of the forty-fourth transistor Q44 may be coupled to the second terminal of the forty-third transistor Q43, a second terminal of the forty-fourth transistor Q44 may be coupled to ground VSS, a control terminal of the forty-third transistor Q43 may be coupled to a control terminal of the forty-fourth transistor Q44, and a node thereof may be coupled between the second terminal of the thirty-ninth transistor Q39 and the first terminal of the forty-transistor Q40.

Wherein the first terminal of the forty-first transistor Q41 may be connected between the second terminal of the forty-third transistor Q43 and the first terminal of the forty-fourth transistor Q44. A control terminal of the forty-first transistor Q41 may be connected to a control terminal of the forty-second transistor Q42, and a node thereof may be connected to a second terminal of the twenty-sixth transistor Q26 and a first terminal of the twenty-seventh transistor Q27.

A first terminal of the forty-fifth transistor Q45 may be connected to the power supply VCC, and a third terminal of the forty-fifth transistor Q45 may be connected to the first terminal of the forty-fifth transistor Q45. A first terminal of the forty-sixth transistor Q46 may be connected to a second terminal of the forty-fifth transistor Q45. A second terminal of the forty-sixth transistor Q46 may be grounded VSS and a third terminal of the forty-sixth transistor Q46 may be connected to the second terminal of the forty-sixth transistor Q46.

The control terminal of the forty-fifth transistor Q45 may be connected to the control terminal of the forty-fifth transistor Q45, and a node thereof is connected between the second terminal of the forty-third transistor Q43 and the first terminal of the forty-fourth transistor Q44.

A first terminal of the forty-seventh transistor Q47 may be connected to the power supply VCC, and a third terminal of the forty-seventh transistor Q47 may be connected to the first terminal of the forty-seventh transistor Q47. A first terminal of the forty-eighth transistor Q48 may be connected to a second terminal of the forty-seventh transistor Q47, and a node thereof may be a first output terminal of the pulse generating circuit 121 to output a first pulse signal. A second terminal of the forty-eight transistor Q48 may be grounded VSS and a third terminal of the forty-eight transistor Q48 may be connected to the second terminal of the forty-eight transistor Q48.

Wherein the control terminal of the forty-seventh transistor Q47 may be connected to the control terminal of the forty-seventh transistor Q47, and the node thereof is connected between the second terminal of the forty-fifth transistor Q45 and the second terminal of the forty-sixth transistor Q46.

A first terminal of the forty-ninth transistor Q49 may be connected to the power supply VCC, and a third terminal of the forty-ninth transistor Q49 may be connected to the first terminal of the forty-ninth transistor Q49. A first terminal of the fifty-seventh transistor Q50 is connected to the second terminal of the forty-ninth transistor Q49, a second terminal of the twenty-seventh transistor Q27 may be grounded VSS, a control terminal of the forty-ninth transistor Q49 may be connected to the control terminal of the fifty-seventh transistor Q50, and a node thereof may be connected between the second terminal of the twenty-sixth transistor Q26 and the first terminal of the twenty-seventh transistor Q27.

A first terminal of the fifty-first transistor Q51 may be connected to the power supply VCC, and a third terminal of the fifty-first transistor Q51 may be connected to the first terminal of the fifty-first transistor Q51. The first terminal of the fifty-first transistor Q52 may be connected to the second terminal of the fifty-first transistor Q51 through the third resistor R3, the second terminal of the fifty-first transistor Q52 may be grounded VSS, and the third terminal of the fifty-first transistor Q52 may be connected to the second terminal of the fifty-first transistor Q52.

Wherein the control terminal of the fifty-first transistor Q51 may be connected to the control terminal of the fifty-first transistor Q52, and a node thereof may be connected between the control terminal of the forty-ninth transistor Q49 and the control terminal of the fifty-first transistor Q50.

A first terminal of the fifty-third transistor Q53 may be coupled to the power source VCC, and a third terminal of the fifty-third transistor Q53 may be coupled to the first terminal of the fifty-third transistor Q53. A first terminal of the fifty-fourth transistor Q54 may be coupled to a second terminal of the fifty-third transistor Q53, and a third terminal of the fifty-fourth transistor Q54 may be coupled to a third terminal of the fifty-third transistor Q53.

A first terminal of the fifty-fifth transistor Q55 may be connected to a first terminal of the fifty-fourth transistor Q54. A first terminal of the fifty-sixth transistor Q56 may be connected to the second terminal of the fifty-fifth transistor Q55, a second terminal of the fifty-sixth transistor Q56 may be connected to ground VSS, a third terminal of the fifty-sixth transistor Q56 may be connected to the second terminal of the fifty-sixth transistor Q56, and a third terminal of the fifty-sixth transistor Q56 may be connected to the third terminal of the fifty-fifth transistor Q55.

The control terminal of the thirteenth transistor Q53, the control terminal of the fifty-fourth transistor Q54, the control terminal of the fifty-fifth transistor Q55, and the control terminal of the fifty-sixth transistor Q56 may be connected, and the nodes thereof are connected to the third resistor R3 and the second terminal of the fifty-first transistor Q51. A first terminal of the third capacitor C3 may be connected between the second terminal of the fifty-first transistor Q51 and the control terminal of the fifty-fourth transistor Q54.

A first terminal of the thirty-fourth transistor Q34 may be connected between the second terminal of the fifty-third transistor Q53 and the first terminal of the fifty-fourth transistor Q54. A second terminal of the fifty-eighth transistor Q58 may be connected between the second terminal of the fifty-fifth transistor Q55 and the first terminal of the fifty-sixth transistor Q56, and a third terminal of the fifty-eighth transistor Q58 may be grounded VSS.

Wherein a control terminal of the fifty-seventh transistor Q57 may be coupled to a control terminal of the fifty-eighth transistor Q58, and a node thereof may be coupled to a second terminal of the fifty-third transistor Q53 and a first terminal of the fifty-fifth transistor Q55.

A first terminal of the fifty-ninth transistor Q59 may be connected to the power supply VCC, a second terminal of the fifty-ninth transistor Q59 may be connected to a first terminal of the fifty-eighth transistor Q58, a third terminal of the fifty-ninth transistor Q59 may be connected to the first terminal of the fifty-ninth transistor Q59, and a control terminal of the fifty-ninth transistor Q59 may be connected to a second terminal of the fifty-seventh transistor Q57.

A first terminal of the sixty transistor Q60 may be connected to the power supply VCC, and a third terminal of the sixty transistor Q60 may be connected to the first terminal of the sixty transistor Q60. A first terminal of the sixty-first transistor Q61 may be connected to the second terminal of the sixty-first transistor Q60, a second terminal of the sixty-first transistor Q61 may be grounded, and a third terminal of the sixty-first transistor Q61 may be connected to the second transistor of the sixty-first transistor Q61.

Wherein the control terminal of the sixty-first transistor Q60 and the control terminal of the sixty-first transistor Q61 may be connected, and a node thereof may be connected between the control terminal of the fifty-seventh transistor Q57 and the control terminal of the fifty-eighth transistor Q58.

A first terminal of the sixty transistor Q62 may be connected to the power VCC, and a third terminal of the sixty transistor Q62 may be connected to the first terminal of the sixty transistor Q62. A first terminal of the sixty-third transistor Q63 may be coupled to a second terminal of the sixty-transistor Q62. A second terminal of the sixty-third transistor Q63 may be grounded VSS, and a third terminal of the sixty-third transistor Q63 may be connected to the second terminal of the sixty-third transistor Q63.

The control terminal of the sixty-second transistor Q62 may be connected to the control terminal of the sixty-second transistor Q62, and the node thereof is connected between the second terminal of the sixty-second transistor Q60 and the first terminal of the sixty-first transistor Q61.

A second terminal of the sixty-fourth transistor Q64 may be grounded VSS, and a third terminal of the sixty-fourth transistor Q64 may be connected to the second terminal of the sixty-fourth transistor Q64.

A first terminal of the sixty-fifth transistor Q65 may be connected to the power supply VCC, and a third terminal of the sixty-fifth transistor Q65 may be connected to the first terminal of the sixty-fifth transistor Q65. A first terminal of the sixty-sixth transistor Q66 may be connected to a second terminal of the sixty-fifth transistor Q65.

A first terminal of the sixty-seventh transistor Q67 may be connected to the second terminal of the sixty-sixth transistor Q66, a second terminal of the sixty-seventh transistor Q67 may be grounded VSS, a control terminal of the sixty-sixth transistor Q66 may be connected to the control terminal of the sixty-seventh transistor Q67, and a node thereof may be connected between the second terminal of the sixty-transistor Q62 and the first terminal of the forty-transistor Q40.

Wherein a first terminal of the sixty-fourth transistor Q64 may be connected between a second terminal of the sixty-sixth transistor Q66 and a first terminal of the sixty-seventh transistor Q67. A control terminal of the sixty-fourth transistor Q64 may be connected to a control terminal of a sixty-fifth transistor Q65, and a node thereof may be connected to a second terminal of the forty-ninth transistor Q49 and a first terminal of the fifty-first transistor Q50.

A first terminal of the sixty-eighth transistor Q68 may be connected to the power supply VCC and a third terminal of the sixty-eighth transistor Q68 may be connected to the first terminal of the sixty-eighth transistor Q68. A first terminal of the sixty-ninth transistor Q69 may be connected to a second terminal of the sixty-eighth transistor Q68. A second terminal of the sixty-ninth transistor Q69 may be grounded VSS, and a third terminal of the sixty-ninth transistor Q69 may be connected to the second terminal of the sixty-ninth transistor Q69.

The control terminal of the sixty-eighth transistor Q68 may be connected to the control terminals of the sixty-ninth transistors Q69, 9, and the node thereof is connected between the second terminal of the sixty-sixth transistor Q66 and the first terminal of the sixty-seventh transistor Q67.

A first terminal of the seventy transistor Q70 may be connected to the power source VCC, and a third terminal of the seventy transistor Q70 may be connected to the first terminal of the seventy transistor Q70. A first terminal of the seventy-first transistor Q71 may be connected to a second terminal of the seventy-first transistor Q70, and a node thereof may serve as a second output terminal of the pulse generating circuit 121 to output a second pulse signal. The second terminal of the seventy-first transistor Q71 may be grounded VSS, and the third terminal of the seventy-first transistor Q71 may be connected to the second terminal of the seventy-first transistor Q71.

The control terminal of the seventy-eighth transistor Q70 may be connected to the control terminal of the seventy-first transistor Q71, and the node thereof may be connected between the second terminal of the sixty-eighth transistor Q68 and the second terminal of the sixty-ninth transistor Q69.

In the present embodiment, the twenty-sixth transistor Q26, the twenty-eighth transistor Q28, the thirty-seventh transistor Q30, the thirty-first transistor Q31, the thirty-fourth transistor Q34, the thirty-sixth transistor Q36, the thirty-seventh transistor Q37, the thirty-ninth transistor Q39, the forty-fourth transistor Q42, the forty-third transistor Q43, the forty-fifth transistor Q45, the forty-seventh transistor Q47, the forty-ninth transistor Q49, the fifty-first transistor Q51, the thirteenth transistor Q53, the fifty-fourth transistor Q54, the fifty-seventh transistor Q57, the fifty-ninth transistor Q59, the sixty-transistor Q60, the sixty-fourth transistor Q62, the sixty-fifth transistor Q65, the sixty-sixth transistor Q66, the sixty-eighth transistor Q68, and the seventy-seventh transistor Q70 may be PMOS transistors.

Twenty-seventh transistor Q27, twenty-ninth transistor Q29, thirty-eighth transistor Q32, thirty-third transistor Q33, thirty-fifth transistor Q35, thirty-eighth transistor Q38, fortieth transistor Q40, fortieth-first transistor Q41, fortieth-fourth transistor Q44, fortieth-sixth transistor Q46, fortieth-eighth transistor Q48, fifty-sixth transistor Q50, fifty-fifth transistor Q52, fifty-fifth transistor Q55, fifty-sixth transistor Q56, fifty-eighth transistor Q58, sixtieth-first transistor Q61, sixty-third transistor Q63, sixtieth-fourth transistor Q64, sixtieth-seventh transistor Q67, sixtieth-ninth transistor Q69, seventieth-first transistor Q71 may be NMOS transistors.

In addition, in the twenty-sixth transistor Q26 to the seventy-first transistor Q71, the control end may be a gate of the MOS transistor, the first end may be a source/drain of the MOS transistor, the second end may be a source/drain of the MOS transistor, and the third end may be a substrate electrode of the MOS transistor.

The pulse generation circuit 121 may be used in conjunction with the high voltage output circuit 122. The pulse generating circuit 121 generates two pulses with a pulse width of 300ns to 600ns, respectively and rapidly switches two LDMOS (not shown), transmits a control signal to the high tub area, and then restores the pulse signal to one signal through an RS flip-flop circuit (not shown), thereby controlling the high voltage output of the high voltage output circuit 122.

Referring to fig. 6, fig. 6 is a schematic circuit diagram of an embodiment of the high voltage output circuit in fig. 1. In the present embodiment, the high voltage output circuit 122 may include the following:

a first terminal of the seventy transistor Q72 may be connected to a high voltage power source, and a third terminal of the seventy transistor Q72 may be connected to the first terminal of the seventy transistor Q72. A first terminal of the seventy-third transistor Q73 may be connected to the second terminal of the seventy-third transistor Q72, a second terminal of the seventy-third transistor Q73 may be connected to the ground VS, and a third terminal of the seventy-third transistor Q73 may be connected to the second terminal of the seventy-third transistor Q73. The control terminal of the seventeenth transistor Q72 may be connected to the control terminal of the seventeenth transistor Q73.

A first terminal of the seventy-fourth transistor Q74 may be connected to the high voltage power supply, and a third terminal of the seventy-fourth transistor Q74 may be connected to the first terminal of the seventy-fourth transistor Q74. A first terminal of the seventy-fifth transistor Q75 may be connected to the second terminal of the seventy-fourth transistor Q74, a second terminal of the seventy-fifth transistor Q75 may be grounded VS, and a third terminal of the seventy-fifth transistor Q75 may be connected to the second terminal of the seventy-fifth transistor Q75. Wherein a control terminal of the seventy-fourth transistor Q74 may be connected to a control terminal of the seventy-fifth transistor Q75, and a node thereof may be connected between a first terminal of the seventy-third transistor Q73 and a second terminal of the seventy-third transistor Q72.

A first terminal of the seventy-sixth transistor Q76 may be connected to the high voltage power supply, and a third terminal of the seventy-sixth transistor Q76 may be connected to the first terminal of the seventy-sixth transistor Q76. A first terminal of the seventy-seventh transistor Q77 may be connected to the second terminal of the seventy-sixth transistor Q76, a second terminal of the seventy-seventh transistor Q77 may be grounded VS, and a third terminal of the seventy-seventh transistor Q77 may be connected to the second terminal of the seventy-seventh transistor Q77. Wherein a control terminal of the seventy-sixth transistor Q76 may be connected to a control terminal of the seventy-seventh transistor Q77, and a node thereof may be connected between a first terminal of the seventy-fifth transistor Q75 and a second terminal of the seventy-fourth transistor Q74.

A third terminal of the seventy-eight transistor Q78 may be connected to a first terminal of the seventy-eight transistor Q78. A first terminal of the seventy-ninth transistor Q79 may be connected to the second terminal of the seventy-eighth transistor Q78, a second terminal of the seventy-ninth transistor Q79 may be grounded VS, and a third terminal of the seventy-ninth transistor Q79 may be connected to the second terminal of the seventy-ninth transistor Q79. The control terminal of the seventy-eighth transistor Q78 may be connected to the control terminal of the seventy-ninth transistor Q79.

A third terminal of the eighteenth transistor Q80 may be connected to the first terminal of the eighteenth transistor Q80. A first terminal of the eighty-first transistor Q81 may be connected to the second terminal of the eighty-first transistor Q80, a second terminal of the eighty-first transistor Q81 may be connected to the ground VS, and a third terminal of the eighty-first transistor Q81 may be connected to the second terminal of the eighty-first transistor Q81. Wherein a control terminal of the eighteenth transistor Q80 may be connected to a control terminal of the seventeenth transistor Q81, and a node thereof may be connected between a first terminal of the seventeenth transistor Q79 and a second terminal of the seventy-eighth transistor Q78.

A third terminal of the eighth transistor Q82 may be connected to the first terminal of the eighth transistor Q82. A first terminal of the eighty-third transistor Q83 may be coupled to the second terminal of the eighty-third transistor Q82, a second terminal of the eighty-third transistor Q83 may be coupled to the ground VS, and a third terminal of the eighty-third transistor Q83 may be coupled to the second terminal of the eighty-third transistor Q83. Wherein a control terminal of the eighth twelve transistor Q82 may be coupled to a control terminal of the eighth three transistor Q83, and a node thereof may be coupled between a first terminal of the eighth one transistor Q81 and a second terminal of the eighth transistor Q80.

Wherein, the first terminal of the seventy-eighth transistor Q78, the first terminal of the eighty-transistor Q80 and the first terminal of the eighty-transistor Q82 may be connected, a node thereof is connected to the first terminal of the fourth resistor R4, and a connection node between the four may be connected to a high voltage power source.

A first terminal of the eighty-fourth transistor Q84 may be connected to the high voltage power supply, a third terminal of the eighty-fourth transistor Q84 may be connected to the first terminal of the eighty-fourth transistor Q84, and a control terminal of the eighty-fourth transistor Q84 may be connected between the first terminal of the seventy-seventh transistor Q77 and the second terminal of the seventy-sixth transistor Q76.

A first terminal of the eighty-fifth transistor Q85 may be connected to the second terminal of the eighty-fourth transistor Q84, a second terminal of the eighty-fifth transistor Q85 may be connected to the ground VS, and a third terminal of the eighty-fifth transistor Q85 may be connected to the second terminal of the eighty-fifth transistor Q85. A control terminal of the eighty-fifth transistor Q85 may be connected between a connection node between the second terminal of the eighty-transistor Q82 and the first terminal of the eighty-third transistor Q83 and the second terminal of the fourth resistor.

The anode of the first diode D1 may be connected between the second terminal of the eighty-fourth transistor Q84 and the first terminal of the eighty-fifth transistor Q85, and the cathode of the first diode D1 may be connected to the high voltage power supply. The cathode of the second diode D2 may be connected to the anode of the first diode D1, and the anode of the second diode D2 may be grounded. The cathode of the third diode D3 may be connected to the high voltage power supply, and the anode of the third diode D3 may be grounded VS. The first diode D1, the second diode D2, and the third diode D3 can limit the voltage direction in the high voltage output circuit 122 to prevent reverse current.

The connection node between the control terminal of the seventy-eighth transistor Q72 and the control terminal of the seventy-thirteenth transistor Q73 may be connected to the connection node between the control terminal of the seventy-eighth transistor Q78 and the control terminal of the seventy-ninth transistor Q79, and the connection node may be used as an input terminal of the high voltage output circuit 122 to receive the pulse signal. The connection node between the second terminal of the eighty-four transistor Q84 and the first terminal of the eighty-five transistor Q85 may serve as an output terminal of the high voltage output circuit 122 to output a high voltage output signal.

In the present embodiment, the seventy transistor Q72, the seventy-fourth transistor Q74, the seventy-sixth transistor Q76, the seventy-eighth transistor Q78, the eighty-transistor Q80, the eighth twelve transistor Q82, and the eighty-fourth transistor Q84 may be PMOS transistors.

The seventy-third transistor Q73, the seventy-fifth transistor Q75, the seventy-seventh transistor Q77, the seventy-ninth transistor Q79, the eighty-first transistor Q81, the eighty-thirteenth transistor Q83, and the eighty-fifth transistor Q85 may be NMOS transistors.

In addition, in the seventy-fifth transistor Q72 to the eighty-fifth transistor Q85, the control end may be a gate of the MOS transistor, the first end may be a source/drain of the MOS transistor, the second end may be a source/drain of the MOS transistor, and the third end may be a substrate electrode of the MOS transistor.

When the control terminal of the eighty-fourth transistor Q84 receives a low level while the high voltage output circuit 122 is in operation, the eighty-fourth transistor Q84 is turned on, and the high voltage power source flows from the first terminal to the second terminal of the eighty-fourth transistor Q84 and is further output from the output terminal of the high voltage output circuit 122.

With continued reference to fig. 1, the second output circuit 130 may be a low voltage output circuit 130. The low voltage output circuit 130 may be configured to receive the intermediate signal and generate a low voltage output signal based on the intermediate signal.

Referring to fig. 7, fig. 7 is a schematic circuit diagram of an embodiment of the low voltage output circuit in fig. 1. In the present embodiment, the low voltage output circuit 130 may include the following:

A first terminal of the eighty-sixth transistor Q86 may be connected to the power supply VCC and a third terminal of the eighty-sixth transistor Q86 may be connected to the first terminal of the eighty-sixth transistor Q86. A first terminal of the eighty-seventh transistor Q87 may be connected to the second terminal of the eighty-sixth transistor Q86, a second terminal of the eighty-seventh transistor Q87 may be connected to the common terminal COM, and a third terminal of the eighty-seventh transistor Q87 may be connected to the second terminal of the eighty-seventh transistor Q87. Wherein the control terminal of the eighty-sixth transistor Q86 may be connected to the control terminal of the eighty-seventh transistor Q87.

A first terminal of the eighty-eight transistor Q88 may be connected to the power supply VCC and a third terminal of the eighty-eight transistor Q88 may be connected to the first terminal of the eighty-eight transistor Q88. A first terminal of the eighty-ninth transistor Q89 may be connected to the second terminal of the eighty-eighth transistor Q88, a second terminal of the eighty-ninth transistor Q89 may be connected to the common terminal COM, and a third terminal of the eighty-ninth transistor Q89 may be connected to the second terminal of the eighty-ninth transistor Q89. Wherein a control terminal of the eighty-eighth transistor Q88 may be connected to a control terminal of the eighty-ninth transistor Q89, and a node thereof may be connected between a first terminal of the eighty-seventh transistor Q87 and a second terminal of the eighty-sixth transistor Q86.

A first terminal of the ninety transistor Q90 may be connected to the power supply VCC and a third terminal of the ninety transistor Q90 may be connected to the first terminal of the ninety transistor Q90. A first terminal of the ninety-first transistor Q91 may be connected to the second terminal of the ninety-first transistor Q90, a second terminal of the ninety-first transistor Q91 may be connected to the common terminal COM, and a third terminal of the ninety-first transistor Q91 may be connected to the second terminal of the ninety-first transistor Q91. Wherein a control terminal of the nineteenth transistor Q90 may be connected to a control terminal of the nineteenth transistor Q91, and a node thereof may be connected between a first terminal of the eighteenth transistor Q89 and a second terminal of the eighty-eighth transistor Q88.

A first terminal of the ninety transistor Q92 may be connected to the power source VCC and a third terminal of the ninety transistor Q92 may be connected to the first terminal of the ninety transistor Q92. A first terminal of the ninety-third transistor Q93 may be connected to the second terminal of the ninety-third transistor Q92, a second terminal of the ninety-third transistor Q93 may be connected to the common terminal COM, and a third terminal of the ninety-third transistor Q93 may be connected to the second terminal of the ninety-third transistor Q93. The control terminal of the ninth transistor Q92 may be connected to the control terminal of the ninety-third transistor Q93.

A first terminal of the ninety-fourth transistor Q94 may be connected to the power supply VCC and a third terminal of the ninety-fourth transistor Q94 may be connected to the first terminal of the ninety-fourth transistor Q94. A first terminal of the ninety-fifth transistor Q95 may be connected to the second terminal of the ninety-fourth transistor Q94, a second terminal of the ninety-fifth transistor Q95 may be connected to the common terminal COM, and a third terminal of the ninety-fifth transistor Q95 may be connected to the second terminal of the ninety-fifth transistor Q95. Wherein a control terminal of the ninety-fourth transistor Q94 may be coupled to a control terminal of the ninety-fifth transistor Q95, and a node thereof may be coupled between a first terminal of the ninety-third transistor Q93 and a second terminal of the ninety-transistor Q92.

A first terminal of the ninety-sixth transistor Q96 may be connected to the power supply VCC and a third terminal of the ninety-sixth transistor Q96 may be connected to the first terminal of the ninety-sixth transistor Q96. A first terminal of the ninety-seventh transistor Q97 may be connected to the second terminal of the ninety-sixth transistor Q96, a second terminal of the ninety-seventh transistor Q97 may be connected to the common terminal COM, and a third terminal of the ninety-seventh transistor Q97 may be connected to the second terminal of the ninety-seventh transistor Q97. Wherein a control terminal of the ninety-sixth transistor Q96 may be connected to a control terminal of the ninety-seventh transistor Q97, and a node thereof may be connected between a first terminal of the ninety-fifth transistor Q95 and a second terminal of the ninety-fourth transistor Q94.

A first terminal of the ninety-eight transistor Q98 may be connected to the power supply VCC, a third terminal of the ninety-eight transistor Q98 may be connected to the first terminal of the ninety-eight transistor Q98, and a control terminal of the ninety-eight transistor Q98 may be connected between the first terminal of the ninety-one transistor Q91 and the second terminal of the ninety-transistor Q90.

A first terminal of the ninety-ninth transistor Q99 may be connected to the second terminal of the ninety-eighth transistor Q98, a second terminal of the ninety-ninth transistor Q99 may be connected to the common terminal COM, and a third terminal of the ninety-ninth transistor Q99 may be connected to the second terminal of the ninety-ninth transistor Q99. A control terminal of the ninety-ninth transistor Q99 may be connected between the second terminal of the ninety-sixth transistor Q96 and the first terminal of the ninety-seventh transistor Q97.

Wherein a first terminal of the fifth resistor R5 may be connected to the power supply VCC, and a second terminal of the fifth resistor R5 may be connected between a node between the second terminal of the ninety-sixth transistor Q96 and the first terminal of the ninety-seventh transistor Q97 and the control terminal of the ninety-ninth transistor Q99.

The cathode of the fourth diode D4 may be connected to the power source VCC, the anode of the fourth diode D4 may be connected to the cathode of the fifth diode D5, and the anode of the fifth diode D5 may be connected to the common terminal COM. Alternatively, the common terminal COM may be a ground terminal. The fourth diode D4 and the fifth diode D5 limit the voltage direction in the low voltage output circuit 130, and prevent reverse current.

The connection node of the control terminal of the eighty-sixth transistor Q86 and the control terminal of the eighty-seventh transistor Q87 may be connected to the connection node of the control terminal of the ninety-third transistor Q92 and the control terminal of the ninety-third transistor Q93, and the node thereof may be used as an input terminal of the low voltage output circuit 130 to receive the pulse signal. The connection node between the second terminal of the ninety-eight transistor Q98 and the first terminal of the ninety-nine transistor Q99 may serve as an output terminal of the low voltage output circuit 130 to output a low voltage output signal.

In the present embodiment, the eighty-sixth transistor Q86, the eighty-eighth transistor Q88, the ninety-fourth transistor Q90, the ninety-fourth transistor Q92, the ninety-sixth transistor Q94, the ninety-sixth transistor Q96, and the ninety-eighth transistor Q98 may be PMOS transistors.

The eighty-seventh transistor Q87, the eighty-ninth transistor Q89, the ninety-first transistor Q91, the ninety-third transistor Q93, the ninety-fifth transistor Q95, the ninety-seventh transistor Q97, and the ninety-ninth transistor Q99 may be NMOS transistors.

In addition, in the eighty-sixth transistor Q86 to the ninety-ninth transistor Q99, the control end may be a gate of the MOS transistor, the first end may be a source/drain of the MOS transistor, the second end may be a source/drain of the MOS transistor, and the third end may be a substrate electrode of the MOS transistor.

When the control terminal of the ninety-eight transistor Q98 receives a low level during operation of the low voltage output circuit 130, the ninety-eight transistor Q98 is turned on, and the power VCC flows from the first terminal to the second terminal of the ninety-eight transistor Q98 and is further output from the output terminal of the low voltage output circuit 130.

In addition, the driving circuit of the present embodiment includes three grounds, namely, a VSS input ground, a VS high voltage output ground and a COM low voltage output ground. The three are obviously different.

In the present application, the transistor may be not only a MOS transistor in the above embodiment, but also a BJT (Bipolar Junction Transistor ), and the type of the transistor is not limited herein.

In the related art driving circuit, the high and low voltage control signals pass through the respective rectifying and filtering circuits and the level shifting circuit, so that there is a problem of matching the high and low voltage control signals. In addition, in such a driving circuit, an additional penetration preventing protection circuit is required to improve the safety and reliability of the whole system. Compared with the related art, the application can adopt the same rectifying and filtering circuit and level shifting circuit, solves the problem of matching high-low voltage control signals, and has better matching property of the high-low voltage control signals; meanwhile, the problem of penetration of an upper bridge and a lower bridge is solved by using an edge trigger circuit, a selection switch, a rectifying and filtering circuit and the like, so that the safety is greatly improved; in addition, the circuit has simple structure, small area of the chip bearing the driving circuit and low cost.

Based on the above-mentioned driving circuit 100, the present application also proposes a home appliance. Referring to fig. 8, fig. 8 is a schematic structural view of an embodiment of the household appliance of the present application. The home appliance 200 may include the driving circuit 200 described above. Among them, the home appliance 200 may include, but is not limited to, a refrigerator, a television, a washing machine, etc., and is not specifically recited herein.

It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. Further, for convenience of description, only some, but not all, of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and the like in this disclosure are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims

1. A driving circuit, characterized in that the driving circuit comprises:

a first input configured to input a first signal;

A second input configured to input a second signal;

the signal processing circuit is configured to process the input signal to obtain an intermediate signal;

A first output circuit;

a second output circuit;

The selection circuit is connected with the signal processing circuit and is configured to control the signal processing circuit to be alternatively connected with the first output circuit or the second output circuit according to the input signal so as to enable the first output circuit or the second output circuit to process the intermediate signal to obtain an output signal;

the selection circuit is connected to the first input terminal and the second input terminal, and the selection circuit is configured to control the signal processing circuit to connect to the first output circuit in response to receiving the first signal, or to control the signal processing circuit to connect to the second output circuit in response to receiving the second signal.

2. The driving circuit according to claim 1, wherein,

The selection circuit includes:

the edge trigger circuit is connected with the first input end and the second input end and is used for generating a trigger signal according to the first signal or the second signal;

The switch circuit comprises a first connecting end, a second connecting end and a control end, wherein the first connecting end is connected with the signal processing circuit, the control end is used for inputting the trigger signal, and the second connecting end is used for alternatively connecting the first output circuit or the second output circuit according to the trigger signal.

3. The drive circuit of claim 2, wherein the edge trigger circuit comprises a JK flip-flop comprising:

the J signal input end is connected with the first input end;

the K signal input end is connected with the second input end;

The signal output end is connected with the control end of the switch circuit, and the second connection end of the switch circuit is used for alternatively connecting the first output circuit or the second output circuit according to the trigger signal output by the JK trigger.

4. The drive circuit according to claim 1, wherein the signal processing circuit includes:

The rectification filter circuit is connected with the first input end and the second input end, and is used for receiving the input signal from the first input end or the second input end, carrying out rectification filter processing on the input signal and outputting a rectification filter signal;

And the level shift circuit is connected with the output end of the rectification filter circuit, receives the rectification filter signal, performs level shift processing on the rectification filter signal and outputs the intermediate signal.

5. The drive circuit according to claim 4, wherein the rectifying-and-filtering circuit includes:

A first transistor, a control end of which is used for receiving the input signal, and a first end of which is used for being connected with a power supply;

The control end of the second transistor is connected with the control end of the first transistor, the control end of the second transistor is used for receiving the input signal, the first end of the second transistor is used for being connected with the second end of the first transistor, and the second end of the second transistor is grounded;

a first capacitor, wherein a first end of the first capacitor is connected between a first end of the second transistor and a second end of the first transistor through a first resistor, and a second end of the first capacitor is grounded;

a third transistor, a first end of which is connected with the power supply;

A fourth transistor, a first end of which is connected with a second end of the third transistor, and a third end of which is connected with a third end of the third transistor;

a fifth transistor, a first end of which is connected with a second end of the fourth transistor;

A sixth transistor, a first end of the sixth transistor is connected to the second end of the fifth transistor, a second end of the sixth transistor is grounded, and a third end of the sixth transistor is connected to the third end of the fifth transistor;

The control end of the third transistor, the control end of the fourth transistor, the control end of the fifth transistor and the control end of the sixth transistor are connected, and the nodes of the control ends are connected between the first resistor and the first end of the first capacitor;

A seventh transistor having a first terminal connected between the second terminal of the third transistor and the first terminal of the fourth transistor, a third terminal of the seventh transistor being connected to the power supply;

An eighth transistor having a second terminal connected between the second terminal of the fifth transistor and the first terminal of the sixth transistor, the third terminal of the eighth transistor being connected to ground;

Wherein the control terminal of the seventh transistor is connected to the control terminal of the eighth transistor, and the node thereof is connected between the first terminal of the fifth transistor and the second terminal of the fourth transistor;

A ninth transistor, a control terminal of which is connected to the second terminal of the seventh transistor and to ground, a first terminal of which is connected to the power supply, and a second terminal of which is connected to the first terminal of the eighth transistor;

a tenth transistor, a first end of which is connected to the power supply;

an eleventh transistor, a first terminal of the eleventh transistor being connected to a second terminal of the tenth transistor, a second terminal of the eleventh transistor being grounded;

Wherein the control terminal of the tenth transistor is connected to the control terminal of the eleventh transistor, and a node thereof is connected between the control terminal of the seventh transistor and the control terminal of the eighth transistor;

a twelfth transistor, a first terminal of which is connected to the power supply;

a thirteenth transistor, a first end of which is connected to a second end of the twelfth transistor, a node of which is used as an output end of the rectifying and filtering circuit, and a second end of which is grounded;

wherein the control terminal of the twelfth transistor is connected to the control terminal of the thirteenth transistor, and the node thereof is connected between the second terminal of the tenth transistor and the first terminal of the eleventh transistor.

6. The driving circuit according to claim 5, wherein,

The rectifying and filtering circuit further comprises a protection circuit, and the protection circuit comprises:

a first NOT gate, wherein the input end of the first NOT gate receives the first signal;

The first input end of the first AND gate is connected with the output end of the first NOT gate, and the second input end of the first AND gate receives the second signal;

A second NOT gate, the input end of which receives the second signal;

the first input end of the second AND gate is connected with the output end of the second NOT gate, and the second input end of the second AND gate receives the first signal;

The first input end of the first OR gate is connected with the output end of the first AND gate, the second input end of the first OR gate is connected with the output end of the second AND gate, and the output end of the first OR gate is connected between the control end of the first transistor and the control end of the second transistor.

7. The drive circuit of claim 1, wherein a voltage value of the first signal is greater than a voltage value of the second signal, the first signal being a high voltage signal and the second signal being a low voltage signal;

the first output circuit includes:

the pulse generation circuit is used for receiving the intermediate signal and generating a pulse signal according to the intermediate signal;

And the high-voltage output circuit is used for receiving the pulse signal and generating a high-voltage output signal according to the pulse signal.

8. The drive circuit of claim 7, wherein the second output circuit comprises:

and the low-voltage output circuit is used for receiving the intermediate signal and generating a low-voltage output signal according to the intermediate signal.

9. A household appliance comprising a drive circuit as claimed in any one of the preceding claims 1-8.