CN112117922B - Half-cycle space vector pulse modulation method of single-phase three-level converter - Google Patents

Abstract

The invention discloses a half-cycle space vector pulse modulation method of a single-phase three-level converter, which divides each PWM cycle into two half-cycle interruptions, and then performs voltage vector synthesis respectively. According to the relationship between the given voltage and the initial voltage vector of this interruption period, the output voltage pulse is divided into three types of pulses, and the pulse jump in this period is integrated with the redundant vector jump of the midpoint voltage equalization. The switching loss can be effectively reduced, and at the same time, the balanced control of the three-level mid-point voltage can be achieved; the modulation method proposed by the present invention can effectively reduce the modulation control delay, improve the dynamic performance, and reduce the current harmonic content; the present invention can also Effectively control the voltage change rate (dv/dt) in medium and high voltage systems, and reduce the impact of excessive dv/dt on motor insulation and sensitive electronic equipment.

Description

A half-cycle space vector pulse modulation method for single-phase three-level converter

technical field

The invention belongs to the technical field of power electronics and electric drive, and in particular relates to a half-cycle space vector pulse modulation method of a single-phase three-level converter.

Background technique

In medium-voltage and high-power transmission systems, large-capacity and high-performance converters are widely used. In order to improve the capacity level of the system, the converter mostly adopts the topology structure of single-phase and multi-level. The Pulse Width Modulation (PWM, Pulse Width Modulation) method is the core technology of the converter, which directly affects the performance index of the device. At present, the most widely used PWM methods mainly include: carrier-based sinusoidal PWM method (SPWM) and space vector-based PWM method (SVPWM). The basic principle of SPWM is to compare n-1 triangular carriers with the same frequency and amplitude of n levels with the modulated wave to obtain the corresponding switching signal, but the voltage utilization rate is low and it is difficult to flexibly realize the centering. The shortcomings of the point-clamped inverter's mid-point voltage equalization control; and the SVPWM, based on the concept of voltage space vector, has the advantages of high voltage utilization and easy digital implementation, and has been widely used in engineering. However, the SVPWM method of traditional single-phase converters still cannot take into account the requirements of multiple indicators such as switching loss, DC voltage equalization, output harmonic characteristics, and voltage change rate (dv/dt) limit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to address the deficiencies of the above technologies, and to provide a single-phase three-level converter that can not only effectively optimize the switching times of switching devices, reduce switching losses, but also realize balanced control of the three-level midpoint voltage. Half-cycle space vector pulse modulation method.

In order to realize the above-mentioned purpose, the half-cycle space vector pulse modulation method of the single-phase three-level converter designed by the present invention, the concrete steps are as follows:

Step 1: Obtain the given voltage value V _ref expected to be output by the converter in each interruption period, and normalize the given voltage V _ref according to the DC bus voltage V _dc of the converter. The constant voltage V ^* is

V ^* = _Vref / _Vdc (1)

The range of the normalized given voltage V ^* is limited to -1≤V ^* ≤1;

Step 2. Use the termination vector of the previous interrupt cycle as the initial vector V _i of the current cycle, and judge the output pulse type with the normalized given voltage V ^* . There are three types of pulse types, which are pulse type 1. , pulse type 2, pulse type 3:

V_th为归一化后的电压阈值，T_pmin为最小脉宽对应的时间，T_pwm为PWM的周期时间；in,

V _th is the normalized voltage threshold, T _pmin is the time corresponding to the minimum pulse width, and T _pwm is the cycle time of PWM;

Step 3: According to the output pulse type, calculate the output switching vector of the converter and the vector action time;

Step 4: Limit the vector action time according to the minimum pulse width limit corresponding time t _pmin , so as to obtain the corrected vector action time;

Step 5. Redundant vector selection of the switching vector is performed according to the midpoint voltage and the direction of the output AC current;

Step 6. At the beginning of each interrupt cycle, latch the data of the vector duty cycle buffer into the vector register; before the end of the interrupt cycle, write the vector duty cycle calculated in the current cycle into the vector duty cycle buffer in the device;

Step 7: Compare the data value of the duty cycle with the value of the triangular carrier counter, and generate the corresponding PWM modulation pulse after passing through the dead zone circuit.

Further, in the step 1, the interruption period is half of the PWM period. According to the preset PWM period, a bidirectional counter is used for counting to generate a triangular carrier wave, and an interruption signal is respectively generated at the trough and the peak of each triangular carrier wave.

Further, in the step 2,

Pulse type 1, the given voltage is close to the initial voltage vector, the output voltage of the converter does not jump, and the switching vector of the previous interruption cycle is maintained;

Pulse type 2, the level difference between the given voltage and the initial voltage vector is less than 0.5 times the DC voltage V _dc , and the output voltage pulse is a two-level level jump;

Pulse type 3, when the level difference between the given voltage and the initial voltage vector is other, the output voltage pulse is a three-level level jump.

Further, in the step 3,

Pulse type 1, the expression of termination vector V _f is

V _f =V _i

Based on the volt-second balance rule, the action time t _f of the termination vector is calculated as:

t _f =0.25T _pwm

Pulse type 2. First, calculate the output termination vector V _f according to V ^* . The calculation formula is as follows:

Based on the volt-second balance rule, the action time t _f of the termination vector is calculated as:

Pulse type 3. First, calculate the intermediate vector V _m and the output termination vector V _f respectively according to V ^* . The calculation formula is as follows:

Based on the volt-second balance rule, the action time t _m of the intermediate vector and the action time t _f of the termination vector are calculated as:

Further, in the step 4,

Pulse Type 1

Since there is no jump in the output pulse, there is no narrow pulse phenomenon in pulse type 1;

Pulse Type 2

The vector action time after the minimum pulse width limit is

Pulse Type 3

The vector action time after the minimum pulse width limit is

Further, in the step 5, the redundant vector selection of the switching vector of the single-phase three-level H-bridge converter topology through the midpoint voltage and the output AC current i _L direction is as follows:

When the voltage V _c1 across the capacitor C1 is greater than or equal to the voltage V _c2 across the capacitor C2, the output level ±0.5V _dc switching vector selection is respectively

When the voltage V _c1 across the capacitor C1 is less than the voltage V _c2 across the capacitor C2, the output level ±0.5V _dc switching vector selection is respectively

Compared with the prior art, the present invention has the following advantages:

1. Use the termination vector of the previous interrupt cycle as the initial vector of the current cycle to synthesize the voltage vector, and at the same time combine the pulse jump in the current cycle with the redundant vector selection of the midpoint voltage equalization, which can not only effectively optimize the switching device performance. Switching times, reducing switching loss, and realizing balanced control of three-level midpoint voltage;

2. The interruption period is half of the PWM period, and the total delay time of PWM modulation control is reduced from 1.5 times the PWM period to 0.75 times, which can effectively improve the dynamic performance of the converter, and the output harmonic characteristics are good;

3. The maximum level jump amplitude of the output voltage is limited to 0.5V _dc , which can effectively control the voltage change rate (dv/dt) in the medium and high voltage system and improve the system performance;

4. The method can be easily implemented by a digital signal processor (DSP) and a programmable logic gate array (FPGA), and has the advantages of simple algorithm, less computation and simple implementation.

Description of drawings

Fig. 1 is the topological structure diagram of the main circuit of the single-phase three-level H-bridge converter involved in the present invention;

Fig. 2 is the DSP program flow diagram of the half-cycle space vector pulse modulation method of the single-phase three-level converter of the present invention;

3 is a logic block diagram of PWM generation in the half-cycle space vector pulse modulation method of the single-phase three-level converter of the present invention.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

The present invention is aimed at the topology structure of a single-phase three-level H-bridge converter (as shown in Figure 1), and proposes a half-cycle space vector pulse modulation method for a single-phase three-level converter. The cycle is divided into two half-cycle interruptions, and then voltage vector synthesis is performed separately. According to the relationship between the given voltage and the initial voltage vector of the current interruption cycle, the output voltage pulse is divided into three types of pulses, and the pulse jump in the current cycle is integrated with the redundant vector jump of the midpoint voltage equalization. The switching loss can be effectively reduced, and at the same time, the balanced control of the three-level midpoint voltage can be realized; the modulation method proposed by the invention can effectively reduce the modulation control delay, improve the dynamic performance, and reduce the current harmonic content; it can also effectively control Voltage change rate (dv/dt) in medium and high voltage systems, reducing the impact of excessive dv/dt on motor insulation and sensitive electronic equipment.

The specific steps of the half-cycle space vector pulse modulation method of the single-phase three-level converter are as follows:

Step 1: Obtain the given voltage value V _ref expected to be output by the converter in each interruption period, and normalize the given voltage V _ref according to the DC bus voltage V _dc of the converter. The constant voltage V ^* is

V ^* = _Vref / _Vdc (1)

The range of the normalized given voltage V ^* is limited to -1≤V ^* ≤1;

Among them, the interruption period is half of the PWM (pulse) period. The FPGA (to the programmable logic device) counts by the bidirectional counter according to the preset PWM period, generates a triangular carrier, and generates interrupts at the trough and peak of each triangular carrier. Signal, output hardware interrupt signal to DSP (digital signal processing) external interrupt after interrupting logic circuit;

Step 2. Use the termination vector of the previous interrupt cycle as the initial vector V _i of the current cycle, and judge the output pulse type with the normalized given voltage V ^* . There are three types of pulse types, which are pulse type 1. , pulse type 2, pulse type 3:

V_th为归一化后的电压阈值，T_pmin为最小脉宽对应的时间，T_pwm为PWM的周期时间；in,

V _th is the normalized voltage threshold, T _pmin is the time corresponding to the minimum pulse width, and T _pwm is the cycle time of PWM;

Pulse type 1, the given voltage is very close to the initial voltage vector, the output voltage of the converter does not jump, and the switching vector of the previous interruption cycle is maintained;

Pulse type 2, the level difference between the given voltage and the initial voltage vector is less than 0.5 times the DC voltage V _dc , and the output voltage pulse is a two-level level jump;

Pulse type 3, when the level difference between the given voltage and the initial voltage vector is other, the output voltage pulse is a three-level level jump;

Step 3: According to the output pulse type, calculate the output switching vector of the converter and the vector action time;

Pulse type 1. The given voltage is very close to the initial voltage vector, the output voltage of the converter does not jump, and the switching vector of the previous interruption cycle is maintained. At this time, the expression of the termination vector V _f is:

V _f =V _i

Based on the volt-second balance rule, the action time t _f of the termination vector is calculated as:

t _f =0.25T _pwm

Pulse type 2. First, calculate the output termination vector V _f according to V ^* . The calculation formula is as follows:

Based on the volt-second balance rule, the action time t _f of the termination vector is calculated as:

Pulse type 3. First, calculate the intermediate vector V _m and the output termination vector V _f respectively according to V ^* . The calculation formula is as follows:

Based on the volt-second balance rule, the action time t _m of the intermediate vector and the action time t _f of the termination vector are calculated as:

Step 4: Limit the vector action time according to the minimum pulse width limit corresponding time t _pmin , so as to obtain the corrected vector action time;

(1) Pulse type 1

Since there is no jump in the output pulse, there is no narrow pulse phenomenon in pulse type 1;

(2) Pulse type 2

If the initial vector action time t _i (k) calculated in the current interrupt cycle is less than or equal to the action time t _f (k) of the termination vector, then if the initial vector action time t _i (k) of the current cycle and the termination vector of the previous interrupt cycle If the sum of the action time t _f (k-1) is less than the minimum pulse width limit value t _pmin , a narrow pulse will be formed, and the pulse width needs to be limited; similarly, if the initial vector action time t _i (k) calculated by the current interrupt cycle is greater than the action time t _f (k) of the termination vector, but if the termination vector action time t _f (k) of the current cycle is less than 0.5t _pmin , it may be different from the initial vector action time t _i (k+ 1) To form a narrow pulse, therefore, the pulse width also needs to be limited; the vector action time after the minimum pulse width limit is

(3) Pulse type 3

The action time t _i (k) of the initial vector and the action time t _f (k) of the termination vector The minimum pulse width limitation method is the same as that of the pulse type 2. In addition to the initial vector and the termination vector, the pulse type 3 and the intermediate vector need to be minimized. Pulse width limit. If the action time t _m (k) of the middle vector in the current cycle is less than the minimum pulse width limit value t _pmin , a narrow pulse will be formed, and the pulse width needs to be limited; therefore, for pulse type 3, the vector after the minimum pulse width limit The action time is

Step 5. Redundant vector selection of the switching vector is performed according to the midpoint voltage and the direction of the output AC current;

The present invention is directed to the topology of the single-phase three-level H-bridge converter as shown in FIG. 1 , and each three-level half-bridge unit has three switching states of P, O, and N respectively. Taking the A1 bridge arm as an example, in the P state, the terminal voltage V _A1M of the converter A1 end relative to the midpoint M is 0.5V _dc ; in the O state, the terminal voltage V _A1M of the converter A1 end relative to the midpoint M is: 0; N state, the terminal voltage V _A1M of the converter A1 terminal relative to the midpoint M is -0.5V _dc . Similarly, the A2 bridge arm also has three switch states: P, O, and N. The voltage V _A1A2 at both ends of the A-phase winding has five output levels, ±V _dc , ±0.5V _dc , 0, of which the output level 0.5V _dc has two redundant switching vectors [PO] and [ON]. Flat-0.5V _dc has two redundant switching vectors [NO] and [OP]. Since the redundant vectors have opposite influences on the neutral point voltage, the switching can be performed through the neutral point voltage and the output AC current i _L direction. The redundant vector selection of the vector is as follows:

When the voltage V _c1 across the capacitor C1 is greater than or equal to the voltage V _c2 across the capacitor C2, the output level ±0.5V _dc switching vector selection is respectively

When the voltage V _c1 across the capacitor C1 is less than the voltage V _c2 across the capacitor C2, the output level ±0.5V _dc switching vector selection is respectively

Step 6. At the beginning of each interrupt cycle, latch the data of the vector duty cycle buffer into the vector register; before the end of the interrupt cycle, write the vector duty cycle calculated in the current cycle into the vector duty cycle buffer in the device;

Step 7: Compare the data value of the duty cycle with the value of the triangular carrier counter, and generate the corresponding PWM modulation pulse after passing through the dead zone circuit.

FIG. 2 is a block diagram of a DSP program flow for implementing the space vector pulse width modulation method of the present invention provided by an embodiment of the present invention. First, the program is interrupted, and the DC voltage and output AC current are sampled, and the fault is judged according to the set protection threshold. If there is a fault, the PWM enable is no, the program enters the blockade pulse, and exits the interrupt. If there is no fault, the output voltage is normalized according to the given voltage command and the measured DC side bus voltage, as shown in formula (1). ; Then judge the pulse type, as shown in formula (2). According to the pulse type, when the output pulse is pulse type 1, the switch vector selection and duty cycle calculation subroutine of pulse type 1 is entered. At this time, the output pulse has no level jump, and the output pulse remains in the last interrupt period; When the pulse is pulse type 2, enter the switch vector selection and duty cycle calculation subroutine of pulse type 2, and the output pulse is a two-level level jump; when the output pulse is pulse type 3, enter the switch of pulse type 3 Vector selection and duty cycle calculation subroutine, at this time the output pulse is a three-level level jump. Then enter the minimum pulse width limiting procedure, as shown in equations (9) and (10), to obtain the corrected duty cycle. Then enter the midpoint voltage equalization subroutine, select the redundant vector of the switching vector according to the midpoint voltage and the direction of the output AC current; finally, output the switching vector and the duty cycle to the programmable logic device (FPGA).

FIG. 3 is a logic block diagram of PWM generation in an FPGA provided by an embodiment of the present invention. According to the set PWM cycle, the FPGA is counted by a bidirectional counter to generate a triangular carrier, and an interrupt signal is generated at the trough and peak of each triangular carrier. After the interrupt logic circuit, the hardware interrupt signal is output to the DSP external interrupt. At the trough or peak moment of each triangular carrier, the data in the switching vector and the duty cycle buffer are latched into the vector and duty cycle registers; before the next peak or trough, the FPGA transfers the switching vector sent by the DSP and duty cycle are saved to the switching vector and duty cycle buffer. After the triangular carrier and the duty cycle are compared by the comparator, the pulse output is carried out through the dead zone logic circuit, and the dead zone value in the dead zone logic is stored in the dead zone time register.

Those skilled in the art can easily understand that the above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, etc., All should be included within the protection scope of the present invention.

Claims (5)

1. a half-cycle space vector pulse modulation method of a single-phase three-level converter, is characterized in that: the concrete steps of described modulation method are as follows: Step 1: Obtain the given voltage value V _ref expected to be output by the converter in each interruption period, and normalize the given voltage V _ref according to the DC bus voltage V _dc of the converter. The constant voltage V ^* is V ^* = _Vref / _Vdc (1) The range of the normalized given voltage V ^* is limited to -1≤V ^* ≤1; Step 2. Use the termination vector of the previous interrupt cycle as the initial vector V _i of the current cycle, and judge the output pulse type with the normalized given voltage V ^* . There are three types of pulse types, which are pulse type 1. , pulse type 2, pulse type 3:

in,

V _th is the normalized voltage threshold, T _pmin is the time corresponding to the minimum pulse width, and T _pwm is the cycle time of PWM; Step 3: According to the output pulse type, calculate the output switching vector of the converter and the vector action time; Pulse type 1, the expression of termination vector V _f is V _f =V _i Based on the volt-second balance rule, the action time t _f of the termination vector is calculated as: t _f =0.25T _pwm Pulse type 2. First, calculate the output termination vector V _f according to V ^* . The calculation formula is as follows:

Based on the volt-second balance rule, the action time t _f of the termination vector is calculated as:

Pulse type 3. First, calculate the intermediate vector V _m and the output termination vector V _f respectively according to V ^* . The calculation formula is as follows:

Based on the volt-second balance rule, the action time t _m of the intermediate vector and the action time t _f of the termination vector are calculated as:

Step 4: Limit the vector action time according to the minimum pulse width limit corresponding time t _pmin , thereby obtaining the corrected vector action time; Step 5. Redundant vector selection of the switching vector is performed according to the midpoint voltage and the direction of the output AC current; Step 6. At the beginning of each interrupt cycle, latch the data of the vector duty cycle buffer into the vector register; before the end of the interrupt cycle, write the vector duty cycle calculated in the current cycle into the vector duty cycle buffer in the device; Step 7: Compare the data value of the duty cycle with the value of the triangular carrier counter, and generate the corresponding PWM modulation pulse after passing through the dead zone circuit. 2. The half-cycle space vector pulse modulation method of the single-phase three-level converter according to claim 1, is characterized in that: in the step 1, the interruption period is half of the PWM period, and according to the preset PWM period, It is counted by a bidirectional counter to generate a triangular carrier, and an interrupt signal is generated at the trough and peak of each triangular carrier. 3. The half-cycle space vector pulse modulation method of the single-phase three-level converter according to claim 1, is characterized in that: in the described step 2, Pulse type 1, the given voltage is close to the initial voltage vector, the output voltage of the converter does not jump, and the switching vector of the previous interruption cycle is maintained; Pulse type 2, the level difference between the given voltage and the initial voltage vector is less than 0.5 times the DC voltage V _dc , and the output voltage pulse is a two-level level jump; Pulse type 3, when the level difference between the given voltage and the initial voltage vector is other, the output voltage pulse is a three-level level jump. 4. The half-cycle space vector pulse modulation method of the single-phase three-level converter according to claim 1, wherein: in the step 4, Pulse Type 1 Since there is no jump in the output pulse, there is no narrow pulse phenomenon in pulse type 1; Pulse Type 2 The vector action time after the minimum pulse width limit is

Pulse Type 3 The vector action time after the minimum pulse width limit is

In the formula, k represents the current interrupt cycle, t _i (k) represents the initial vector action time calculated in the current interrupt cycle, t _f (k) represents the termination vector action time calculated in the current interrupt cycle, and t _m (k) represents the current interrupt cycle. Calculated intermediate vector action time. 5. The half-cycle space vector pulse modulation method of the single-phase three-level converter according to claim 1, characterized in that: in the step 5, the single-phase three-level H-bridge converter topology structure passes through the midpoint The redundant vector selection of switching vector in the direction of voltage and output AC current i _L is as follows: When the voltage V _c1 across the capacitor C1 is greater than or equal to the voltage V _c2 across the capacitor C2, the output level ±0.5V _dc switching vector selection is respectively

When the voltage V _c1 across the capacitor C1 is less than the voltage V _c2 across the capacitor C2, the output level ±0.5V _dc switching vector selection is respectively

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