CN112117356B - Full-color active addressing Micro-LED chip structure and manufacturing method thereof - Google Patents
Full-color active addressing Micro-LED chip structure and manufacturing method thereof Download PDFInfo
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Abstract
本发明涉及一种全彩有源寻址Micro‑LED芯片结构及其制作方法，包括具有驱动电路阵列的支撑衬底、位于支撑衬底上的堆叠层，以及贯穿堆叠层与驱动电路阵列连接的互联电极，其中堆叠层从下至上包括有衬底金属键合层、多色发光外延层上下表面覆盖有透明导电层的多层夹心结构、介质填充层、滤光层、钝化层，互联电极包括连接第一外延层的p型面与驱动像素的阵列电极、连接第二外延层p型面与驱动像素的贯穿阵列电极、连接第三外延层p型面与驱动像素的贯穿阵列电极、贯穿堆叠层分别与多色发光外延层n型面连接的共用电极。本发明技术方案可制造出高分辨率且高效的全彩驱动融合Micro‑LED芯片。
The invention relates to a full-color active addressing Micro-LED chip structure and a manufacturing method thereof, comprising a support substrate with a drive circuit array, a stack layer on the support substrate, and a stack layer connected to the drive circuit array through the stack layer. Interconnecting electrodes, wherein the stacked layers from bottom to top include a substrate metal bonding layer, a multi-color light-emitting epitaxial layer with a multi-layer sandwich structure covered with a transparent conductive layer on the upper and lower surfaces, a dielectric filling layer, a filter layer, and a passivation layer, and interconnecting electrodes It includes an array electrode connecting the p-type surface of the first epitaxial layer and the driving pixel, a through-array electrode connecting the p-type surface of the second epitaxial layer and the driving pixel, a through-array electrode connecting the p-type surface of the third epitaxial layer and the driving pixel, and a through-array electrode connecting the p-type surface of the third epitaxial layer and the driving pixel. The stacked layers are respectively connected with a common electrode connected to the n-type surface of the multi-color light-emitting epitaxial layer. The technical solution of the present invention can manufacture a high-resolution and high-efficiency full-color drive fusion Micro-LED chip.
Description
Technical Field
The invention relates to the technical field of semiconductor optoelectronic devices, in particular to a full-color active addressing Micro-LED chip structure and a manufacturing method thereof.
Background
As an active light emitting display technology, each of the red, green and blue sub-emitting pixels of the Micro-LED is an independently adjustable light source. Micro-LEDs not only have high contrast, high speed and wide viewing angle similar to Organic Light Emitting Diodes (OLEDs), but also can provide wider color gamut, higher brightness, lower power consumption, longer lifetime, greater durability and environmental stability. In addition, the Micro-LED can integrate a sensor and electronic circuits to form a thin film display, and is embedded in a sensing system such as fingerprint identification, gesture control and the like. Therefore, the Micro-LED display technology has wide application prospects in various consumption application fields such as wearable equipment, augmented reality, smart phones and televisions.
Currently, efficient Micro-LEDs capable of emitting red, green and blue colors are grown on the same substrate in one step only by an epitaxial growth technology, which still faces great difficulty, and epitaxial growth and processing technologies, transfer printing technologies (i.e., a mass transfer technology) and color conversion technologies based on Micro-nano structures become main technological development directions for realizing full-color Micro-LEDs. However, as the size of Micro-LED chips is further reduced, the precision and speed of chip array alignment and the chip yield and yield, which in turn affect the precision and speed, make the technology more challenging to mature and industrialize.
In order to avoid the restriction of the realization technology capability of arranging or aligning the chip arrays in the horizontal direction, the wafer bonding technology can integrate a plurality of functional films in the vertical direction of a single substrate, namely three different epitaxial layers of red, green and blue (RGB) form a vertical stacked array, so that the wafer bonding technology becomes a preferred scheme for full color Micro-LED, and can be applied to Micro-display application scenes requiring high brightness and high resolution, such as virtual reality, augmented reality, Micro-projection, head-up displays and the like. Geum et al, in academic journal Nanoscale (Nanoscale), Vol.11, p.23139-23148, disclose a method for manufacturing a vertical stacked full-color Micro-LED, which comprises passing three epitaxial layers of RGB through silicon dioxide/silicon nitride (SiO)2/SiNx) The Distributed Bragg Reflectors (DBRs) are respectively bonded on a support substrate which is prepared and used for completing the CMOS drive circuit array in a wafer bonding mode, the DBR layer serves as a wafer bonding layer and also serves as a filter layer, and the designed light-emitting wavelength is reflected or transmitted on a bonding interface; forming a light emitting pixel array by a semiconductor manufacturing process; finally, manufacturing leads to interconnect each single-color light-emitting pixel with the driving circuit array.
The manufacturing method enables the light-emitting pixels to realize the high-resolution full-color Micro-LED chip array without transfer printing or color conversion. However, the chip array lead manufactured by the method has a complex structure, each light-emitting pixel needs 6 leads, the increase of the density of the leads causes the increase of the parasitic resistance and capacitance of the chip, a large amount of power consumption is lost on the leads, and the efficiency of the chip is reduced. In addition, a large number of leads occupy more chip light-emitting areas, and the proportion of the light-emitting areas is limited, thereby restricting the improvement of the display resolution.
Disclosure of Invention
The invention mainly aims to overcome the defect of poor chip efficiency caused by the large number of electrode leads of a vertically stacked full-color Micro-LED chip in the prior art, and provides a full-color active addressing Micro-LED chip structure and a manufacturing method thereof.
The invention adopts the following technical scheme:
a full-color active addressing Micro-LED chip structure comprises a supporting substrate with a driving circuit, a stacking layer positioned on the supporting substrate, and an interconnection electrode penetrating through the stacking layer and electrically connected with the driving circuit, wherein the driving circuit is provided with a first driving pixel, a second driving pixel and a third driving pixel; the method is characterized in that: the stacking layers comprise a first stacking layer, a first medium filling layer, a second stacking layer, a second medium filling layer, a third stacking layer and a passivation layer from bottom to top; the first stacking layer is provided with a metal bonding layer and a first epitaxial layer, and is bonded with the supporting substrate through the metal bonding layer, and the metal bonding layer is positioned on a p-type surface of the first epitaxial layer; the first dielectric filling layer is deposited on the upper surface of the first stacking layer; the second stacking layer is provided with a first optical filter layer and a second epitaxial layer, and the first optical filter layer is bonded with the first medium filling layer; the second medium filling layer is deposited on the surface of the second stacking layer; the third stacking layer is provided with a third epitaxial layer and a second filter layer, and the second filter layer is bonded with the second medium filling layer; the interconnection electrode comprises a first p-type electrode, a second p-type electrode, a third p-type electrode and a common electrode, the first p-type electrode is electrically connected with the first driving pixel and the p-type surface of the first epitaxial layer, the second p-type electrode is electrically connected with the second driving pixel and the p-type surface of the second epitaxial layer, the third p-type electrode is electrically connected with the third driving pixel and the p-type surface of the third epitaxial layer, and the common electrode is positioned on the periphery of the stacking layer and is provided with a first n-type contact electrode, a second n-type contact electrode and a third n-type contact electrode which are respectively electrically connected with the n-type surface of the first epitaxial layer, the n-type surface of the second epitaxial layer and the n-type surface of the third epitaxial layer; the passivation layer is deposited on the upper surfaces of the third stacked layer and the interconnection electrode.
Preferably, the first stacked layer further comprises a first transparent conductive layer located on the first epitaxial layer n-type surface; the part of the metal bonding layer, which is electrically connected with the first driving pixel, forms the first p-type electrode; the first n-type contact electrode is electrically connected with the first transparent conducting layer; the first dielectric layer is deposited on the upper surface of the first n-type contact electrode.
Preferably, the second stacked layer further comprises a second transparent conductive layer deposited on the second epitaxial layer p-type surface and the first optical filter layer upper surface, and a third transparent conductive layer deposited on the second epitaxial layer n-type surface; the second p-type electrode penetrates through the first stacking layer and the second stacking layer and is electrically connected with the second transparent conducting layer; the second n-type contact electrode is electrically connected with the third transparent conducting layer; the second dielectric layer is also deposited on the upper surface of the second n-type contact electrode.
Preferably, the first filter layer or the second filter layer is a multilayer medium thin film and/or a medium micro-nano structure; the first filter layer has high reflectivity for light emitted by the second epitaxial layer and high transmissivity for light emitted by the first epitaxial layer; or the second filter layer has a high reflectivity for light emitted by the third epitaxial layer and a high transmissivity for light emitted by the first and second epitaxial layers.
Preferably, the third stacked layer further includes a fourth transparent conductive layer and a fifth transparent conductive layer, the fourth transparent conductive layer is deposited on the p-type surface of the third epitaxial layer and the upper surface of the second filter layer, and the fifth transparent conductive layer is deposited on the n-type surface of the third epitaxial layer; the third p-type electrode penetrates through the third, second and first stacked layers and is electrically connected to the fourth transparent conductive layer 231; the third n-type contact electrode is electrically connected with the fifth transparent conductive layer.
Preferably, a passivation layer is further arranged between the common electrode and the periphery of the stacked layer; a passivation layer is also arranged between the second P-type electrode and the stacked layer, and the first P-type electrode is positioned between the second P-type electrode and the third P-type electrode.
Preferably, the passivation layer is made of SiO2、SiNx、Al2O3Or HfO2Any one of them.
Preferably, the interconnection electrode is made of any one or more of aluminum, silver, rhodium, zinc, gold, germanium, nickel, chromium, platinum, tin, copper, tungsten, palladium, indium and titanium.
A manufacturing method of a full-color active addressing Micro-LED chip structure is characterized by comprising the following steps:
1) manufacturing a first stacked layer with a first epitaxial layer and a metal bonding layer, and bonding a support substrate with a driving circuit array and the first epitaxial layer through the metal bonding layer;
2) patterning the first stack layer to form light emitting pixels through a semiconductor manufacturing process, wherein each light emitting pixel comprises a first driving pixel, a second driving pixel and a third driving pixel; manufacturing a first p-type electrode on the first stacking layer, wherein the first p-type electrode is electrically connected with the first driving pixel and the p-type surface of the first epitaxial layer; manufacturing a first n-type contact electrode electrically connected with the n-type surface of the first epitaxial layer at the periphery of the first stacking layer;
3) depositing a first dielectric filling layer on the upper surface of the first stacking layer and the upper surface of the first n-type contact electrode; manufacturing a second stacking layer with a first filter layer and a second epitaxial layer, and bonding the first filter layer and the first medium filling layer; manufacturing a second p-type electrode, electrically connecting the second p-type electrode with a second driving pixel and the p-type surface of the second epitaxial layer, and manufacturing a second n-type contact electrode, electrically connected with the n-type surface of the second epitaxial layer, on the periphery of the second stacking layer;
4) depositing a second medium filling layer on the upper surface of the second stacked layer and the upper surface of the second n-type contact electrode; manufacturing a third stacking layer with a second filter layer and a third epitaxial layer, and bonding the second filter layer and the second medium filling layer; manufacturing a third p-type electrode, electrically connecting the third p-type electrode with the third driving pixel and the p-type surface of the third epitaxial layer, and manufacturing a third n-type contact electrode, electrically connected with the n-type surface of the third epitaxial layer, on the periphery of the third stacked layer;
5) and the first n-type contact electrode, the second n-type contact electrode and the third n-type contact electrode form a common electrode, the first p-type electrode, the second p-type electrode and the third p-type electrode form an interconnection electrode, and a passivation layer is deposited on the upper surfaces of the third stacked layer and the interconnection electrode.
Preferably, in step 2), when the first stacked layer is manufactured, a first transparent conductive layer is manufactured on the n-type surface of the first epitaxial layer; in the step 3), when the second stacked layer is manufactured, a step of manufacturing a second transparent conducting layer and a third transparent conducting layer on the p-type surface and the n-type surface of the second epitaxial layer respectively is further included; in step 4), when the third stacked layer is manufactured, a step of manufacturing a fourth transparent conductive layer and a fifth transparent conductive layer on the p-type surface and the n-type surface of the third epitaxial layer respectively is further included.
As can be seen from the above description of the present invention, compared with the prior art, the present invention has the following advantages:
the scheme of the invention avoids the technical obstacles for realizing the full-color Micro-LED chip by adopting a transfer printing technology or a color conversion technology; in addition, based on the characteristic that the chip alignment exposure technology is more mature than the chip alignment bonding technology, the LED stack layer is formed by repeatedly depositing, bonding and stripping the substrate on the support substrate through the manufacturing method of defining the light-emitting pixels in a graphical mode after wafer bonding, and the manufacturing difficulty of the chip is reduced; and thirdly, the three-dimensional active addressing electrode structure penetrating through the stacked layers reduces the number of leads, enhances the current distribution uniformity and further improves the efficiency of the full-color Micro-LED chip. The technical scheme of the invention can be used for manufacturing the high-resolution and high-efficiency full-color driving fusion Micro-LED chip.
Drawings
FIG. 1 is a cross-sectional view of a structure of the present invention (a single emissive pixel);
FIG. 2 is a cross-sectional view of the structure of the present invention (a plurality of light-emitting pixels);
FIG. 3 is a top view of a structure (a plurality of light-emitting pixels) according to the present invention;
FIG. 4 is a schematic diagram of a first stack layer;
FIG. 5 is a schematic view of fabricating a first via and a second via;
FIG. 6 is a schematic view of depositing a passivation layer;
FIG. 7 is a schematic view of filling with a conductive material;
FIG. 8 is a schematic diagram of a first dielectric fill layer;
FIG. 9 is a schematic view of fabricating a second stack of layers;
FIG. 10 is a schematic view of fabricating a third via and a fourth via;
FIG. 11 is a schematic view of the lateral dimension of the upper portion of the enlarged third through hole;
FIG. 12 is a schematic view of depositing a passivation layer;
FIG. 13 is a schematic view of filling with a conductive material;
FIG. 14 is a schematic view of fabricating a second dielectric fill layer;
FIG. 15 is a schematic view of forming a third stack of layers;
FIG. 16 is a schematic view of making a fifth via and a sixth via;
FIG. 17 is a schematic view of depositing a passivation layer;
FIG. 18 is a schematic view of filling with a conductive material;
FIG. 19 is a schematic view of depositing a passivation layer;
in the figure:
102. a support substrate, 110R, a first driving pixel, 110G, a second driving pixel, 110B, a third driving pixel, 201, a first stack layer, 210, a substrate metal bonding layer, 210R, an epitaxial metal bonding layer, 211, a first epitaxial layer, 212, a first transparent conductive layer, 213, a first dielectric fill layer, 202, a second stack layer, 220, a first optical layer, 221, a second transparent conductive layer, 222, a second epitaxial layer, 223, a third transparent conductive layer, 224, a second dielectric fill layer, 203, a third stack layer, 230, a second optical layer, 231, a fourth transparent conductive layer, 232, a third epitaxial layer, 233, a fifth transparent conductive layer, 240, a passivation layer, 301G, a first via, 301B, a second via, 302G, a third via, 302B, a fourth via, 310, a conductive material, 303G, a fifth via, 303B, a sixth via, 310, a conductive material, 312. a first n-type contact electrode, 311R, a first p-type electrode, 313, a second n-type contact electrode, 311G, a second p-type electrode, 314, a third n-type contact electrode, 311B, a third p-type electrode.
Detailed Description
The invention is further described below by means of specific embodiments.
The terms "first", "second", and the like in the present invention are merely for convenience of description to distinguish different constituent elements having the same name, and do not denote a sequential or primary-secondary relationship. In the description, the directions or positional relationships indicated by "upper", "lower", "left", "right", "front", and "rear" are used based on the directions or positional relationships shown in the drawings only for convenience of describing the present invention, and do not indicate or imply that the device referred to must have a specific direction, be constructed and operated in a specific direction, and thus, should not be construed as limiting the scope of the present invention.
The terms "first," "second," "third," and the like in this disclosure are used solely to distinguish between similar items and not necessarily to describe a particular order or sequence, nor are they to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate. In addition, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
Referring to fig. 1, a full-color active addressing Micro-LED chip structure includes a supporting substrate 102 having a driving circuit, a stack layer on the supporting substrate 102, and an interconnection electrode penetrating the stack layer and electrically connected to the driving circuit, the driving circuit having a first driving pixel 110R, a second driving pixel 110G, and a third driving pixel 110B. The stacked layers include a first stacked layer 201, a first dielectric filling layer 213, a second stacked layer 202, a second dielectric filling layer 224, a third stacked layer 203 and a passivation layer 240 from bottom to top.
The first stacked layer 201 is provided with a metal bonding layer and a first epitaxial layer 211, and is bonded with the supporting substrate 102 through the metal bonding layer, and the metal bonding layer is located on a p-type surface of the first epitaxial layer 211; the first dielectric filling layer 213 is deposited on the upper surface of the first stack layer 201; the second stacked layer 202 has a first filter layer 220 and a second epitaxial layer 222, the first filter layer 220 is bonded to the first dielectric fill layer 213; the second dielectric fill layer 224 is deposited on the surface of the second stack 202; the third stacked layer 203 is provided with a third epitaxial layer 232 and a second filter layer 230, and the second filter layer 230 is bonded with the second medium filling layer 224; the interconnection electrode includes a first p-type electrode 311R, a second p-type electrode 311G, a third p-type electrode 311B, and a common electrode, the first p-type electrode 311R is electrically connected to the p-type surfaces of the first driving pixel 110R and the first epitaxial layer 211, the second p-type electrode 311G is electrically connected to the p-type surfaces of the second driving pixel 110G and the second epitaxial layer 222, the third p-type electrode 311B is electrically connected to the p-type surfaces of the third driving pixel 110B and the third epitaxial layer 232, and the common electrode is located at the periphery of the stacked layers and is provided with a first n-type contact electrode 312, a second n-type contact electrode 313, and a third n-type contact electrode 314 that are electrically connected to the n-type surface of the first epitaxial layer 211, the n-type surface of the second epitaxial layer 222, and the n-type surface of the third epitaxial layer 232, respectively; the passivation layer 240 is deposited on the upper surfaces of the third stack layer 203 and the interconnection electrodes.
Each driving circuit has three driving pixels, which may be divided into a first driving pixel 110R, a second driving pixel 110G, and a third driving pixel 110B corresponding to a red driving pixel, a green driving pixel, and a blue driving pixel, respectively. A plurality of driving circuits may be formed on the supporting substrate 102 to form a driving circuit array, which has an electrode array.
The driving pixels are used as individual pixel driving devices for driving one epitaxial layer in a light emitting pixel to emit light. For an array of drive circuits, each drive pixel has a contact and a ground contact (i.e., a common electrode), only the contacts of the drive pixel being shown in fig. 1. Each pixel has two sets of electrodes: one set of contact array electrodes is connected to three driving pixels, respectively, and the other set of contact electrodes is connected to ground (i.e., a common electrode).
The first stack layer 201 further comprises a first transparent conductive layer 212, wherein the first transparent conductive layer 212 is located on the n-type surface of the first epitaxial layer 211; the part of the metal bonding layer electrically connected with the first driving pixel 110R forms a first p-type electrode 311R; a first n-type contact electrode 312 electrically connected to the first transparent conductive layer 212; a first dielectric layer is deposited on the upper surface of the first n-type contact electrode 312.
The second stacked layer 202 further includes a second transparent conductive layer 221 and a third transparent conductive layer 223, the second transparent conductive layer 221 is deposited on the p-type surface of the second epitaxial layer 222 and the upper surface of the first filter layer 220, and the third transparent conductive layer 223 is deposited on the n-type surface of the second epitaxial layer 222; the second p-type electrode 311G penetrates through the first stacked layer 201 and the second stacked layer 202 and is electrically connected to the second transparent conductive layer 221; the second n-type contact electrode 313 is electrically connected to the third transparent conductive layer 223; a second dielectric layer is also deposited on the upper surface of the second n-type contact electrode 313.
The first filter layer 220 or the second filter layer 230 is a multilayer dielectric thin film and/or a dielectric micro-nano structure; the first filter layer 220 has a high reflectivity for light emitted from the second epitaxial layer 222 and a high transmittance for light emitted from the first epitaxial layer 211; or the second filter layer 230 has a high reflectivity for light emitted from the third epitaxial layer 232 and a high transmittance for light emitted from the first and second epitaxial layers 211 and 222.
The third stacked layer 203 further includes a fourth transparent conductive layer 231 and a fifth transparent conductive layer 233, the fourth transparent conductive layer 231 is deposited on the p-type surface of the third epitaxial layer 232 and the upper surface of the second filter layer 230, and the fifth transparent conductive layer 233 is deposited on the n-type surface of the third epitaxial layer 232; the third p-type electrode 311B penetrates through the third stacked layer 203, the second stacked layer 202 and the first stacked layer 201 and is electrically connected to the fourth transparent conductive layer 231; the third n-type contact electrode 314 is electrically connected to the fifth transparent conductive layer 233.
A passivation layer 240 is also arranged between the common electrode and the periphery of the stacked layer; a passivation layer 240 is also disposed between the second and third p- type electrodes 311G and 311B and the stacked layers, and the first p-type electrode 311R may be positioned between the second and third p- type electrodes 311G and 311B.
In practice, the support substrate 102 of the present invention is a silicon-based substrate, or may be a transparent substrate (e.g., a glass substrate). The material of the support substrate 102 may also be one of gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), silicon carbide (SiC), zinc oxide (ZnO), and sapphire substrates. The driving pixel may include a driver circuit other than the CMOS driver circuit, for example, a driver circuit including a Thin Film Transistor (TFT) driver circuit or a III-V compound semiconductor.
The first epitaxial layer 211, the second epitaxial layer 222, and the third epitaxial layer 232 include one of a group III-V nitride, a group III-V arsenide, a group III-V phosphide, and a group III-V antimonide, which is an LED epitaxial structure having a p-type layer, an active region light emitting layer, and an n-type layer. The selectable light-emitting wavelength ranges of the first epitaxial layer 211, the second epitaxial layer 222 and the third epitaxial layer 232 are 580-680 nm, 480-580 nm and 380-480 nm respectively, and can be red light, green light and blue light respectively.
In addition, the passivation layer 240 is made of SiO2、SiNx、Al2O3Or HfO2Any one of them. The interconnection electrode is made of any one or a plurality of composite materials of aluminum, silver, rhodium, zinc, gold, germanium, nickel, chromium, platinum, tin, copper, tungsten, palladium, indium or titanium.
The invention also provides a manufacturing method of the full-color active addressing Micro-LED chip structure, which is characterized by comprising the following steps of:
1) a first stacked layer 201 having a first epitaxial layer 211 and a metal bonding layer is fabricated, and a support substrate 102 having a driving circuit array is bonded to the first epitaxial layer 211 through the metal bonding layer.
Referring to fig. 4, specifically, a substrate metal bonding layer 210 is uniformly deposited on the upper surface of the supporting substrate 102. The first epitaxial layer 211 is grown on a separate epitaxial substrate. A continuous uniform epitaxial metal bonding layer 210R is deposited on the p-type surface of the first epitaxial layer 211. The epitaxial metal bonding layer 210R may include various combinations of an ohmic contact layer, a light reflecting layer, and a metal bonding layer. The substrate metal bonding layer 210 and the epitaxial metal bonding layer 210R are bonded together to constitute a metal bonding layer.
Since the first epitaxial layer 211 is unpatterned, bonding does not require fine alignment and can be accomplished using techniques such as eutectic bonding, thermal compression bonding, and Transient Liquid Phase (TLP) bonding. The epitaxial substrate is then removed by, for example, a laser lift-off process or wet chemical etching. After the epitaxial substrate is removed, a first transparent conductive layer 212 is deposited on the upper surface, i.e., the n-type surface, of the first epitaxial layer 211. The metal bonding layer 210, the red epitaxial layer 211 and the first transparent conductive layer 212 together constitute a first stacked layer 201.
2) Patterning the first stack layer 201 to form light emitting pixels each including a first driving pixel 110R, a second driving pixel 110G, and a third driving pixel 110B through a semiconductor manufacturing process; manufacturing a first p-type electrode 311R on the first stacked layer 201 to be electrically connected with the first driving pixel 110R and the p-type surface of the first epitaxial layer 211; a first n-type contact electrode 312 electrically connected to the n-type surface of the first epitaxial layer 211 is formed on the periphery of the first stacked layer 201.
Specifically, referring to fig. 5, in this step, the first stacked layer 201 is patterned to form light emitting pixels each including three driving pixels through photolithography and etching processes, wherein a first via hole 301G and a second via hole 301B are fabricated right above the second driving pixel 110G and the third driving pixel 110B to expose corresponding pixel drivers.
In this example, a first via 301G etched to expose the second drive pixel 110G is used to connect to the p-type surface of the second epitaxial layer 222, and a second via 301B etched to expose the third drive pixel 110B is used to connect to the p-type surface of the third epitaxial layer 232. The patterned metal bonding layer (including 210 and 210R) is electrically connected to the p-type surface of the first epitaxial layer 211, i.e., a first p-type electrode 311R, which serves as a p-type surface metal pad of the first epitaxial layer 211.
Referring to fig. 6, a passivation layer 240 is deposited on the sidewalls and the bottom of the outer periphery of the etched first stack layer 201, and the sidewalls of the first and second via holes 301G and 301B, and the passivation layer of the sidewalls may partially extend to the first transparent conductive layer 212.
Referring to fig. 7, the conductive material 310 is filled in the two light emitting pixel gaps, i.e., the periphery (including the sidewalls and the bottom) of the first stack layer 201, the first via hole 301G, and the second via hole 301B, respectively, and the conductive material 310 may be, for example, TiN, tungsten, or the like. The conductive material 310 located at the periphery of the first stacked layer 201 extends to the first transparent conductive layer 212 to constitute a first n-type contact electrode 312. The first n-type contact electrode 312 includes a portion of the conductive material 310 and the first transparent conductive layer 212 covering the light emitting pixel gap (the periphery of the first stacked layer 201) above the light emitting pixel gap.
3) Depositing a first dielectric filling layer 213 on the upper surface of the first stack layer 201 and the upper surface of the first n-type contact electrode 312; fabricating a second stacked layer 202 having a first filter layer 220 and a second epitaxial layer 222, and bonding the first filter layer 220 to the first dielectric fill layer 213; a second p-type electrode 311G is formed to be electrically connected to the second driving pixel 110G and the p-type surface of the second epitaxial layer 222, and a second n-type contact electrode 313 is formed at the periphery of the second stacked layer 202 to be electrically connected to the n-type surface of the second epitaxial layer 222.
Specifically, the first dielectric filling layer 213 is deposited on the upper surface of the conductive material 310 and the upper surface of the first transparent conductive layer 212 in step 2), and then the structure of fig. 8 is obtained by performing planarization through a chemical mechanical polishing technique after deposition.
The second stack 202 is made as follows:
the second epitaxial layer 222 is grown on a separate epitaxial substrate. A second transparent conductive layer 221 and a first filter layer 220 are sequentially deposited on the second epitaxial layer 222. The first dielectric fill layer 213 and the first filter layer 220 are bonded together. The green epitaxial layer 222 substrate is then removed by, for example, a laser lift-off process or wet chemical etching. After the epitaxial substrate is removed, a third transparent conductive layer 223 is deposited on the upper surface, i.e., the n-type surface, of the second epitaxial layer 222. The first filter layer 220, the second transparent conductive layer 221, the second epitaxial layer 222 and the third transparent conductive layer 223 together constitute a second stacked layer 202, see the structure shown in fig. 9.
The first filter layer 220 is characterized by a high transmittance (i.e., a lens) for photons in the red wavelength band and a high reflectance (i.e., a mirror) for photons in the green wavelength band. Therefore, photons generated by electroluminescence of the first epitaxial layer 211 upwards penetrate through the stacked layers and are emitted from the upper surface of the light-emitting pixel under the action of the antireflection mirror and the reflector of the metal bonding layer 210, photons generated by electroluminescence of the second epitaxial layer 222 cannot downwards penetrate through the first filter layer 220 under the action of the reflector and are absorbed by the first epitaxial layer 211, and the problem that color mixing is caused due to photoluminescence of the first epitaxial layer 211 under the excitation of green light, and display color saturation is affected is avoided. The first filter layer 220 may be a multi-layer dielectric film (e.g., an interference cut filter film), a dielectric micro-nano structure, and/or a combination thereof.
By aligning the photolithography and etching processes, the second stack layer 202 has the same patterned structure as the first stack layer 201, and a third via hole 302G and a fourth via hole 302B are respectively fabricated in the vertical direction of the first via hole 301G and the second via hole 301B, exposing corresponding portions of the conductive material 310 in step 2). Further, by aligning the photolithography and etching processes, the lateral dimension of the upper portion of the third via hole 302G is enlarged, and the portion of the second transparent conductive layer 221 located in the third via hole 302G is exposed, see fig. 11. Passivation layer 240 is then deposited on the peripheral sidewalls of second stacked layer 202, the sidewalls of third via hole 302G, and the sidewalls of fourth via hole 302B, and the passivation layer 240 on the peripheral sidewalls extends partially to third transparent conductive layer 223. The passivation layer 240 of the lower sidewall of the third via hole 302G partially extends to the second transparent conductive layer 221, and the passivation layer 240 of the upper sidewall partially extends to the third transparent conductive layer 223. The passivation layer 240 on the sidewall of the fourth via hole 302B partially extends to the third transparent conductive layer 223, as shown in fig. 12.
The light emitting pixel gap, the third through hole 302G, and the fourth through hole 302B are filled with a conductive material 310. Specifically, the conductive material 310 forms a p-type electrode contact with the exposed region of the second transparent conductive layer 221, which is the second p-type electrode 311G. The second n-type contact electrode 313 is a conductive material 310 at the periphery of the second stacked layer 202 and extends to a partial region near the outer side of the upper surface of the third transparent conductive layer 223, as shown in fig. 13.
4) Depositing a second dielectric filling layer 224 on the upper surface of the second stacked layer 202 and the upper surface of the second n-type contact electrode 313; manufacturing a third stacked layer 203 with a second filter layer 230 and a third epitaxial layer 232, and bonding the second filter layer 230 and the second medium filling layer 224; a third p-type electrode 311B is formed to be electrically connected to the third driving pixel 110B and the p-type surface of the third epitaxial layer 232, and a third n-type contact electrode 314 is formed on the periphery of the third stacked layer 203 to be electrically connected to the n-type surface of the third epitaxial layer 232.
Specifically, the second dielectric filling layer 224 is deposited on the surface of the conductive material 310 in the second stacked layer 202 and step 3), and the deposited second dielectric filling layer may be planarized by a chemical mechanical polishing technique, so as to obtain the structure of fig. 14. The third stack 203 is made as follows:
the third epitaxial layer 232 is grown on a single epitaxial substrate, and a continuous and uniform fourth transparent conductive layer 231 and the second filter layer 230 are sequentially deposited on the p-type surface of the third epitaxial layer 232. Bonding the second dielectric fill layer 224 and the second filter layer 230 together. The blue epitaxial layer 232 substrate is then removed by, for example, a laser lift-off process or wet chemical etching.
After the epitaxial substrate is removed, a fifth transparent conductive layer 233 is deposited on the upper surface, i.e., the n-type surface, of the third epitaxial layer 232. The second filter layer 230, the fourth transparent conductive layer 231, the third epitaxial layer 232, and the fifth transparent conductive layer 233 collectively constitute a third stacked layer 203, see the structure shown in fig. 15.
The second filter layer 230 is characterized by high transmittance (i.e., a lens) for photons in the red and green wavelength bands and high reflectance (i.e., a mirror) for photons in the blue wavelength band. Therefore, photons generated by electroluminescence of the first epitaxial layer 211 and the second epitaxial layer 222 pass through the stacked layer upward and exit from the upper surface of the light-emitting pixel under the action of the antireflection mirror, the reflector of the metal bonding layer, and the reflector of the first filter layer 220, and photons generated by electroluminescence of the third epitaxial layer 232 cannot be absorbed by the stacked layer under the action of the reflector of the second filter layer 230. The second filter layer 230 may include, for example, a multi-layer dielectric film (e.g., an interference cut filter film), a dielectric micro-nano structure, and/or combinations thereof.
Through aligning the photolithography and etching processes, the third stacked layer 203 has the same patterned structure as the second stacked layer 202, that is, the through holes 303G and 303B are respectively fabricated in the vertical direction of the third through hole 302G and the fourth through hole 302B, exposing the conductive material 310 filled in step 3).
Further, by aligning the photolithography and etching processes, the lateral dimension of the upper portion of the sixth via 303B is enlarged, so that a portion of the fourth transparent conductive layer 231 is exposed in the sixth via 303B, as shown in fig. 16. A passivation layer 240 is then deposited in the fifth via 303G, on the sidewalls of the sixth via 303B, and on the periphery of the third stacked layer 203, as in the structure shown in fig. 17.
When the conductive material 310 is filled in the periphery of the third stacked layer 203, i.e., the pixel gap and the sixth via 303B, the conductive material 310 in the sixth via 303B and the exposed region of the fourth transparent conductive layer 231 form a p-type electrode contact, i.e., a third p-type electrode 311B. The conductive material 310 covering the light emitting pixel gap and a partial region extending to the upper surface of the fifth transparent conductive layer 233 near the light emitting pixel gap constitute a third n-type contact electrode 314, as shown in fig. 18.
5) The first n-type contact electrode 312, the second n-type contact electrode 313, and the third n-type contact electrode 314 are electrically connected to form a common electrode. The common electrode and the first, second and third p- type electrodes 311R, 311G and 311B serve as interconnection electrodes, and a passivation layer 240 is deposited on the upper surfaces of the third stacked layer 203 and the interconnection electrodes.
In the invention, the common electrode 314 is distributed in a gridding manner in the gaps around each light-emitting pixel, and the width of the common electrode 314 is smaller than the distance between the light-emitting pixels; the positions of the first p-type electrode 311R, the second p-type electrode 311G, the third p-type electrode 311B, the first n-type contact electrode 312, the second n-type contact electrode 313 and the fourth n-type contact electrode 314 are uniformly distributed on the central axis of the light emitting pixel, and are insulated and protected by the passivation layer 240 to prevent the occurrence of a chip short circuit, see fig. 3.
The above description is only an embodiment of the present invention, but the design concept of the present invention is not limited thereto, and any insubstantial modifications made by using the design concept should fall within the scope of infringing the present invention.
Claims (10)
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| WO2025091231A1 (en) * | 2023-10-31 | 2025-05-08 | Jade Bird Display (shanghai) Limited | Micro-led array layer and micro-led display panel |
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