CN112117263A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The disclosed embodiments relate to a semiconductor structure and a method for manufacturing the same. A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is located above the first semiconductor die and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die by bonding the second active surface to the first back surface at a first hybrid bonding interface in a vertical direction. In a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.

Description

Semiconductor structure and method of making the same

technical field

Embodiments of the present disclosure relate to a semiconductor structure and a fabrication method thereof.

Background technique

In recent years, the semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density comes from the continuous reduction in minimum feature size, which enables more components to be integrated into a given area. For example, integrated components occupy an area close to the surface of a semiconductor wafer; however, there is a physical limit to the density that can be achieved in two-dimensional (2D) integrated circuit formation. For example, one of these limitations arises from the dramatic increase in the number and length of interconnects between semiconductor devices as the number of semiconductor devices increases. As existing integrated circuit design rules require reducing the pitch of conductive wiring layouts in semiconductor structures, there is an ongoing effort to develop new mechanisms for forming semiconductor structures.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a semiconductor structure including a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite the first active surface. The second semiconductor die is located over the first semiconductor die and includes a second semiconductor substrate having a second active surface and a second back surface opposite the second active surface. The second semiconductor die is bonded to the first semiconductor die by bonding the second active surface to the first back surface at a first hybrid bonding interface in a vertical direction. In the lateral direction, the first dimension of the first semiconductor die is larger than the second dimension of the second semiconductor die.

Description of drawings

Aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. Note that in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1-4 are schematic cross-sectional views illustrating various stages in a semiconductor die fabrication method according to some embodiments of the present disclosure.

5-24 are schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

25 is a schematic top view illustrating the relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure.

26A is an enlarged schematic cross-sectional view illustrating the bonding interface between the semiconductor die in the dashed region A outlined in FIG. 11 and the carrier die underlying the semiconductor die, according to some embodiments of the present disclosure .

26B is an enlarged schematic cross-sectional view illustrating a bonding interface between a semiconductor die and a carrier die underlying the semiconductor die in accordance with some embodiments of the present disclosure.

27A is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of the die stack in the dashed region B outlined in FIG. 17, according to some embodiments of the present disclosure.

27B is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of a die stack in accordance with some embodiments of the present disclosure.

28A is an enlarged schematic cross-sectional view illustrating the bonding interface between adjacent levels of the die stack in the dashed region C outlined in FIG. 19, according to some embodiments of the present disclosure.

28B is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of a die stack in accordance with some embodiments of the present disclosure.

28C is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of a die stack in accordance with some embodiments of the present disclosure.

29A is an enlarged schematic cross-sectional view illustrating the configuration of the outermost level of the die stack in the dashed region D outlined in FIG. 19, according to some embodiments of the present disclosure.

29B is an enlarged schematic cross-sectional view illustrating the configuration of the outermost level of the die stack in accordance with some embodiments of the present disclosure.

30 to 44 are schematic cross-sectional views respectively illustrating semiconductor structures according to some embodiments of the present disclosure.

45 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

46A and 46B are schematic top views, respectively, illustrating the relative positions among a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure.

47 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure.

48A and 48B are schematic top views, respectively, illustrating the relative positions among a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure.

49-56 are schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

57 is a schematic top view illustrating the relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure.

58 is a schematic cross-sectional view illustrating the application of a semiconductor structure according to some embodiments of the present disclosure.

[Explanation of symbols]

10A, 10A', 10A", 10B': semiconductor die

10A"', 10B": Thinned semiconductor die

10A(1): Tier 1/Internal Tier

10A(2): Second Tier/Internal Tier

10A(T): the topmost level

10A(T-1): Tier (T-1)/Internal Tier

10B: Carrier Die/Semiconductor Die

10B(0): Basic level

20, 40: Insulation envelope

20': Insulation material

20a, 20b, S60: Surface

20S, 40S, 60S, 70S, 100S, 110s, 130s, 130SW, 150SW, 230s, 230SW, S5: Sidewalls

30: Conductive terminal

31: bump

32: Metal top cover

50, 51, 160, 240: isolation layer

50(0), 50(1), 50(T-1): isolation structure

50a, 51a: first lateral portion

50b, 51b: second lateral portion

50c, 51c: Connection part

50c', 51c': flattened connection portion

60: EMI shielding layer

60A: EMI shielding material

70: Protective layer

100: Die stacking

100b, 110b, 110b', 110b", 110b"', 130b, 160b, 210b, 210b', 210b", 230b, 240b: Bottom surface

110, 210: Semiconductor substrate

120, 220: Internal wiring structure

130, 230: Via hole

140, DI1, DI2, DI3, DI4: Dielectric layer

150: Bonded conductors

150a: Bond pads

150b: Bonding Through Holes

A, B, C, D: dotted area/dotted box

AP: Conductive pad

BE: Beveled edge

BS: Dorsal

C1: first component

C2: Second component

CT: Terminal

D1, D2: depth

FS: Front side

I-I, II-II, III-III, IV-IV: Cross Section Lines

IF1, IF2: bonding interface

MP: Metallized Pattern

OP: open mouth

P1a, P1b, P1c, P1d, P2a, P2b, P2c, P2d, P3a, P3b, P3c, P3d, P4a, P4b, P4c, P4d, P5, P6, P7: Semiconductor structure

PL: Passivation layer

R1, R2: Sag

RE: rounded edges

S1, S3: Front surface

S2, S4: back surface

SC: Component assembly

SE: sharp edge

SS1, SS2: Stacked structure

T1, T2, T3, T4, T5, T6, T10A, T10B, T50, T51, T60: Thickness

TB1, TB2, TB3, TB4: Temporary bonding layers

TC1, TC2, TC3, TC4: Temporary carriers

TP1: Tape Frame

UF: Primer layer

W1, W2, W2': semiconductor wafers

W1': Thinned semiconductor wafer

W10B, W100: Width

X, Y: direction

Z: stacking direction

Detailed ways

The following disclosure provides many different embodiments or examples for implementing various features of the presented subject matter. Specific examples of components, values, operations, materials, arrangements or similar elements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, arrangements or similar elements are contemplated. For example, reference in the following description to forming a first feature "on" or "on" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include Embodiments wherein additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may reuse reference numbers and/or letters in various instances. This re-use is for the purpose of brevity and clarity and is not itself indicative of the relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, for example, "beneath", "below", "lower", "above", "upper" may be used herein. (upper)" and similar terms to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Additionally, for ease of description, terms such as "first," "second," "third," and similar terms may be used herein to describe similar or different ones shown in the figures elements or features, and may be used interchangeably depending on the order in which they are presented or the context in which they are described.

Some embodiments of the present disclosure may also include other features and processes. For example, test structures may be included to facilitate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. The test structures may include, for example, test pads formed in redistribution layers or on the substrate to enable testing of 3D packages or 3DICs, use of probes and/or probecards, and the like operate. Verification tests can be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein can be used in conjunction with test methods that include intermediate verification of known good dies (KGDs) to improve yield and reduce cost.

1-4 are schematic cross-sectional views illustrating various stages in a semiconductor die fabrication method according to some embodiments of the present disclosure. Referring to FIG. 1 , in some embodiments, a semiconductor wafer W1 is provided. In some embodiments, semiconductor wafer W1 includes a plurality of semiconductor dies 10A' connected to each other. For example, each of the semiconductor dies 10A' may include an integrated circuit device (eg, a logic die, a memory die, a radio frequency die, a power management die, a micro-electro-mechanical-system , MEMS) die, similar devices, or a combination of these). In some embodiments, the thickness T1 of the semiconductor wafer W1 is in the range of about 720 micrometers (μm) to about 800 μm.

For example, each of the semiconductor dies 10A' includes a semiconductor substrate 110, interconnect structures 120, a plurality of vias 130, a dielectric layer 140, and a plurality of bonding conductors 150 formed in the semiconductor substrate 110 There are a plurality of semiconductor devices (not shown), the interconnect structure 120 is formed on the semiconductor substrate 110, the plurality of vias 130 are formed in the semiconductor substrate 110 and extend into the interconnect structure 120, through the An electrical layer 140 is formed on the interconnect structure 120 opposite the semiconductor substrate 110 , and the plurality of bonding conductors 150 are formed on the interconnect structure 120 and are laterally covered by the dielectric layer 140 . In some embodiments, as shown in FIG. 1 , each of the semiconductor dies 10A' has a front surface S1 and a bottom surface 110b' opposite the front surface S1. The bonding conductors 150 are distributed at the front surface S1 and are exposed in an accessible manner by the dielectric layer 140, and the bottom surface 110b' can be regarded as a side away from the interconnect structure 120 and the bonding conductors 150.

In some embodiments, the semiconductor substrate 110 includes a bulk semiconductor, which may be doped or undoped, a semiconductor-on-insulator (SOI) substrate, other supporting substrates (eg, quartz, glass, etc.), combinations thereof, or the like. In some embodiments, the semiconductor substrate 110 includes elemental semiconductors (eg, silicon or germanium in crystalline, polycrystalline, or amorphous structures, etc.), compound semiconductors (eg, silicon carbide, gallium arsenide, gallium phosphide, phosphide, etc.) Indium, indium arsenide and/or indium antimonide, etc.), alloy semiconductors (for example, silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (aluminum indium arsenide, AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multi-layer structure, or the substrate may include a multi-layer compound semiconductor structure. In some embodiments, alloyed SiGe is formed over a silicon substrate. In other embodiments, the SiGe substrate is strain gauged. The semiconductor substrate 110 may include a plurality of semiconductor devices (not shown) formed therein or thereon, and the semiconductor devices may be or may include active devices (eg, transistors, diodes, etc.) and/or passive devices (eg, , capacitors, resistors, inductors, etc.) or other suitable electrical components. In some embodiments, the semiconductor device is formed at a side of the semiconductor substrate 110 proximate the interconnect structure 120 .

The semiconductor substrate 110 may include circuitry (not shown) formed in a front-end-of-line (FEOL) process, and the interconnect structure 120 may be formed in a back-end-of-line (FEOL) process. line, BEOL). In some embodiments, the interconnect structure 120 includes an inter-layer dielectric (ILD) layer formed over the semiconductor substrate 110 and covering the semiconductor device and an inter-metal dielectric layer formed over the ILD layer (inter-metallization dielectric, IMD) layer. In some embodiments, the ILD layer and the IMD layer are made of, for example, oxide, silicon dioxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), fluorinated silicate Low dielectric constant (low-K) dielectric materials such as fluorinated silicate glass (FSG), SiOxCy, spin-on glass, spin-on polymers, silicon carbon materials, compounds thereof, composites thereof, combinations thereof, or the like or Very low dielectric constant (extreme low-K, ELK) material formation. The ILD layer and the IMD layer may include, without limitation, any suitable number of layers of dielectric material.

In some embodiments, an interconnect structure 120 is formed on the semiconductor substrate 110, and the interconnect structure 120 includes one or more dielectric layers (eg, dielectric layer DI1 shown in FIG. 26A ) and one or more A metallization pattern (eg, metallization pattern MP shown in FIG. 26A ). Metallization patterns can be embedded in dielectric layers (eg, IMD layers), and metallization patterns (eg, metal lines, metal vias, metal pads, metal traces, etc.) can be made of, eg, copper, gold, aluminum, the like, or the like Combination and other conductive materials are formed. In some embodiments, the interconnect structures 120 are electrically coupled to each other to semiconductor devices formed in and/or on the semiconductor substrate 110 and to external components (eg, a plurality of test pads, a plurality of bonding conductors, etc.). For example, metallization patterns in the dielectric layer route electrical signals between the semiconductor devices of the semiconductor substrate 110 . Semiconductor devices are interconnected with metallization patterns to perform one or more functions including memory structures (eg, memory cells), processing structures, input/output circuitry, or the like. The outermost layer of interconnect structure 120 may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics, polyimide, combinations of these, or the like (eg, the passivation layer PL shown in FIG. 26A ). In some embodiments, each of the semiconductor dies 10A' includes a conductive pad disposed over and electrically coupled to the top metallization pattern of the interconnect structure 120 (eg, as shown in FIG. 26A ) Conductive pads AP), and the passivation layer of the interconnect structure 120 may have openings that expose at least part of the conductive pads for testing or for further electrical connections.

In some embodiments, vias 130 are formed to extend into semiconductor substrate 110 . The vias 130 can be in physical and electrical contact with the metallization pattern of the interconnect structure 120 . For example, when the via hole 130 is initially formed, the via hole 130 is embedded in the semiconductor substrate 110 and may not extend to the bottom surface 110b' of the semiconductor substrate 110. That is, for the semiconductor wafer W1, the via holes 130 are not exposed by the semiconductor substrate 110 in an accessible manner.

For example, each of the vias 130 may include a barrier material (eg, TiN, Ta, TaN, Ti, or the like; not shown) and a conductive material (eg, copper, tungsten, aluminum, silver, etc.) combination or the like; not shown). For example, barrier material may be formed between the conductive material and the semiconductor substrate 110 .

In alternate embodiments, a dielectric liner (not shown) (eg, silicon nitride, oxide, polymer, other combination, etc.). In some embodiments, vias 130 are formed by forming recesses in semiconductor substrate 110 and depositing a dielectric liner, barrier material, and conductive material in the recesses, respectively, removing excess on semiconductor substrate 110 . Material. For example, the plurality of recesses of the semiconductor substrate 110 are lined with dielectric liners to laterally separate the semiconductor substrate 110 and the vias 130 . The vias 130 may be formed by using a via-first approach. For example, the via 130 is formed during the formation of the interconnect structure 120 . Alternatively, the via hole 130 may be formed using a via-last method, and may be formed after the interconnection structure 120 is formed. The present disclosure is not limited thereto.

In some embodiments, a dielectric layer 140 is formed on the interconnect structure 120 . For example, the dielectric layer 140 includes a dielectric material (eg, silicon nitride, silicon oxide, high-density plasma (HDP) oxide, tetra-ethyl-orthosilicate (tetra-ethyl-orthosilicate) ortho-silicate, TEOS), undoped silicate glass (USG), the like, or a combination thereof) formed of one or more layers (eg, the dielectric layers DI2, DI3, DI4). In some embodiments, the bonding is then performed using a dielectric layer 140 laterally covering the bonding conductors 150 . It should be understood that depending on process requirements, the dielectric layer 140 may include a layer of etch stop material (not shown) sandwiched between the layers of dielectric material. For example, the etch stop material layer is different from the overlying or underlying dielectric material layer. The layer of etch stop material may be formed of a material having a high etch selectivity relative to an overlying or underlying layer of dielectric material for terminating etching of the layer of dielectric material. The structure of the dielectric layer 140 will be described in detail later with reference to the drawings.

In some embodiments, multiple bond vias (eg, bond vias 150b shown in FIG. 26A ) and/or multiple bond pads (eg, FIG. 26A ) are formed over the interconnect structure 120 , for example. Bond conductors 150 such as bond pads 150a) shown in to provide external electrical connection to the circuitry and semiconductor device. In the present disclosure, the bonding conductors 150 each have bonding pads with two or more bonding vias disposed thereon. Bond conductors 150 may be formed of conductive materials such as copper, gold, aluminum, the like, or combinations thereof. Bond conductors 150 may be electrically coupled to semiconductor devices of semiconductor substrate 110 through interconnect structure 120 . Bond conductors 150 may be substantially flush with dielectric layer 140 for bonding. The above examples are provided for illustrative purposes, other embodiments may utilize fewer or additional elements (eg, conductive pads), and details of the semiconductor die will be explained later in conjunction with enlarged views. In other words, for example, it can also be said that the semiconductor wafer W1 includes a semiconductor substrate 110 , interconnect structures 120 , vias 130 , dielectric layers 140 , and bonding conductors 150 , as shown in FIG. 1 .

2, in some embodiments, semiconductor wafer W1 is placed on temporary carrier TC1 through temporary bonding layer TB1. The material of the temporary carrier TC1 may include glass, metal, ceramic, silicon, plastic, combinations thereof, multiple layers thereof, or other suitable materials that may provide structural support for the semiconductor wafer W1 during subsequent processing. In some embodiments, the temporary carrier TC1 is made of glass, and the temporary bonding layer TB1 used to bond the semiconductor wafer W1 to the temporary carrier TC1 includes a polymer adhesive layer (eg, a die attach film). film, DAF)), such as light-to-heat conversion (LTHC) release coatings, ultra-violet (UV) glues, etc., degrade when exposed to radiation sources (eg, UV light or lasers) Or an ultraviolet (UV) cured layer that loses its adhesive properties. Other suitable temporary adhesives may be used. In some embodiments, the temporary carrier TC1 is a silicon wafer, and the temporary bonding layer TB1 includes a silicon-containing dielectric material (eg, silicon oxide, silicon nitride, etc.) or other suitable dielectric material for bonding. For example, the bonding includes oxide-to-oxide bonding, and the dielectric layer 140 of the semiconductor wafer W1 is bonded to the temporary bonding layer TB1. Alternatively, the temporary bonding layer TB1 may be omitted.

In some embodiments, as shown in FIG. 2 , the front side FS of the semiconductor wafer W1 (eg, the front surface S1 of the semiconductor die 10A′) is bonded to the temporary carrier TC1 , and the back side BS ( For example, the bottom surface 110b') of the semiconductor die 10A' faces up for subsequent processing. For example, the front side FS is opposite to the back side BS along the stacking direction Z of the semiconductor substrate 110 and the interconnect structure 120 .

2 and 3 , in some embodiments, the semiconductor wafer W1 is thinned to form a thinning process such as etching, grinding, chemical mechanical polishing (CMP), combinations thereof, or other suitable thinning techniques. Thinned semiconductor wafer W1'. For example, a thinning process is performed on the backside BS of the semiconductor wafer W1 (eg, the bottom surface 110b' of the semiconductor die 10A') to obtain a thinned semiconductor wafer W1' having a reduced thickness T2 . That is, the reduced thickness T2 of the thinned semiconductor wafer W1' is smaller than the thickness T1 of the semiconductor wafer W1. In some embodiments, the reduced thickness T2 ranges from about 40 μm to about 200 μm. As shown in FIG. 3, after the thinning process, the vias 130 have not yet become accessible through the backside BS of the thinned semiconductor wafer W1' (eg, the bottom surface 110b" of the semiconductor die 10A"). revealed. In other words, for each semiconductor die 10A", the bottom surface 130b of the via 130 is not exposed in an accessible manner by the bottom surface 110b" of the semiconductor die 10A".

4, in some embodiments, after the wafer backside thinning process, the thinned semiconductor wafer W1' is mounted on the tape frame TP1. For example, the structure shown in FIG. 3 is turned upside down (eg, upside-down in the stacking direction Z) such that the backside BS of the thinned semiconductor wafer W1 ′ (eg, the semiconductor substrate of the semiconductor die 10A″ 110) bottom surface 110b") is provided on the tape frame TP1. Next, a de-bonding process may be performed on the temporary carrier TC1 to release from the thinned semiconductor wafer W1'. For example, external energy (eg, UV light or laser) is applied on the temporary bonding layer TB1. Alternatively, the removal process of the temporary carrier TC1 may include a mechanical peeling process, a grinding process, an etching process, or the like. In some embodiments, a cleaning process is performed using a suitable solvent, cleaning chemical, or other cleaning technique to remove residues of the temporary bonding layer TB1 from the thinned semiconductor wafer W1'. Subsequently, a singulation process is performed on the thinned semiconductor wafer W1 ′ to obtain a plurality of separated individual semiconductor dies 10A″. As shown in FIG. 4 , for example, the separation The respective semiconductor dies 10A" of each have a front surface S1 and a bottom surface 110b".

For example, during the singulation process, tape frame TP1 holds thinned semiconductor wafer W1' in place, and can be cut along scribe lines (not shown) using a dicing tool (eg, a saw) The thinned semiconductor wafer W1' is passed through. In other embodiments, the singulation process is performed prior to mounting on the tape frame TP1. In some embodiments, the function and performance of the semiconductor die 10A" included in the thinned semiconductor wafer W1' is tested by probing prior to dicing/singulation, and the Only known good dies (KGD) were selected from core 10A" and used for subsequent processing.

In some embodiments, the temporary carrier TC1 shown in FIGS. 2 and 3 may be replaced by a tape frame TP1. For example, the semiconductor wafer W1 is mounted on the first tape frame with the front side FS of the semiconductor wafer W1 facing the first tape frame, and then a thinning process is performed on the back side BS of the semiconductor wafer W1. Subsequently, the thinned semiconductor wafer W1' is transferred for mounting on the second tape frame with the backside BS of the thinned semiconductor wafer W1' (eg, the bottom surface 110b" of the semiconductor die 10A") facing the second tape frame Two tape frames, and then a singulation process is performed, and the second tape frame holds the thinned semiconductor wafer W1' in place during the singulation process. It should be noted that the above examples are provided for illustrative purposes and that the formation of semiconductor die 10A" may be formed in any logical order not limited by this disclosure.

FIGS. 5-24 are schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure, and are taken along the cross-sectional line I-I depicted in FIG. 25 . 25 is a schematic top view illustrating the relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure. 26A is an enlarged schematic cross-sectional view illustrating the bonding interface between the semiconductor die in the dashed region A outlined in FIG. 11 and the carrier die underlying the semiconductor die, according to some embodiments of the present disclosure . 27A is an enlarged schematic cross-sectional view illustrating a bonding interface between adjacent levels of the die stack in the dashed region B outlined in FIG. 17, according to some embodiments of the present disclosure. 28A is an enlarged schematic cross-sectional view illustrating the bonding interface between adjacent levels of the die stack in the dashed region C outlined in FIG. 19, according to some embodiments of the present disclosure. 29A is an enlarged schematic cross-sectional view illustrating the configuration of the outermost level of the die stack in the dashed region D outlined in FIG. 19, according to some embodiments of the present disclosure. Methods of fabricating semiconductor structures include bonding a die stack (e.g., 100) to a carrier die (e.g., 10B), wherein forming the die stack involves a plurality of stacked semiconductor dies (e.g., 10A and 10A'). For ease of understanding, the same elements are designated by the same reference numerals, and for the sake of brevity, they will not be repeated here.

5, in some embodiments, at least one semiconductor die 10B' is provided. For example, a semiconductor wafer (not shown) is processed in the manner described in FIGS. 1-4 to produce a respective plurality of semiconductor dies 10B', and therefore for simplicity, no reference to the semiconductor The formation of the die 10B' is described in detail. Each of the semiconductor dies 10B' may include structures similar to those of the semiconductor die 10A". For example, each of the semiconductor dies 10B' has a front surface S3 and a bottom surface 210b' opposite the front surface S3, and includes A semiconductor substrate 210 , an interconnect structure 220 and a plurality of via holes 230 , a plurality of semiconductor devices are formed in the semiconductor substrate 210 , and the interconnect structure 220 is formed on the semiconductor substrate 210 and includes a structure close to the front surface S3 The vias 230 are formed in the semiconductor substrate 210 and extend into the dielectric layers of the interconnect structure 220 to be in physical contact with the metallization patterns of the interconnect structure 220 and electrical contacts. The vias 230 of each of the semiconductor dies 10B′ may be electrically coupled to the metallization patterns of the semiconductor devices and interconnect structures 220 .

For illustrative purposes, only two semiconductor dies 10B' are shown in FIG. 5; however, the number of semiconductor dies 10B' is not limited to the present disclosure. Based on the design layout and requirements, the number of semiconductor die 10B' may be one or more than one.

It should be noted that various layers and features of each of semiconductor die 10B' are omitted from the figures. For example, the interconnect structure 220 includes a passivation layer (not shown) formed over the top metallization pattern of the interconnect structure 220 to provide a degree of protection to the underlying structures. The passivation layer may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics, polyimide, combinations of these, or the like. At this time, the conductive pad can be protected by covering the conductive pad with a passivation layer.

It is understood that semiconductor dies diced from different semiconductor wafers may have different properties and functions. In some embodiments, semiconductor die 10B' and semiconductor die 10A" are singulated from different semiconductor wafers, which may differ in function and properties. For example, the semiconductor die depicted in FIG. 5 Die 10B' is a logic die (eg, system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), etc.). Another In one aspect, the semiconductor die 10A" illustrated in FIG. 4 is, for example, a memory die (eg, dynamic random access memory (DRAM) die, static random access memory (SRAM) Die, synchronous dynamic random access memory (synchronous dynamic random access memory, SDRAM), NAND flash memory, etc.). As shown in FIG. 5, for example, two semiconductor dies 10B' are shown for illustration purposes; however, the number of semiconductor dies 10B' is not limited to the number depicted in this disclosure and can be based on requirements and Design layouts to select and specify.

Referring to Figures 6 and 7, in some embodiments, semiconductor die 10B' is disposed on temporary carrier TC2 through temporary bonding layer TB2. For example, a semiconductor wafer including semiconductor die 10B' is probed and tested prior to singulation. After the singulation process is performed, only known good semiconductor dies 10B' are picked and placed on the temporary carrier TC2. In some embodiments, a temporary bonding layer TB2 is deposited on the temporary carrier TC2, and the front surface S3 of each of the semiconductor dies 10B' is bonded to the temporary carrier TC2 through the temporary bonding layer TB2. In alternative embodiments, the temporary bonding layer TB2 may be omitted. The formation and/or materials of the temporary bonding layer TB2 and the temporary carrier TC2 are similar to the formation and/or materials of the temporary bonding layer TB1 and the temporary carrier TC1 depicted in FIG. 2 , and thus will not be repeated herein. As shown in FIG. 6, for example, the bottom surface 210b' of semiconductor die 10B' faces upward for subsequent processing.

Thereafter, for each of the semiconductor dies 10B', a thinning process (eg, etching, grinding, CMP process, or the like) is performed on the bottom surface 210b' of the semiconductor substrate 210 until the vias 230 are closed The bottom surface 210b" of the semiconductor substrate 210 is exposed so as to form the thinned semiconductor die 10B". For example, after attaching semiconductor die 10B' to temporary bonding layer TB2, semiconductor die 10B' is thinned to form thinned semiconductor die 10B", thinned semiconductor die 10B" Each has a thickness T3 ranging approximately from 5 μm to 100 μm. In some embodiments, thickness T3 is less than thickness T2. As shown in FIG. 7, in some embodiments, in each of the thinned semiconductor dies 10B", the bottom surface 230b of the via hole 230 is protected by the bottom surface 210b" of the semiconductor substrate 210 to be able to The way to touch is exposed. For example, in each thinned semiconductor die 10B", the bottom surface 230b of the via 230 and the bottom surface 210b" of the semiconductor substrate 210 are substantially flush and coplanar. In each of the thinned semiconductor dies 10B", when the semiconductor substrate 210 is a silicon substrate, the vias 230 that penetrate the semiconductor substrate 210 are referred to as semiconductor vias (TSVs) or TSV.

8, in some embodiments, the thinned semiconductor die 10B" is recessed such that the vias 230 protrude from the semiconductor substrate 210. In other words, the thinned semiconductor die is partially removed 10B" of the semiconductor substrate 210 to obtain a bottom surface 210b, and portions of each of the vias 230 protrude from the bottom surface 210b of the semiconductor substrate 210. After the recesses, in the cross section shown in FIG. 8 , a plurality of recesses R1 are formed, wherein each of the recesses R1 is formed on the bottom surface 210b and between the protruding portions of the two adjacent via holes 230 between. For example, the recesses R1 each have a depth D1 (as measured along the stacking direction Z) ranging approximately from 0.5 μm to 1.5 μm.

During the recessing process, the semiconductor substrate 210 of each of the thinned semiconductor dies 10B" may be partially removed by etching. For example, the material relative to the vias 230 and the temporary bonding layer For the material of TB2, the etching process has high etch-rate selectivity to the material of the semiconductor substrate 210. For example, the amount of removal of the semiconductor substrate 210 can be controlled by adjusting the etching time. In some embodiments, the vias 230 and the temporary bonding layer TB2 may remain intact during recessing. The etching process may include dry etching, wet etching, or a combination thereof. In some embodiments, using suitable solvents, cleaning chemistries A cleaning process is performed to remove residues from the etch process using a product or other cleaning technique.

9, in some embodiments, an isolation layer 50 is formed over the temporary carrier TC2 and on the thinned semiconductor die 10B". In some embodiments, the isolation layer 50 includes a first lateral portion 50a, a Two lateral portions 50b and connecting portion 50c. For example, as shown in Figure 9, the first lateral portion 50a is disposed on and extends over the temporary bonding layer TB2, and the second lateral portion 50b disposed on the bottom surface 210b of the semiconductor substrate 210 and the bottom surface 230b and sidewalls 230s of the via hole 230 and extending over the bottom surface 210b of the semiconductor substrate 210 and the bottom surface 230b and the sidewall 230s of the via hole 230 , and the connecting portion 50c is disposed on the first lateral portion 50a and extends into contact with the second lateral portion 50b. In some embodiments, the isolation layer 50 has a thickness T50 ranging approximately from 0.5 μm to 1.6 μm, wherein Thickness T50 is measured as the minimum distance between opposite sides of isolation layer 50. As shown in Figure 9, second lateral portion 50b fills recess R1. In one embodiment, thickness T50 is greater than depth D1, however this The disclosure is not limited thereto. In an alternative embodiment, the thickness T50 is substantially equal to the depth D1. In other words, the isolation layer 50 is thick enough to cover the protruding portion of the via hole 230 .

In some embodiments, the first lateral portion 50a and the second lateral portion 50b extend laterally, eg, along the direction X and/or the direction Y shown in FIG. 9 . For example, direction X is different from direction Y, and direction X and direction Y are independently perpendicular to stacking direction Z. In some embodiments, the connecting portion 50c extends vertically to connect the first lateral portion 50a and the second lateral portion 50b. For example, the connecting portion 50c may extend upward in a straight line as shown in FIG. 9 . However, the connecting portion 50c may extend upward in a stepped fashion (eg, connecting portion 51c in FIG. 15).

In some embodiments, the isolation layer 50 may be conformally formed over the temporary carrier TC2 by, for example, spin coating, a chemical vapor deposition (CVD) process, or the like. In some embodiments, the material of the isolation layer 50 may include a nitride (eg, silicon nitride), an oxide (eg, silicon oxide), or the like (eg, silicon oxynitride, silicon carbide, polymers, the like). Alternatively, a native oxide may be formed on the bottom surface 210b of the semiconductor substrate 210 of each of the thinned semiconductor dies 10B" prior to forming the isolation layer 50. As shown in FIG. 9 For example, the portion of the via hole 230 protruding from the bottom surface 210b of the semiconductor substrate 210 is surrounded by the second lateral portion 50b of the isolation layer 50 .

Referring to FIGS. 9 and 10 together, in some embodiments, isolation layer 50 is partially removed to expose vias 230 . In such an embodiment, the isolation layer 50 is patterned by a planarization process, wherein one first lateral portion 50a and a planarized connecting portion 50c' connected to the one first lateral portion 50a are formed together One isolation structure 50( 0 ), and the second lateral portion 50b of the isolation layer 50 is planarized to form the isolation layer 240 disposed on the bottom surface 210b. The planarization process may include, for example, a CMP process or the like. So far, the carrier die 10B is fabricated. In some embodiments, the thicknesses T10B of the carrier dies 10B each range approximately from 3 μm to 90 μm. In some embodiments, thickness T10B is less than or substantially equal to thickness T3. In this disclosure, in semiconductor structure P1a, carrier dies 10B are each referred to as a base level 10B( 0 ) of a die stack. It should be noted that various layers and features of the semiconductor die are omitted from the figures, and that the carrier die 10B may include more elements formed therein to perform different functions.

In some embodiments, for each carrier die 10B as shown in FIG. 10, isolation layer 240 exposes vias 230 in an accessible manner for further electrical connection. In some embodiments, the thickness T4 of the isolation layer 240 of the carrier die 10B ranges from approximately 0.3 μm to 1 μm. After the planarization process, for example, a cleaning process may optionally be performed to clean and remove residues generated by the planarization process. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method. In some embodiments, vias 230 may also be planarized during planarization of isolation layer 50 . In some embodiments, the thickness T50 of the isolation layer 50 is greater than or substantially equal to the depth D1 of the recess R1 , and the thickness T4 of the isolation layer 240 is less than or substantially equal to the depth D1 of the recess R1 .

In some embodiments, the bottom surface 240b of the isolation layer 240 is substantially flush with the bottom surface 230b of the via hole 230 . That is, the bottom surface 240b of the isolation layer 240 and the bottom surface 230b of the via hole 230 are substantially coplanar. In some embodiments, as shown in FIG. 10 , the portion of each of the via holes 230 protruding from the bottom surface 210 b of the semiconductor substrate 210 is laterally covered by the isolation layer 240 , and the bottom of the via hole 230 is laterally covered by the isolation layer 240 . Surface 230b is exposed by isolation layer 240 in an accessible manner. In some embodiments, with such planarization, carrier dies 10B are formed separated from each other by isolation structures 50(0). In the present disclosure, for example, as shown in FIG. 10 , the carrier dies 10B each have a front surface S3 and a back surface S4 (eg, bottom surface 240b ) opposite the front surface S3 .

Referring to FIG. 11, in some embodiments, a first set of multiple semiconductor dies 10A" are provided, wherein the semiconductor dies 10A" are stacked on semiconductor die 10B. For example, semiconductor die 10A" and carrier die 10B are fabricated separately as described in conjunction with Figures 1-4 and 5-10, respectively. In some embodiments, a pick and place process, for example, or other A suitable bonding technique removes semiconductor die 10A" from tape frame TP1 (shown in Figure 4) to mount semiconductor die 10A" on carrier die 10B. Semiconductor die 10A" may be tested prior to bonding, So that only Known Good Dies (KGD) are used for bonding. In the present disclosure, semiconductor die 10A" and carrier die 10B are bonded together in a face-to-back configuration. As shown in FIG. 11, for example, the front side of semiconductor die 10A" The surfaces S1 respectively face the back surface S4 of the carrier die 10B.

For illustration purposes, only one semiconductor die 10A" disposed on one carrier die 10B is shown in FIG. 11; however, the number of semiconductor dies 10A" disposed on one carrier die 10B is not limited to the present disclosure. Based on design layout and requirements, the number of semiconductor dies 10A" may be one or more than one. For example, in alternate embodiments, a plurality of semiconductor dies 10A" are provided on one carrier die 10B (see FIG. 45 ). ).

In some embodiments, a bonding process is performed to bond semiconductor die 10A" to carrier die 10B. For example, as shown in FIGS. 11 and 26A (shown by the dashed box (or dashed area) A shown in FIG. As shown in the enlarged cross-sectional view indicated), the bonding interface IF1 between one semiconductor die 10A" and the corresponding underlying carrier die 10B includes metal-to-metal bonding (eg, copper pair copper bonding) and dielectric-to-dielectric bonding (eg, oxide-to-oxide bonding, oxide-to-nitride bonding, or nitride-to-nitride bonding). That is, the bonding process includes a hybrid bonding process. For example, the bonding conductors 150 of the semiconductor die 10A" and the vias 230 of the carrier die 10B are bonded together by copper-to-copper bonding (referred to as direct metal-to-metal bonding), and Dielectric layer 140 (eg, dielectric layer DI4 ) of semiconductor die 10A" and isolation layer 240 of carrier die 10B are bonded by oxide-to-nitride (referred to as direct dielectric-to-dielectric bonding). -to-dielectric bonding)) together. In the present disclosure, the bonding interface IF1 may be referred to as a hybrid bonding interface.

It should be noted that the joining methods described above are examples only, and are not intended to be limiting. In some embodiments, as shown in FIG. 26A , there is an offset between the sidewalls 150SW of the bonding conductors 150 and the sidewalls 230SW of the vias 230 located below the bonding conductors 150 . In other words, since the bonding conductor 150 has a larger bonding surface than the via hole 230, even if misalignment occurs, a direct metal-to-metal bonding can still be achieved, thereby exhibiting better reliability. In some embodiments where the dimensions of the bond conductors 150 are smaller than the dimensions of the corresponding vias 230 , the dielectric layer 140 of the semiconductor die 10A″ proximate the bond conductors 150 may be bonded to the portion of the vias 230 of the carrier die 10B.

In some embodiments, the via 130 may taper (eg, taper) from the interconnect structure 120 to the bottom surface 110b". Alternatively, for example, as shown in Figures 11 and 26A , the via hole 130 has substantially vertical (vertical) sidewalls. The shape of the via hole 130 in the cross-sectional view along the stacking direction Z may depend on design requirements and is not intended to be limiting in the present disclosure On the other hand, in the top view (plan) view on the X-Y plane, the shape of the via hole 130 can be determined according to the design requirements, and can be a circular shape, an oval shape, a rectangular shape, a polygonal shape or a combination thereof; The present disclosure is not so limited.Similar geometric specifications can also be applied to the vias 230 of the carrier die, and thus will not be described in detail herein.

For example, as shown in FIGS. 11 and 26A , each bond conductor 150 of one semiconductor die 10A″ distributed at front surface S1 and the corresponding one of the semiconductor die 10B below the bond conductor 150 The vias 230 are in physical and electrical contact. In some embodiments, such bond conductors 150 are in physical and electrical contact with corresponding metallization patterns MP overlying the bond conductors 150, as shown in Figure 26A. However, The present disclosure is not so limited; in alternative embodiments, such bonding conductors 150 may be in physical and electrical contact with corresponding conductive pads AP overlying the bonding conductors 150, as shown in FIG. 26B.

12, in some embodiments, isolation structure 50(0) is removed from temporary carrier TC2. For example, the isolation structures 50(0) may be removed by etching or a similar process; the present disclosure is not so limited. For example, the etching process may include dry etching, wet etching, or a combination thereof. In one embodiment, as shown in FIG. 12, the isolation layer 240 of each carrier die 10B exposed by the overlying semiconductor die 10A" remains during removal of the isolation structure 50(0) However, in an alternative embodiment, the isolation layer 240 of each carrier die 10B exposed by the overlying semiconductor die 10A" may be simultaneously removed during the removal of the isolation structure 50(0).

12 and 13 together, in some embodiments, a thinning process (eg, grinding, CMP, or the like) may be performed on the bottom surface 110b" of the semiconductor die 10A" to form a thinned semiconductor die Die 10A'''. In some embodiments, vias 130 are exposed by bottom surface 110b''' of thinned semiconductor die 10A'''. That is, during bonding of semiconductor die 10A'' to the carrier tube Following the die 10B, the semiconductor die 10A" is thinned to form a thinned semiconductor die 10A"' having a thickness T5 ranging approximately from 40 μm to 200 μm. As shown in 13, for example, in each of the thinned semiconductor dies 10A''', the bottom surface 130b of the via 130 is accessible by the bottom surface 110b''' of the semiconductor substrate 110. For example, in each thinned semiconductor die 10A''', the bottom surface 130b of the via 130 is substantially flush and coplanar with the bottom surface 110b''' of the semiconductor substrate 110. In the In each of the thinned semiconductor dies 10A"', since the vias 130 extend through the semiconductor substrate 110, the vias 130 are referred to as semiconductors when the semiconductor substrate 110 is a silicon substrate Through-hole (TSV) or TSV.

14, in some embodiments, the thinned semiconductor die 10A"' is recessed such that the vias 130 protrude from the semiconductor substrate 110. In other words, the thinned semiconductor die is partially removed The semiconductor substrate 110 of each of the cores 10A ″′ obtains a bottom surface 110 b , and portions of each of the vias 130 protrude from the bottom surface 110 b of the semiconductor substrate 110 . After the recesses are performed, in the cross section shown in FIG. 14 , a plurality of recesses R2 are formed, wherein each of the recesses R2 is formed on the bottom surface 110 b and between the protruding portions of two adjacent via holes 130 . For example, the recesses R2 each have a depth D2 (as measured along the stacking direction Z) ranging approximately from 0.5 μm to 1.5 μm. The recessing process is similar to the process described in connection with FIG. 8 and therefore will not be described in detail herein.

Referring to FIG. 15, in some embodiments, an isolation layer 51 is formed over the temporary carrier TC2. In some embodiments, the isolation layer 51 includes a first lateral portion 51a, a second lateral portion 51b, and a connecting portion 51c. For example, as shown in FIG. 15 , the first lateral portion 51 a is disposed on and extends over the temporary bonding layer TB2 , and the second lateral portion 51 b is disposed on the bottom surface 110 b of the semiconductor substrate 110 and on the bottom surface 130b and the sidewalls 130s of the via hole 130 and extending over the bottom surface 110b of the semiconductor substrate 110 and the bottom surface 130b and the sidewall 130s of the via hole 130 , and the connecting portion 51c is provided on the first side Upward portion 51a and extending into contact with second lateral portion 51b. In some embodiments, isolation layer 51 has a thickness T51 ranging approximately from 0.5 μm to 1.6 μm, where thickness T51 is measured as the minimum distance between opposite sides of isolation layer 51 . As shown in FIG. 15, the second lateral portion 51b fills the recess R2. In one embodiment, the thickness T51 is greater than the depth D2, although the present disclosure is not limited thereto. In an alternative embodiment, thickness T51 is substantially equal to depth D2. In other words, the isolation layer 51 is thick enough to cover the protruding portion of each of the vias 130 . As shown in FIG. 15 , for example, a portion of the via hole 130 protruding from the bottom surface 110 b of the semiconductor substrate 110 is surrounded by the second lateral portion 51 b of the isolation layer 51 .

In some embodiments, as shown in FIG. 15, the first and second lateral portions 51a and 51b extend laterally (eg, in direction X and/or direction Y), and the connecting portion 51c may be stepped toward the Extends upward (eg extends along stacking direction Z in addition to direction X and/or direction Y). The formation and material of the isolation layer 51 may be the same as the formation process of the isolation layer 50 as illustrated in FIG. 9 , and thus will not be described in detail herein. In one embodiment, the thickness T51 of the isolation layer 51 may be the same as the thickness T50 of the isolation layer 50 . In alternative embodiments, the thickness T51 of the isolation layer 51 may be different from the thickness T50 of the isolation layer 50 .

Referring to FIGS. 15 and 16 together, in some embodiments, isolation layer 51 is partially removed to expose vias 130 . In such an embodiment, the isolation layer 51 is planarized, wherein one first lateral portion 51 a and the planarized connecting portion 51 c ′ connected to the one first lateral portion 51 a together constitute one isolation structure 50 (1), and the second lateral portion 51b of the isolation layer 51 is planarized to form the isolation layer 160 disposed on the bottom surface 110b. The planarization process may include being performed by, for example, a CMP process or the like. So far, the semiconductor die 10A is manufactured. In some embodiments, the thickness T10A of the semiconductor die 10A ranges from approximately 3 μm to 50 μm. In some embodiments, thickness T10A is less than or substantially equal to thickness T5. In this disclosure, in the semiconductor structure P1a, the semiconductor die 10A here is referred to as the first level 10A( 1 ) of the die stack. It should be noted that various layers and features of the semiconductor die are omitted from the figures, and that the semiconductor die 10A may include more elements formed therein to perform different functions.

In some embodiments, as shown in FIG. 16, isolation layer 160 exposes vias 130 in an accessible manner for further electrical connection. In some embodiments, the thickness T6 of the isolation layer 160 ranges from approximately 0.3 μm to 1 μm. After the planarization process, for example, a cleaning process may optionally be performed to clean and remove residues generated by the planarization process. However, the present disclosure is not limited thereto, and the planarization process may be performed by any other suitable method. In some embodiments, vias 130 may also be planarized during planarization of isolation layer 51 . In some embodiments, the thickness T51 of the isolation layer 51 is greater than or substantially equal to the depth D2 of the recess R2, and the thickness T6 of the isolation layer 160 is less than or substantially equal to the depth D2 of the recess R2.

In some embodiments, the bottom surface 160b of the isolation layer 160 is substantially flush with the bottom surface 130b of the via hole 130 . That is, the bottom surface 160b of the isolation layer 160 and the bottom surface 130b of the via hole 130 are substantially coplanar. In some embodiments, as shown in FIG. 16 , the portion of each of the via holes 130 protruding from the bottom surface 110 b of the semiconductor substrate 110 is laterally covered by the isolation layer 160 , and the bottom of the via hole 130 is covered laterally by the isolation layer 160 . Surface 130b is accessible by isolation layer 160 . In some embodiments, with such planarization, semiconductor dies 10A are formed separated from each other by isolation structures 50(1). In the present disclosure, for example, as shown in FIG. 16 , semiconductor dies 10A each have a front surface S1 and a back surface S2 (eg, bottom surface 160b ), the back surface S2 being opposite the front surface S1 . That is, for example, the front surfaces S1 of the semiconductor die 10A (eg, the first level 10A( 1 ) of the die stack) respectively face and are bonded to the carrier die 10B (eg, the base level of the die stack) 10B(0)) back surface S4.

Referring to FIG. 17, in some embodiments, a second plurality of semiconductor dies 10A" are provided, and the semiconductor dies 10A" are respectively stacked on the semiconductor dies 10A of the first level 10A(1). In this disclosure, each semiconductor die 10A" (from the second group) is disposed on one of the semiconductor dies 10A of the first level 10A( 1 ) in a face-to-face configuration for forming a die stack of the second level (eg, 10A( 2 ) shown in FIG. 18 ). For example, the front surfaces S1 of the semiconductor dies 10A" (from the second group) face the first level 10A( 1 ), respectively. Back surface S2 of semiconductor die 10A. Similar to the process set forth in FIG. 11 , prior to semiconductor die 10A″ being removed from tape frame TP1 (shown in FIG. 4 ) for mounting on semiconductor die 10A of first level 10A( 1 ) Previously, semiconductor die 10A" could be tested so that only known good die (KGD) were used for bonding.

In some embodiments, the bonding process is performed by hybrid bonding to bond semiconductor die 10A″ to semiconductor die 10A. For example, as shown in FIGS. As shown in the enlarged cross-sectional view indicated by dashed area) B), the bonding interface IF2 between one semiconductor die 10A" and the corresponding underlying semiconductor die 10A includes a metal-to-metal bond (eg, a copper-to-copper bond) and an intermediate Dielectric-to-dielectric bonding (eg, oxide-to-oxide bonding, oxide-to-nitride bonding, or nitride-to-nitride bonding). For example, the bonding conductors 150 of the semiconductor die 10A" and the vias 130 of the semiconductor die 10A are bonded together by copper-to-copper bonding (referred to as direct metal-to-metal bonding), and the dielectric of the semiconductor die 10A" Layer 140 (eg, dielectric layer DI4 ) is bonded to isolation layer 160 of semiconductor die 10A by oxide-to-nitride bonding (referred to as direct dielectric-to-dielectric bonding). In the present disclosure, the bonding interface IF2 may be referred to as a hybrid bonding interface.

It should be noted that the joining methods described above are examples only, and are not intended to be limiting. As shown in FIG. 27A , for example, there is an offset between the sidewall 150SW of the bonding conductor 150 and the sidewall 130SW of the via hole 130 located below the bonding conductor 150 . In other words, since the bonding conductor 150 has a larger bonding surface than the via hole 130, even if misalignment occurs, a direct metal-to-metal bonding can be achieved, thereby exhibiting better reliability. In some embodiments where the dimensions of the bond conductors 150 are smaller than the dimensions of the corresponding vias 130 , the dielectric layer 140 of the semiconductor die 10A″ proximate the bond conductors 150 may be further bonded to portions of the vias 130 of the semiconductor die 10A , such as metal-to-dielectric bonding.

As shown in FIGS. 17 and 27A , for example, each bond conductor 150 of one semiconductor die 10A″ distributed at the front surface S1 and the corresponding one of the semiconductor die 10A located below the bond conductor 150 The vias 130 are in physical and electrical contact. In some embodiments, as shown in Figure 27A, such bond conductors 150 are in physical and electrical contact with corresponding metallization patterns MP overlying the bond conductors 150. However, The present disclosure is not so limited; in alternative embodiments, see FIG. 27B , such bonding conductors 150 may be in physical and electrical contact with corresponding conductive pads AP overlying the bonding conductors 150 .

Referring to Figure 18, in some embodiments, the steps set forth in Figures 12-17 are repeated to form a plurality of die stacks 100 over the plurality of carrier dies 10B in the base level 10B(0). As shown in FIG. 18, one die stack 100 is provided on one carrier die 10B. In some embodiments, the die stacks 100 each include one topmost level 10A(T), where the topmost level 10A(T) includes the semiconductor die 10A" depicted in FIG. 4 . It should be understood that the notation T indicates each The number of levels of a die stack 100, and each of the die stacks 100 disposed on the base level 10B(0) may include any number of levels. For example, T is an integer greater than 1. For example, as shown in FIG. As shown in 18, semiconductor die 10A" has vias 130 that are not exposed. In some embodiments, in each of the die stacks 100, the semiconductor dies 10A" in the topmost level 10A(T) are larger than the inner levels (eg, 10A(1) to 10A(T-1)) Any of the underlying semiconductor dies 10A of the )), the thickness T10A of one level composed of other semiconductor dies 10A.

For example, in each die stack 100, the semiconductor die 10A at the second level 10A(2) is fabricated by performing the method described in connection with FIGS. 13-16 on the structure depicted in FIG. 17 , and thus the semiconductor die 10A at the first level 10A(1) and the second level 10A(2) may be similar or identical in configuration, function and properties. That is, since similar formation steps are used, the semiconductor dies 10A at the first level 10A( 1 ) to the (T-1)th level 10A(T-1 ) of each die stack 100 are in configuration, functional and may be similar or identical in nature. For example, the die stacks 100 each have sidewalls 100S with flat surfaces. In some embodiments, along direction X, the width W10B of each carrier die 10B is greater than the width W100 of (each semiconductor die 10A/10A" of each die stack 100 ). As shown in FIG. 18 , at In some embodiments, there is an offset between the sidewalls 100S of one die stack 100 and the sidewalls S5 (see FIG. 19 ) of the carrier die 10B below the one die stack 100 .

In some embodiments, semiconductor dies in levels (eg, such as inner levels 10A(1)/10A(2), 10A(T-1) and topmost level 10A(T), etc.) may be tested prior to bonding (eg, 10A and 10A") so that only Known Good Dies (KGD) are used to form the die stack 100, thereby increasing the manufacturing yield. The semiconductor dies (eg, 10A and 10A") are memory tubes In some embodiments of the die, due to the vertical stacking and bonding of the semiconductor dies, the die stack 100 may enable faster inter-memory communication during operation, which in turn may increase data bandwidth and enable faster data access and data storage. In some embodiments, during operation, the semiconductor die at the first level 10A(1) may help manage other levels (eg, 10A(2) through 10A(T-1)) stacked on the semiconductor die and data storage and data format interoperability between corresponding semiconductor dies at 10A(T)) and/or carrier dies 10B at base level 10B(0).

In some embodiments, the semiconductor dies (eg, 10A and 10A") of die stack 100 are vertically stacked and bonded by hybrid bonding. For example, for every two adjacent levels of one die stack 100, The upper level is joined to the lower level in a face-to-back configuration. In some embodiments, as shown in Figure 18, the front surface S1 of the second level 10A(2) is joined to the back surface S2 of the first level 10A(1). With this bonding (without using any other external connections), there is no gap between the dies at two adjacent stack levels, thus enabling a better form factor and higher density die stacking in the device As shown in Figure 18, for example, die stacks 100 are separated and isolated from each other by isolation structures 50 (T-1), and carrier dies 10B are also separated from each other by isolation structures 50 (T-1) separation and isolation.

Referring to Figure 19, in some embodiments, isolation structure 50 (T-1) is removed from temporary carrier TC2. For example, the isolation structure 50 (T-1) may be removed by etching or the like; the present disclosure is not limited thereto. The etching process is similar to the steps illustrated in FIG. 12 and therefore will not be described in detail herein. That is, for example, the die stacks 100 are separated and isolated from each other by gaps, and the carrier dies 10B are also separated and isolated from each other by gaps.

As shown in FIGS. 19 and 28A (showing an enlarged cross-sectional view indicated by the dashed box (or dashed area) C shown in FIG. 19 ), the internal levels (eg, 10A(1) to 10A(T-1)) At least one of the semiconductor substrates 110 of the semiconductor die 10A in can have a rounded edge RE. For example, for each of the semiconductor dies 10A, the rounded edge RE is connected to the bottom surface 110b and the sidewalls 110s of the semiconductor substrate 110 . In some embodiments, the dielectric layer 140 of the semiconductor die 10A at the second level 10A(2) is a substantially flat surface such that the rounding of the semiconductor die 10A at the first level 10A(1) A gap is formed between the edge RE and the dielectric layer 140 of the semiconductor die 10A at the second level 10A(2). For such embodiments, in successive steps, the gaps may be filled by later-formed layers/elements such as a dielectric layer, a conductive layer, or a layer having at least one dielectric layer and at least one conductive layer. That is, the rounded edge RE can be covered by a layer/element formed later. The present disclosure is not limited thereto. In alternative embodiments, the gaps may not be filled, and the rounded edges RE may not be covered by any layers/elements. In some embodiments, the rounded edge RE is formed during a backside thinning process (eg, the steps set forth in connection with FIG. 13 ). For example, a grinding pad in contact with the edge of the semiconductor die rounds the edge of the semiconductor die. Through the formation of the rounded edge RE, the semiconductor die 10A can disperse the stress in the edge/corner regions caused by mechanical/thermal stress and bonding, thereby preventing cracking.

In other embodiments, as shown in FIG. 28B , the rounded edge RE may be replaced by a bevel edge BE, wherein the bevel edge BE is connected to the bottom surface 110b and sidewalls 110s of the semiconductor substrate 110 . In some embodiments, the dielectric layer 140 of the semiconductor die 10A at the second level 10A(2) is a substantially flat surface such that the beveled edges of the semiconductor die 10A at the first level 10A(1) A gap is formed between the BE and the dielectric layer 140 of the semiconductor die 10A at the second level 10A(2). For such embodiments, in successive steps, the gaps may be filled by later-formed layers/elements such as a dielectric layer, a conductive layer, or a layer having at least one dielectric layer and at least one conductive layer. That is, the beveled edge BE can be covered by a layer/element formed later. However, in alternative embodiments, the gap may not be filled and the bevel edge BE may not be covered by any layers/elements. In some embodiments, the beveled edge BE is formed by a singulation mark formed at the scribe line for the singulation process (eg, the steps set forth in connection with FIG. 4 ). For example, the singulation marks used to indicate the boundaries of the semiconductor die slope the edges of the semiconductor die. Through the formation of beveled edges BE, semiconductor die 10A can dissipate stress in edge/corner regions caused by mechanical/thermal stress and bonding, thereby preventing cracking.

In still other embodiments, as shown in FIG. 28C , the bottom surface 110b and the sidewalls 110s of the semiconductor substrate 110 may be directly connected at sharp edges SE. In such an embodiment, no gap is formed between the sharp edge SE of the semiconductor die 10A at the first level 10A(1) and the dielectric layer 140 of the semiconductor die 10A at the second level 10A(2). In some embodiments, the sharp edge SE may or may not be covered by any layer/element.

As shown in FIGS. 19 and 29A (showing an enlarged cross-sectional view indicated by the dashed box (or dashed area) D shown in FIG. 19 ), the semiconductor of the semiconductor die 10A″ at the topmost level 10A(T) Substrate 110 may have beveled edges BE. For example, for semiconductor die 10A", beveled edges BE are connected to bottom surface 110b" and sidewalls 110s of semiconductor substrate 110. For such embodiments, in successive steps , the bevel edge BE may be covered by a later-formed layer/element, such as a dielectric layer, a conductive layer, or a layer having at least one dielectric layer and at least one conductive layer, etc. The present disclosure is not limited thereto. In alternative embodiments, the bevel The edge BE may not be covered by any layer/element.

However, the present disclosure is not limited thereto. In other embodiments, as shown in FIG. 29B, the bottom surface 110b" and the sidewalls 110s of the semiconductor substrate 110 may be directly connected at the sharp edge SE. In some embodiments, the sharp edge SE may or may not be covered by any Layer/element overlay.

到

的厚度T60，其中厚度T60是以电磁干扰屏蔽材料60A的相对两侧之间的最小距离来测量。举例来说，电磁干扰屏蔽材料60A至少覆盖管芯堆叠100的侧壁100S及底表面100b，且进一步覆盖基础层级10B(0)的载体管芯10B的侧壁S5以及背表面S4的部分。Referring to FIG. 20 , in some embodiments, an electromagnetic interference shielding material 60A is disposed on the temporary carrier TC2 , and the electromagnetic interference shielding material 60A is disposed on the die stack 100 and the carrier tubes of the base level 10B( 0 ). on the core 10B. In some embodiments, electromagnetic interference shielding material 60A conformally covers die stack 100 and carrier die 10B of base level 10B( 0 ). In some embodiments, the electromagnetic interference shielding material 60A has a range approximately between

arrive

The thickness T60 of , where thickness T60 is measured as the minimum distance between opposite sides of the electromagnetic interference shielding material 60A. For example, EMI shielding material 60A covers at least sidewalls 100S and bottom surface 100b of die stack 100, and further covers portions of sidewalls S5 and back surface S4 of carrier die 10B of base level 10B(0).

In some embodiments, the electromagnetic interference shielding material 60A may be made of a conductive material. Materials for the electromagnetic interference shielding material 60A may include copper, nickel, an alloy of nickel and iron, an alloy of copper and nickel, silver, and the like, but are not limited thereto. In some embodiments, the EMI shielding material 60A may be fabricated using electrolytic plating, electroless plating, sputtering, physical vapor deposition (PVD), chemical vapor deposition, or other suitable metal deposition processes. If desired, a patterning process may optionally be performed to expose portions of the temporary bonding layer TB2. The patterning process may include etching processes such as dry etching, wet etching, or a combination thereof.

21, in some embodiments, after the EMI shielding material 60A is formed, an insulating material 20' is formed over the temporary carrier TC2 to encapsulate the EMI shielding material 60A, the die stack 100, and the carrier die 10B. For example, insulating material 20' may be a molding compound, epoxy, similar material, or other suitable electrically insulating material, and may be applied by compression molding, transfer molding, or a similar process . In some embodiments, the electromagnetic interference shielding material 60A, die stack 100 and carrier die 10B are overmolded and then overmolded using, for example, grinding, chemical mechanical polishing (CMP), a combination thereof, or other suitable thinning process The insulating material 20' is thinned to reduce the overall thickness of the structure. For example, the bottom surface 100b of the die stack 100 (eg, the bottom surface 110b" of the semiconductor die 10A") is exposed by the insulating material 20' after thinning.

In some embodiments, the electromagnetic interference shielding material 60A is also patterned to form the electromagnetic interference shielding layer 60 during the thinning of the insulating material 20'. In certain embodiments, the thinning step may be performed, for example, on the overmolded insulating material 20', such that the surface 20b of the insulating material 20', the bottom surface 100b of the die stack 100 (eg, the semiconductor die 10A) ”) and the surface S60 of the electromagnetic interference shielding layer 60 are flush. For example, surface 20b of insulating material 20', bottom surface 100b of die stack 100 (eg, bottom surface 110b" of semiconductor die 10A"), and surface S60 of electromagnetic interference shielding layer 60 are substantially flush with each other. In other words, surface 20b of insulating material 20' is substantially coplanar with bottom surface 100b of die stack 100 (eg, bottom surface 110b" of semiconductor die 10A") and surface S60 of EMI shielding layer 60. As shown in FIG. 21, for example, the electromagnetic interference shielding layer 60 does not extend over the bottom surface 100b of the die stack 100 (eg, the bottom surface 110b" of the semiconductor die 10A"), and the carrier die 10B and is disposed on the The die stack 100 on the carrier die 10B is separated from the insulating material 20 ′ by the electromagnetic interference shielding layer 60 .

The insulating material 20' may include a low moisture absorption rate and may be rigid after curing for protecting the electromagnetic interference shielding layer 60, the die stack 100, and the carrier die 10B. The electromagnetic interference shielding layer 60 is used to reduce or suppress the electromagnetic field in the space by blocking the electromagnetic field in the space with a barrier made of a conductive material or a magnetic material. In some embodiments, electromagnetic interference shielding layer 60 may reduce coupling of, for example, radio waves, electromagnetic fields, and electrostatic fields. In some embodiments, the electromagnetic interference shielding layer 60 may be in electrical contact with a ground (not shown) to be electrically grounded.

In some embodiments, the semiconductor substrate 110 of the semiconductor die 10A" may also be patterned during the thinning of the insulating material 20', to which the present disclosure is not limited. In other embodiments, the thinning may be omitted process, and bury or cover EMI shielding material 60A, die stack 100, and carrier die 10B by insulating material 20'. In such an embodiment, EMI shielding material 60A acts as an EMI shielding layer and is connected to ground ( not shown) in electrical contact for electrical grounding.

Referring to Figure 22, in some embodiments, another temporary carrier TC3 is attached to the insulating material 20', optionally opposite the temporary carrier TC2. In some embodiments where insulating material 20' is thinned to expose semiconductor die 10A" at topmost level 10A(T), temporary carrier TC3 is bonded to insulating material 20' (eg, surface 20b) through temporary bonding layer TB3 and bottom surface 100b of die stack 100 (eg, bottom surface 110b" of semiconductor die 10A"). A lift-off process may be performed in which temporary carrier TC2 and temporary bonding are released from carrier die 10B at base level 10B(0). layer TB2, thereby exposing front surface S3 of carrier die 10B and surface 20a of insulating material 20'. For example, in stacking direction Z, surface 20a of insulating material 20' is opposite surface 20b of insulating material 20'. In some embodiments, the front surface S3 of the carrier die 10B is cleaned after stripping the temporary carrier TC2 for further processing. The stripping process has been illustrated in Figure 4 and is therefore not discussed herein for simplicity Repeat.

Referring to FIG. 23 , in some embodiments, after the temporary carrier TC2 and the temporary bonding layer TB2 are removed, a plurality of conductive terminals 30 are subsequently formed at the exposed front surface S3 of the carrier die 10B. The conductive terminals 30 may be formed using, for example, sputtering, printing, plating, deposition, or the like. The conductive terminals 30 may be formed from conductive materials including copper, aluminum, gold, nickel, silver, palladium, tin, solder, metal alloys, similar materials, or combinations thereof. For example, each of the conductive terminals 30 includes bumps 31 . The bumps 31 can be micro bumps, metal pillars, bumps formed by electroless nickel-electroless palladium-immersion gold (ENEPIG), controlled collapse chip connection (C4) bumps, balls Ball grid array (BGA) bumps or the like. In embodiments where bumps 31 are micro-bumps, the bump pitch between two adjacent bumps 31 ranges from about 35 μm to about 55 μm. The bumps 31 may be solderless and may have substantially vertical (vertical) sidewalls. In some embodiments, each of the conductive terminals 30 includes a metal cap 32 formed on top of the bumps 31 by, for example, plating, printing, or the like. For example, the material of the metal cap 32 includes nickel, tin, tin lead, gold, silver, palladium, nickel palladium gold, nickel gold, the like, or any combination of these.

In some embodiments, prior to forming the conductive terminals 30 , as shown in FIG. 23 , a protective layer 70 is formed at the base level 10B( 0 ) of the die stack 100 . In some embodiments, protective layer 70 is disposed on carrier die 10B and insulating material 20' and extends to cover front surface S3 of carrier die 10B and surface 20a of insulating material 20'. In other words, protective layer 70 is in contact with insulating material 20' and carrier die 10B. For example, the protective layer 70 includes passivation materials such as silicon oxide, silicon nitride, undoped silicate glass, polyimide, or other suitable insulating materials for protecting the underlying structures. In some embodiments, protective layer 70 includes a plurality of openings OP that expose underlying conductive features (not shown) in interconnect structures 220 of each of carrier dies 10B at least in part for further electrical connections. For example, as shown in FIG. 23 , conductive terminals 30 are formed in physical and electrical contact with conductive features in interconnect structures 220 of carrier die 10B exposed through openings OP formed in protective layer 70 .

Alternatively, the protective layer 70 may be omitted, and the present disclosure is not limited thereto. In such an embodiment, the conductive terminals 30 are formed directly on the carrier die 10B for physical and electrical contact with the conductive features in the interconnect structures 220 of the carrier die 10B.

Alternatively, the protective layer 70 may be replaced by a redistribution wiring structure (not shown) that includes one or more dielectric layers and one or more metallization layers in an alternating arrangement. In such an embodiment, the conductive terminals 30 are formed on the redistributed wiring structure to make electrical contact with conductive features in the interconnect structure 220 of the carrier die 10B through the metallization layer in the redistributed wiring structure.

24, in some embodiments, the temporary carrier TC3 and the temporary bonding layer TB3 are removed from the insulating material 20' and the die stack 100 by a lift-off process. For example, the lift-off process includes applying energy to the temporary bonding layer, mechanical exfoliation, etching, or other suitable removal techniques. Subsequently, a singulation process is performed to form a plurality of separate individual semiconductor structures P1a. The singulation may be performed along scribe lines (not shown) by, for example, sawing, laser cutting, or the like. The insulating material 20' may be cut through to form the insulating envelope 20. The insulating encapsulant 20 exposes the bottom surface 100b of the die stack 100 exposed by the EMI shielding layer 60 and is disposed on the sidewall 100S of the die stack 100 and the carrier die 10C covered by the EMI shielding layer 60 . Part of the side wall S5 and the back surface S4.

In some embodiments, as shown in FIG. 24 , semiconductor structure P1a has a carrier die 10B, a die stack 100 disposed on the carrier die 10B, an insulating package formed on the carrier die 10B and the die stack 100 Encapsulation 20 , EMI shielding layer 60 sandwiched between insulating encapsulation 20 and carrier die 10B and between insulating encapsulation 20 and die stack 100 , disposed on carrier die 10B and insulating encapsulation 20 The protective layer 70 and the conductive terminals 30 provided on the insulating encapsulation body 20 . In some embodiments, carrier die 10B is, for example, a logic die configured to perform read, program, erase, and/or other operations, and die stack 100 is, for example, includes stacking on top of each other and programmed by carrier die 10B memory stack of memory dies. In some embodiments, the semiconductor structure P1a is referred to as a (semiconductor) device package. For example, semiconductor dies 10A/10A" in die stack 100 of semiconductor structure P1a may be high bandwidth memory (HBM) dies, and carrier die 10B may be logic transistors that provide control functions for these memory dies Die. In other words, the semiconductor die 10A/10A" and the carrier die 10B in the die stack 100 are bonded together by hybrid bonding and are electrically connected and in electrical communication with each other. Depending on product requirements, other types of dies may be employed in the semiconductor structure P1a. In this disclosure, die stack 100 is referred to as stack structure SS1 together with carrier die 10B.

In some embodiments, the sidewall S5 of the carrier die 10B covered by the EMI shielding layer 60 is further covered by the insulating encapsulant 20 after singulation. For example, the sidewalls 20S of the insulating encapsulant 20 may be substantially flush with the sidewalls 70S of the protective layer 70 after singulation. That is, the sidewalls 20S of the insulating encapsulation body 20 are aligned with the sidewalls 70S of the protective layer 70 . In some embodiments, as shown in FIG. 24 , the sidewalls 100S of the die stack 100 are remote from the sidewalls 20S of the insulating encapsulant 20 , and the sidewalls S5 of the carrier die 10B are also remote from the sidewalls of the insulating encapsulant 20 . Wall 20s.

As shown in FIGS. 24 and 25 (top plan views on the X-Y plane), for the semiconductor structure P1a, the location of the die stack 100 is within the location of the carrier die 10B and within the location of the insulating encapsulant 20 and the positioning position of the carrier die 10B is within the positioning position of the insulating encapsulation body 20 . In other words, the perimeter of the die stack 100 is smaller than the perimeter of the carrier die 10B and the perimeter of the insulating encapsulation 20 , and the perimeter of the carrier die 10B is smaller than the perimeter of the insulating encapsulation 20 .

However, the present disclosure is not limited thereto. 30 to 44 are schematic cross-sectional views respectively illustrating semiconductor structures according to some embodiments of the present disclosure. For ease of understanding, the same elements are designated by the same reference numerals and will not be repeated here.

In alternate embodiments, additional insulating enclosures may be included. The semiconductor structure P1b shown in FIG. 30 is similar to the semiconductor structure P1a shown in FIG. 24 , except that the semiconductor structure P1b further includes an insulating encapsulant 40 . For example, as shown in FIG. 30 , the insulating encapsulation body 40 is located at least between the protective layer 70 and the insulating encapsulation body 20 . In some embodiments, insulating encapsulation 40 is formed before insulating encapsulation 20 is formed such that insulating encapsulation 40 further covers sidewall S5 of carrier die 10B covered by EMI shielding layer 60 . For example, insulating encapsulant 40 not only further covers the portion of back surface S4 of carrier die 10B that is exposed by die stack 100 and covered by EMI shielding layer 60 , but also covers the tubes covered by EMI shielding layer 60 . Portion of sidewall 100S of core stack 100 . That is, insulating encapsulation 40 is further partially located between insulating encapsulation 20 and carrier die 10B. As shown in FIG. 30 , for example, sidewalls 20S of insulating encapsulation 20 and sidewalls 70S of protective layer 70 are substantially coplanar and aligned with sidewalls 40S of insulating encapsulation 40 .

In some embodiments, insulating encapsulant 40 may be conformally formed by, for example, spin coating, deposition, or the like. In some embodiments, the material of insulating encapsulant 40 may include nitrides (eg, silicon nitride), oxides (eg, silicon oxide), or the like (eg, silicon oxynitride, silicon carbide, polymers, the like) . The present disclosure is not particularly limited. In the present disclosure, the insulating envelope 40 is different from the insulating envelope 20 .

In yet another alternative embodiment, referring to the semiconductor structure P1c depicted in FIG. 31 , the insulating encapsulation 20 is replaced by an insulating encapsulation 40 . The semiconductor structure P1c shown in FIG. 31 is similar to the semiconductor structure P1a shown in FIG. 24 , except that the semiconductor structure P1c employs an insulating encapsulation 40 instead of the insulating encapsulation 20 . For example, the insulating encapsulant 40 completely covers the EMI shielding layer 60 . As shown in FIG. 31 , for example, the sidewalls 70S of the protective layer 70 and the sidewalls 40S of the insulating encapsulant 40 are substantially coplanar and aligned.

In other alternative embodiments, referring to the semiconductor structure P1d depicted in FIG. 32, there is no insulating encapsulation (eg, 20, 40). The semiconductor structure P1d shown in FIG. 32 is similar to the semiconductor structure P1a shown in FIG. 24 except that the die stack 100 and the carrier die 10B are only covered by the EMI shielding layer 60 . As shown in FIG. 32, for example, sidewalls 70S of protective layer 70 are substantially coplanar and aligned with a side of a portion of EMI shielding layer 60 located on sidewall S5 of carrier die 10B.

In some embodiments, compared with the semiconductor structures P1a to P1d, the semiconductor structures P2a to P2d shown in FIGS. 33 to 36 may include isolation structures (eg, 50(T- 1)). For example, the semiconductor structure P2a shown in FIG. 33 is similar to the semiconductor structure P1a shown in FIG. 24 except that, in the semiconductor structure P2a, the isolation structure 50 (T-1) remains on the carrier On die 10B and die stack 100 . As shown in FIG. 33 , isolation structure 50 ( T-1 ) covers portions of sidewall 100S of die stack 100 , sidewall S5 of carrier die 10B, and the back of carrier die 10B exposed by die stack 100 Surface S4. For example, isolation structure 50 ( T - 1 ) is located between die stack 100 /carrier die 10B and insulating encapsulant 20 . As shown in FIG. 33, protective layer 70 is located on carrier die 10B, isolation structure 50 (T-1), EMI shielding layer 60, and insulating encapsulant 20, and the inner levels (eg, 10A(1) to 10A) The sidewalls of (T-1)) are covered by the isolation structures 50 (T-1). Similarly, as shown in FIGS. 34-36, isolation structures may also be introduced into the semiconductor structures P1b, P1c, and P1d to form semiconductor structures P2b, P2c, and P2d, respectively.

On the other hand, in some embodiments, EMI shielding elements (eg, 60 or 60A) may not be included in the semiconductor structures P3a-P3d shown in FIGS. 37-40, respectively, as compared to the semiconductor structures P2a-P2d.

In some embodiments, EMI shielding elements (eg, 60 or 60A) may not be included in the semiconductor structures P4a-P4d shown in FIGS. 41-44, respectively, as compared to the semiconductor structures P1a-P1d. The semiconductor structure P4a depicted in FIG. 41 is similar to the semiconductor structure P1a depicted in FIG. 24 except that in the semiconductor structure P4a the EMI shielding layer 60 is removed from the carrier die 10B and the die stack 100 remove. As shown in FIG. 41 , sidewall 100S of die stack 100 , sidewall S5 of carrier die 10B and back surface S4 of carrier die 10B exposed by die stack 100 are in physical contact with insulating encapsulant 20 . Similarly, as shown in FIGS. 41-44, electromagnetic interference shielding elements may also be removed from semiconductor structures P1b, P1c, and P1d to form semiconductor structures P4b, P4c, and P4d, respectively.

45 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure. 46A and 46B are schematic top views, respectively, illustrating the relative positions among a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure. For ease of understanding, the same elements are designated by the same reference numerals and will not be repeated here. For example, FIG. 45 is a schematic cross-sectional view of semiconductor structure P5 taken along cross-sectional line II-II depicted in FIG. 46A.

The semiconductor structure P5 shown in FIG. 41 is similar to the semiconductor structure P1a shown in FIG. 24, except that in the semiconductor structure P4a, a plurality of die stacks 100 are disposed on one base level 10B(0) . In other words, in semiconductor structure P5, a plurality of semiconductor dies (eg, 10A and 10A") are disposed on one carrier die 10B. In some embodiments, through hybrid bonding, the die stack 100 faces back to back Carrier die 10B bonded to base level 10B( 0 ) is configured. In this disclosure, die stack 100 and carrier die 10B are collectively referred to as stack structure SS2.

As shown in FIGS. 45 and 46A, for example, the die stacks 100 are arranged on the carrier die 10B in a matrix, such as an NxN or NxM array (N, M>0, N may or may not be equal to equal to M). The array size of the die stack 100 can be specified and selected based on requirements and is not limited to this disclosure. In some embodiments, the die stack 100 is arranged in a 1x3 array as depicted in Figure 46A. However, the present disclosure is not so limited; in alternative embodiments, the die stacks 100 may be arranged in a 2x2 array as depicted in Figure 46B.

In some embodiments, for semiconductor structure P5, the location of the die stack 100 is within the location of the carrier die 10B and the location of the insulating encapsulant 20, and the location of the carrier die 10B is within the location of the insulating encapsulation within the positioning position of the body 20 . In other words, carrier die 10B and insulating encapsulant 20 overlap with a plurality of die stacks 100 arranged side by side.

47 is a schematic cross-sectional view illustrating a semiconductor structure according to some embodiments of the present disclosure. 48A and 48B are schematic top views, respectively, illustrating the relative positions among a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure. For ease of understanding, the same elements are designated by the same reference numerals and will not be repeated here. For example, FIG. 47 is a schematic cross-sectional view of semiconductor structure P6 taken along cross-sectional line III-III depicted in FIG. 48A.

The semiconductor structure P6 shown in FIG. 47 is similar to the semiconductor structure P1a shown in FIG. 24, except that the semiconductor structure P4a includes a plurality of stacked structures SS1 (shown in FIG. 24). As shown in FIGS. 47 and 48A , for example, the stacked structures SS1 are arranged side by side in a matrix, eg, in an N×N or N×M array (N, M>0, N may or may not be equal to M). The array size of the stack structure SS1 can be specified and selected based on requirements and is not limited to the present disclosure. In some embodiments, the stacked structures SS1 are arranged in a 1×3 array as depicted in FIG. 48A . However, the present disclosure is not so limited; in alternative embodiments, the stacked structures SS1 may be arranged in a 2×2 array as depicted in FIG. 48B .

As shown in FIGS. 47 and 48 (top plan views in the X-Y plane), for semiconductor structure P6, the location of each die stack 100 is within the location of each carrier die 10B and within the insulating encapsulant 20 , and the positioning position of each carrier die 10B is within the positioning position of the insulating encapsulation body 20 . In other words, the perimeter of each die stack 100 is smaller than the perimeter of each carrier die 10B and the perimeter of the insulating encapsulation 20 , and the perimeter of each carrier die 10B is smaller than the perimeter of the insulating encapsulation 20 .

In addition, the stacked structure SS1 may be partially or completely replaced by the stacked structure SS2 shown in FIG. 45 . The present disclosure is not limited thereto.

49-56 are schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor structure according to some embodiments of the present disclosure. 57 is a schematic top view illustrating the relative positions between a semiconductor die, a carrier die, and an insulating encapsulant of a semiconductor structure according to some embodiments of the present disclosure. For example, FIG. 49 is a schematic cross-sectional view of semiconductor structure P7 taken along cross-sectional line IV-IV depicted in FIG. 57 . For ease of understanding, the same elements are designated by the same reference numerals and will not be repeated here.

49, in some embodiments, a semiconductor wafer W2 is provided. In some embodiments, semiconductor wafer W2 includes a plurality of semiconductor dies 10B' connected to each other. The details of semiconductor die 10B' have already been set forth in FIG. 5 and are therefore not repeated herein for the sake of brevity. For example, each of the semiconductor dies 10B' may include integrated circuit devices (eg, logic dies, memory dies, radio frequency dies, power management dies, microelectromechanical systems (MEMS) dies, the like) or a combination of these).

50, in some embodiments, semiconductor wafer W2 is disposed on temporary carrier TC4 through temporary bonding layer TB4. In some embodiments, a temporary bonding layer TB4 is deposited on the temporary carrier TC4, and the semiconductor wafer W2 is bonded to the temporary bonding layer TB4 through the temporary bonding layer TB4 by placing the front surface S3 of the semiconductor die 10B' in contact with the temporary bonding layer TB4. Temporary vector TC4. Alternatively, the temporary bonding layer TB4 may be omitted. The formation and/or materials of the temporary bonding layer TB4 and the temporary carrier TC4 are similar to the formation and/or materials of the temporary bonding layer TB1 and the temporary carrier TC1 illustrated in FIG. 2 , and thus will not be repeated herein. As shown in Figure 50, for example, the bottom surface 210b' of semiconductor die 10B' faces upward for subsequent processing.

51, in some embodiments, semiconductor wafer W2 is processed to form semiconductor wafer W2' having a plurality of semiconductor dies 10B connected to each other. In some embodiments, semiconductor die 10B is referred to as carrier die 10B. For example, the semiconductor wafer W2 is processed through the steps set forth in FIGS. 7 to 10 , so for the sake of brevity, detailed descriptions are omitted. As shown in FIG. 51 , each of the carrier dies 10B includes a semiconductor substrate 210 in which a plurality of semiconductor devices are formed, an interconnect structure 220 , an isolation layer 240 , and a plurality of vias 230 , the interconnect structure 220 is formed on the semiconductor substrate 210 and includes a plurality of dielectric layers and a plurality of metallization patterns close to the front surface S3, and the isolation layer 240 is formed on the semiconductor substrate 210 opposite to the interconnect structure 220 above, and vias 230 are formed in the semiconductor substrate 210 , extending into the dielectric layer of the interconnect structure 220 for physical and electrical contact with the metallization pattern of the interconnect structure 220 and penetrating the isolation layer 240 . The vias 230 of each of the carrier dies 10B may be electrically coupled to semiconductor devices in the semiconductor substrate 210 through the metallization pattern of the interconnect structure 220 . In some embodiments, the semiconductor dies 10B each have a front surface S3 and a back surface S4 opposite the front surface S3. In some embodiments, each of the carrier dies 10B is referred to as one base level 10B( 0 ) of one die stack 100 .

Referring to FIG. 52, in some embodiments, a first set of multiple semiconductor dies 10A" are provided, wherein the semiconductor dies 10A" are stacked on a carrier die 10B. For example, semiconductor die 10A" is fabricated as described in connection with Figures 1-4. In some embodiments, semiconductor die 10A" is bonded to carrier die 10B in a face-to-back configuration by a hybrid bonding process. The bonding process and bonding relationship/configuration is illustrated in FIG. 11 in conjunction with FIGS. 26A and 26B (showing an enlarged cross-sectional view indicated by the dashed box (or dashed area) A), and is therefore no longer referred to herein. be repeated. For example, as shown in FIG. 52, the front surfaces S1 of the semiconductor die 10A" are respectively bonded to the back surfaces S4 of the carrier die 10B.

Referring to FIG. 53 , in some embodiments, the semiconductor dies 10A″ of the first group are processed to form the plurality of semiconductor dies 10A of the first level 10A( 1 ) in the die stack 100 . For example, The semiconductor die 10A" is processed through the steps illustrated in FIGS. 12-16 , and thus will not be repeated for the sake of brevity. As shown in FIG. 53, each of the semiconductor dies 10A includes a semiconductor substrate 110, an interconnect structure 120, a plurality of vias 130, a dielectric layer 140, a plurality of bonding conductors 150, and an isolation layer 160, A plurality of semiconductor devices (not shown) are formed in the semiconductor substrate 110, the interconnect structure 120 is formed on the semiconductor substrate 110, and the plurality of vias 130 are formed in the semiconductor substrate 110 and extend to the interconnect. Within the wiring structure 120 , a dielectric layer 140 is formed on the wiring structure 120 and opposite the semiconductor substrate 110 , and the plurality of bonding conductors 150 are formed on the wiring structure 120 and are laterally covered by the dielectric layer 140 , the isolation layer 160 is disposed on the semiconductor substrate 110 opposite to the interconnect structure 120 , and the via hole 130 penetrates the isolation layer 160 . In some embodiments, the semiconductor dies 10A each have a front surface S1 and a back surface S2 opposite the front surface S1 . For example, as shown in FIG. 53, semiconductor dies 10A are separated from each other by isolation structures 50(1), which are located over semiconductor wafer W2'.

Referring to FIG. 54, in some embodiments, a second plurality of semiconductor dies 10A" are provided, and the semiconductor dies 10A" are respectively stacked on the semiconductor dies 10A of the first level 10A(1). In this disclosure, each semiconductor die 10A" (from the second group) is disposed on one of the semiconductor dies 10A of the first level 10A( 1 ) in a face-to-face configuration for forming a die stack The second level of 100 (eg, 10A(2) depicted in FIG. 55 ). In some embodiments, the semiconductor die 10A″ (from the second group) is bonded to the first level 10A ( 1) of the semiconductor die 10A. The bonding process and bonding relationship/configuration are illustrated in FIG. 17 in conjunction with FIGS. 27A and 27B (showing enlarged cross-sectional views indicated by dashed box (or dashed area) B), and are therefore not referred to herein. be repeated. For example, as shown in FIG. 54, the front surfaces S1 of the semiconductor dies 10A" (from the second group) are respectively bonded to the back surfaces S2 of the semiconductor dies 10A of the first level 10A(1). For example, The vias 130 are not yet accessible by the semiconductor substrate 110 .

55, in some embodiments, a die stack 100 is formed over the carrier die 10B. For example, each of the die stacks 100 includes at least one inner level (eg, 10A(1)-10A(T-1)) and a topmost level 10A(T). In some embodiments, the structure depicted in FIG. 54 is processed to form die stack 100 . For example, in each die stack 100, each inner level (eg, 10A(2) through 10A(T) may be fabricated through the same steps as described in FIG. 53 to form the first level 10A(1) -1)), and the topmost level 10A(T) can be fabricated by the process illustrated in FIG. 54, and therefore, for the sake of brevity, it will not be repeated. That is, semiconductor dies 10A at inner levels (eg, 10A( 1 ) to 10A(T-1 )) may be individually fabricated by repeating the steps described in FIGS. 12-16 , and may be fabricated by repeating The topmost layer 10A(T) is fabricated as described in FIG. 17 . As such, the semiconductor dies 10A at the first level 10A( 1 ) to the (T-1)th level 10A(T-1 ) of each die stack 100 differ in configuration, function, and Can be similar or identical in nature. In some embodiments, after the die stack 100 is formed, the isolation structures are removed from the semiconductor wafer W2'. For example, for every two adjacent levels of each die stack 100, the upper level is bonded to the lower level in a face-to-face configuration. By this bonding (without using any other external connections), a semiconductor structure P7 with a better form factor and a higher density of die stacks in the device is achieved.

Referring to FIG. 56, in some embodiments, the semiconductor structure P7 is fabricated by processing the structure depicted in FIG. 55 with the steps set forth in FIGS. In some embodiments, semiconductor structure P7 has carrier die 10B, die stack 100 , insulating encapsulant 20 , EMI shielding layer 60 , protective layer 70 and conductive terminals 30 , and die stack 100 is disposed on carrier die 10B above, the insulating encapsulant 20 is formed on the carrier die 10B and the die stack 100 , and the EMI shielding layer 60 is sandwiched between the insulating encapsulation 20 and the carrier die 10B and the insulating encapsulation 20 and the die stack 100 In between, the protective layer 70 is provided on the carrier die 10 , and the conductive terminals 30 are provided on the insulating encapsulant 20 . As shown in FIG. 56 , for example, sidewalls 20S of insulating encapsulant 20 are aligned with sidewalls S5 of carrier die 10B, sidewalls 60S of electromagnetic interference shielding layer 60 , and sidewalls 70S of protective layer 70 . That is, the sidewalls 20S of the insulating encapsulation body 20 may be substantially flush and coplanar with the sidewalls S5 of the carrier die 10B, the sidewalls 60S of the EMI shielding layer 60 and the sidewalls 70S of the protective layer 70 .

As shown in FIGS. 56 and 57 (top plan views in the X-Y plane), for semiconductor structure P7, the location of the die stack 100 is within the location of the carrier die 10B and within the location of the insulating encapsulant 20 , wherein the edge of the carrier die 10B overlaps the edge of the insulating envelope 20 . In other words, the perimeter of the die stack 100 is smaller than the perimeter of the carrier die 10B and the perimeter of the insulating encapsulation 20 , and the perimeter of the carrier die 10B is substantially equal to the perimeter of the insulating encapsulation 20 .

Additionally, modifications to semiconductor structure P1a may also be employed by semiconductor structures P5, P6, and P7. Since the details of the modification to the semiconductor structure P1a are set forth in FIGS. 30 to 44, they are not repeated for the sake of brevity.

58 is a schematic cross-sectional view illustrating the application of a semiconductor structure according to some embodiments of the present disclosure. For ease of understanding, the same elements are designated by the same reference numerals and will not be repeated here. Referring to Figure 58, an assembly assembly SC is provided that includes a first assembly C1 and a second assembly C2 disposed over the first assembly C1. The first component C1 may be or may include an interposer, a package substrate, a printed circuit board (PCB), a printed circuit board, and/or other carriers capable of carrying integrated circuits. In some embodiments, the second component C2 mounted on the first component C1 is similar to the semiconductor structures P1a-P1d, P2a-P2d, P3a-P3d, P4a-P4d, P5, P6, and P7 described above one. For example, one or more semiconductor structures (eg, P1a-P1d, P2a-P2d, P3a-P3d, P4a-P4d, P5, P6, and P7) may be electrically coupled to the first component C1 through a plurality of terminals CT. The terminal CT may be the conductive terminal 30 .

In some embodiments, an underfill layer UF is formed between the gap between the first component C1 and the second component C2 to at least laterally cover the terminal CT. Alternatively, the primer layer UF is omitted. In one embodiment, the undersize UF may be formed by underfill dispensing or any other suitable method. In some embodiments, the material of the primer layer UF may be the same as or different from the material of the insulating encapsulation bodies 20 and 40 , but the present disclosure is not limited thereto. Due to the primer layer UF, the bonding strength between the first component C1 and the second component C2 is enhanced.

In some other embodiments, the second component C2 mounted on the first component C1 may be an integrated fan-out (InFO) package that includes at least one semiconductor structure packaged therein (eg, on P1a-P1d, P2a-P2d, P3a-P3d, P4a-P4d, P5, P6, and P7) described herein in conjunction with Figures 24, 31-44, 45, 47, and 56. For example, the second component C2 includes a plurality of semiconductor structures (eg, semiconductor structures P1a-P1d, P2a-P2d, P3a-P3d) arranged side-by-side and surrounded by a packaging encapsulant (not shown; eg, molding compound) , any combination of P4a-P4d, P5, P6 and P7). The second component C2 may further include a fan-out redistribution structure (not shown) formed on the encapsulation body and the semiconductor structures laterally encapsulated by the encapsulation body, and the fan-out redistribution structure may electrically coupled to these semiconductor structures. In such embodiments, the terminals CT may be controlled collapse chip attach (C4) bumps, ball grid array (BGA) bumps, other suitable terminals having dimensions larger than the conductive terminals of the semiconductor structure, and/or the like. For example, the terminal CT is formed on the fan-out rewiring structure to be electrically coupled to the first component C1, and the semiconductor structures are electrically coupled to the terminal CT through the fan-out rewiring structure.

The component assembly SC may be formed using other packaging techniques, which are not limited in this disclosure. For example, using wafer level packaging (WLP), chip-on-wafer-on-substrate (CoWoS) process, chip-on-substrate (chip-on-substrate) A chip-on-substrate, CoCoS) process, etc. forms a component assembly SC. Component assembly SC may be part of an electronic system for use in, for example, computers (eg, high performance computers), computing devices used in conjunction with artificial intelligence systems, wireless communication devices, computer-related peripheral devices, entertainment devices, and the like. Component assemblies SC including the semiconductor structures discussed herein can provide high bandwidth data communications. It should be noted that other electronic applications are also possible. Alternatively, additional terminals may be in physical and electrical contact with the first component C1 opposite the terminal CT for electrical connection with any other external components.

According to some embodiments, a semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite the first active surface. The second semiconductor die is located over the first semiconductor die and includes a second semiconductor substrate having a second active surface and a second back surface opposite the second active surface. The second semiconductor die is bonded to the first semiconductor die by bonding the second active surface to the first back surface at a first hybrid bonding interface in a vertical direction. In the lateral direction, the first dimension of the first semiconductor die is larger than the second dimension of the second semiconductor die.

According to some embodiments, in the semiconductor structure, wherein the first semiconductor die further comprises a plurality of first vias penetrating the first semiconductor substrate, and the second semiconductor die further comprises including a plurality of second vias penetrating the second semiconductor substrate, and wherein the plurality of first vias are respectively bonded to the plurality of second vias at the first hybrid bonding interface holes, and the first semiconductor die is electrically connected and in electrical communication with the second semiconductor die through the plurality of first vias and the plurality of second vias. According to some embodiments, in the semiconductor structure, wherein the second semiconductor die includes a first stack having a plurality of second semiconductor dies, wherein the first stack having the plurality of second semiconductor dies Two adjacent second semiconductor dies in a stack are bonded to each other by another hybrid bonding interface, and the second active surface of one of the two adjacent second semiconductor dies is in the other hybrid a second back surface bonded to the other of the two adjacent second semiconductor dies at a bonding interface, wherein the plurality of second semiconductor dies in the first stack pass through the plurality of second semiconductor dies The two vias are electrically connected and in electrical communication with each other, and are electrically connected and in electrical communication with the first semiconductor die through the plurality of first vias and the plurality of second vias. According to some embodiments, in the described semiconductor structure, wherein the stacked structure further comprises: a third semiconductor die including a third semiconductor substrate and a plurality of third vias embedded in the third semiconductor substrate a hole having a third active surface and a third back surface opposite the third active surface, wherein: the third semiconductor die attaches the third semiconductor die at the second hybrid bonding interface along the vertical direction A third active surface is bonded to the second back surface of the outermost second semiconductor die in the first stack opposite the first semiconductor die and is bonded to the outermost second semiconductor die, along all the In the lateral direction, the third dimension of the third semiconductor die is substantially equal to the second dimension of each of the second semiconductor die, and the plurality of third vias are in the second hybrid bond a plurality of second vias bonded to the outermost second semiconductor die at interfaces, respectively, and the third semiconductor die and the first semiconductor die and having the plurality of second semiconductor dies The first stack is electrically connected and in electrical communication. According to some embodiments, in the semiconductor structure, wherein the second semiconductor die further includes at least one second stack having a plurality of second semiconductor dies on the first semiconductor die and having The at least one second stack of the plurality of second semiconductor dies is arranged side by side with the first stack having the plurality of second semiconductor dies in the lateral direction, with the plurality of second semiconductor dies having the plurality of second semiconductor dies. Two adjacent second semiconductor dies in the at least one second stack of two semiconductor dies are bonded to each other by another hybrid bonding interface, and the first one of the two adjacent second semiconductor dies is Two active surfaces are bonded to the second back surface of the other of the two adjacent second semiconductor dies at the other hybrid bonding interface, wherein the plurality of the at least one second stack second semiconductor dies are electrically connected and in electrical communication with each other through the plurality of second vias, and with the first semiconductor through the plurality of first vias and the plurality of second vias Die electrical connections and electrical communication. According to some embodiments, in the described semiconductor structure, wherein the stacked structure further comprises: a third semiconductor die including a third semiconductor substrate and a plurality of third vias embedded in the third semiconductor substrate a hole having a third active surface and a third back surface opposite the third active surface, wherein: the third semiconductor die attaches the third semiconductor die at the second hybrid bonding interface along the vertical direction A third active surface is bonded to the second back surface of the outermost second semiconductor die in the first stack opposite the first semiconductor die and is bonded to the outermost second semiconductor die in the first stack Two semiconductor dies, along the lateral direction, the third semiconductor die has a third dimension substantially equal to the second dimension of each second semiconductor die in the first stack, and the A plurality of third vias are respectively bonded to a plurality of second vias of the outermost second semiconductor die in the first stack at the second hybrid bonding interface, and the third semiconductor a die is electrically connected and in electrical communication with the first semiconductor die and the first stack having the plurality of second semiconductor dies; and at least one fourth semiconductor die including a fourth semiconductor substrate and embedded a plurality of fourth vias in the fourth semiconductor substrate having a fourth active surface and a fourth back surface opposite to the fourth active surface, wherein: the at least one fourth semiconductor transistor core by bonding the fourth active surface to an outermost second semiconductor die in the at least one second stack opposite the first semiconductor die at a third hybrid bonding interface in the vertical direction second back surface bonded to the outermost second semiconductor die in the at least one second stack, the at least one fourth semiconductor die has a fourth dimension in the lateral direction that is substantially equal to the the second dimension of each second semiconductor die in the at least one second stack, and the plurality of fourth vias are respectively bonded to the at least one second via at the third hybrid bonding interface a plurality of second vias of the outermost second semiconductor die in the stack, and the at least one fourth semiconductor die and the first semiconductor die and having the plurality of second semiconductor dies The at least one second stack is electrically connected and in electrical communication. According to some embodiments, in the semiconductor structure, wherein the second semiconductor substrate further comprises sidewalls and rounded edges, the rounded edges connect the second back surface and the sidewalls; or sidewalls A wall and a beveled edge connecting the second back surface and the side wall. According to some embodiments, the semiconductor structure further includes a plurality of conductive terminals on the first active surface of the first semiconductor die and electrically connected to the first semiconductor die. According to some embodiments, in the semiconductor structure, wherein the stacked structure includes two or more than two stacked structures.

According to some embodiments, a semiconductor structure includes a semiconductor device, a plurality of conductive terminals, and a connection structure. The semiconductor device includes a base level and a die stack. The base level includes a first die. The die stack is bonded to the base level and includes a plurality of second dies arranged into at least one inner level and an outermost level. The die stack is bonded to the base level through a first hybrid bonding interface. The at least one inner level is joined with the outermost level by a second hybrid joining interface. There is an offset between sidewalls of the base level and sidewalls of the die stack, wherein the first die and the plurality of second dies are in electrical communication with each other. The plurality of conductive terminals are over and electrically connected to the semiconductor device. the connection structure is located between the semiconductor device and the plurality of conductive terminals, wherein the base level is located between the connection structure and the die stack, and the at least one inner level is located at the base level and the outermost level.

According to some embodiments, the semiconductor structure further comprises: an insulating encapsulant overlying the semiconductor device, wherein the base level is located between the insulating encapsulation and the connection structure and the die stack and the Between the connection structures, the sidewalls of the insulating encapsulation body and the sidewalls of the connection structures are substantially coplanar, and the connection structures include a protective layer or a redistributed circuit structure. According to some embodiments, in the semiconductor structure, wherein the sidewalls of the insulating encapsulant are further substantially coplanar with the sidewalls of the base level. According to some embodiments, the semiconductor structure further comprises: a first insulating encapsulation overlying the semiconductor device and covering the base level; and a second insulating encapsulation overlying the first insulating encapsulation over and overlying the die stack, wherein the sidewalls of the first insulating encapsulation and the sidewalls of the second insulating encapsulation are substantially coplanar with the sidewalls of the connection structure, and all The connection structure includes a protective layer or a redistributed circuit structure. According to some embodiments, in the semiconductor structure, wherein the sidewalls of the first insulating encapsulation and the sidewalls of the second insulating encapsulation are further connected to the sidewalls of the base level The side walls are substantially coplanar. According to some embodiments, the semiconductor structure further includes isolation elements at least partially covering sidewalls of the semiconductor device, wherein the isolation elements extend from the base level toward the die stack, wherein the isolation elements The material of the element includes a conductive layer or a dielectric layer. According to some embodiments, in the described semiconductor structure, wherein the die stack includes two or more die stacks. According to some embodiments, in the described semiconductor structure, wherein the semiconductor device comprises two or more semiconductor devices.

According to some embodiments, a method of fabricating a semiconductor structure includes the steps of forming at least one stacked structure, including providing a base level including a first semiconductor die, and forming a base level including a plurality of first semiconductor die on the base level by hybrid bonding A die stack of two semiconductor dies, wherein a first dimension of the base level is greater than a second dimension of the die stack in a lateral direction, and the first semiconductor die is electrically connected to the plurality of second two semiconductor dies; forming a connection structure over the at least one stack structure, the base level being located between the connection structure and the die stack; and disposing a plurality of conductive structures over the at least one stack structure terminals and electrically connect the plurality of conductive terminals to the first semiconductor die, the connection structure being located between the plurality of conductive terminals and the base level.

According to some embodiments, in the method, wherein the die stack includes a bottommost level, a topmost level, and at least one inner level located between the bottommost level and the topmost level, and the The bottommost level, the at least one inner level, and the topmost level each include one or more of the plurality of second semiconductor dies, wherein the base level is formed by hybrid bonding The die stacking includes hybrid bonding the front surface of the bottommost level to the back surface of the base level to bond the first semiconductor die with the plurality of second semiconductor dies of the bottommost level electrically connecting the one or more of the at least one inner level; hybrid bonding the front surface of the at least one inner level to the back surface of the bottommost level to connect the plurality of first levels of the at least one inner level the one or more of the two semiconductor dies is electrically connected to the one or more of the plurality of second semiconductor dies of the bottommost level; and connecting the bottommost level a front surface of the top level is hybrid bonded to a back surface of the at least one inner level to bond the one or more of the plurality of second semiconductor dies of the at least one inner level with the The one or more of the plurality of second semiconductor dies of the topmost level are electrically connected. According to some embodiments, in the method, wherein forming the die stack at the base level by hybrid bonding includes forming a plurality of die stacks at the base level by hybrid bonding.

The features of several embodiments have been summarized above so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or for carrying out the embodiments described herein example of the same advantages. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations without departing from the spirit and scope of the present disclosure. change.

Claims (1)

1. A semiconductor structure comprising: Stacked structure, including: a first semiconductor die including a first semiconductor substrate having a first active surface and a first back surface opposite the first active surface; and A second semiconductor die, overlying the first semiconductor die, includes a second semiconductor substrate having a second active surface and a second opposite the second active surface a back surface and is bonded to the first semiconductor die by bonding the second active surface to the first back surface at a first hybrid bonding interface in a vertical direction, Wherein the first dimension of the first semiconductor die is larger than the second dimension of the second semiconductor die in the lateral direction.

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