CN112115674A - Method, device and equipment for generating chip wiring design file and storage medium - Google Patents
Method, device and equipment for generating chip wiring design file and storage medium Download PDFInfo
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- CN112115674A CN112115674A CN202011043926.0A CN202011043926A CN112115674A CN 112115674 A CN112115674 A CN 112115674A CN 202011043926 A CN202011043926 A CN 202011043926A CN 112115674 A CN112115674 A CN 112115674A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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Abstract
The application discloses a method, a device, equipment and a storage medium for generating a chip wiring design file, and belongs to the technical field of chip manufacturing. The method comprises the following steps: after receiving a chip wiring design instruction, generating a plurality of wiring tracks which are parallel to each other; wiring on each wiring track, wherein if the width of the wired line is detected not to correspond to the preset track distance in the process of wiring the first wiring track, adjusting the current layout of the plurality of wiring tracks according to the width of the wired line, and continuing wiring on the non-wired wiring track in the plurality of wiring tracks after the layout is adjusted; and after the wires are uniformly distributed on each wiring track, generating a chip wiring design file based on the wiring result. The technical scheme provided by the embodiment of the application can avoid the waste of the manufacturing area of the chip, thereby reducing the manufacturing cost of the chip.
Description
Technical Field
The present disclosure relates to the field of chip manufacturing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for generating a chip wiring design file.
Background
In the chip manufacturing process, a chip manufacturer often needs to manufacture various lines (e.g., power lines, etc.) in a chip according to the design of the chip wiring in a chip wiring design file provided by a chip demander. In general, the process of obtaining the chip wiring design file is as follows: firstly, a plurality of parallel wiring tracks are generated, then, wiring is carried out on the wiring tracks, and after wiring is finished, a chip wiring design file can be obtained based on the wiring result.
In the related art, a track distance between a plurality of wiring tracks generated in the process of acquiring a chip wiring design file generally corresponds to a single-line width. In practical applications, if the width of a wire laid on a certain wiring track is greater than a single-line width, the wiring often cannot be performed on the wiring track adjacent to the wiring track, otherwise, the distance between two adjacent wires laid is smaller than the minimum manufacturing pitch, and the manufacturing area of a chip is wasted due to the fact that some wiring tracks cannot perform wiring, thereby increasing the manufacturing cost of the chip.
Disclosure of Invention
Based on this, the embodiments of the present application provide a method, an apparatus, a device, and a storage medium for generating a chip wiring design file, which can avoid waste of a manufacturing area of a chip, thereby reducing a manufacturing cost of the chip.
In a first aspect, a method for generating a chip wiring design file is provided, and the method includes:
after a chip wiring design instruction is received, generating a plurality of wiring tracks which are parallel to each other, wherein the distance between any two adjacent wiring tracks is a preset track distance; wiring on each wiring track, wherein if the width of the wired line is detected not to correspond to the preset track distance in the process of wiring a first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the wired line, and the wiring tracks which are not wired in the plurality of wiring tracks after the layout is adjusted are continuously wired, wherein the first wiring track is any one of the plurality of wiring tracks; and after the wires are uniformly distributed on each wiring track, generating a chip wiring design file based on the wiring result.
In a second aspect, an apparatus for generating a chip wiring design file is provided, the apparatus comprising:
the first generation module is used for generating a plurality of wiring tracks which are parallel to each other after receiving a chip wiring design instruction, wherein the distance between any two adjacent wiring tracks is a preset track distance;
a wiring module, configured to perform wiring on each wiring track, wherein if it is detected that the width of the wired line does not correspond to the preset track distance in the process of wiring a first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the wired line, and the wiring tracks which are not wired in the plurality of wiring tracks after the layout adjustment are continuously wired, wherein the first wiring track is any one of the plurality of wiring tracks;
and the second generation module is used for generating a chip wiring design file based on the wiring result after the wires are uniformly distributed on each wiring track.
In a third aspect, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, the computer program when executed by the processor implementing the method for generating a chip wiring design file as described in any one of the first aspect above.
In a fourth aspect, there is provided a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the method for generating a chip wiring design file according to any one of the first aspects.
The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:
by generating a plurality of wiring tracks which are parallel to each other after receiving a chip wiring design instruction, wherein the distance between any two adjacent wiring tracks is a preset track distance, and then wiring on each wiring track, wherein if the width of the laid wire is detected to be not corresponding to the preset track distance in the process of wiring the first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the laid wire, and the wiring tracks which are not laid out in the plurality of wiring tracks after the adjustment of the layout are continuously wired, then after the wire distribution of each wiring track is completed, a chip wiring design file is generated based on the wiring result, because the current layout of the plurality of wiring tracks generated before can be adjusted under the condition that the width of the laid wire is detected to be not corresponding to the preset track distance, based on the adjustment of overall arrangement, the track distance between first wiring track and rather than adjacent wiring track will change, and the track distance changes, just can guarantee that the distance of the line of laying out on first wiring track and the line of laying out on rather than adjacent wiring track is not less than minimum manufacturing interval, like this, just can guarantee to lay out on first wiring track and rather than adjacent wiring track simultaneously, consequently, just can avoid just can avoiding can't laying out the problem of wiring at some wiring track, then can play and avoid extravagant manufacturing area of chip, thereby reduce the effect of the manufacturing cost of chip.
Drawings
Fig. 1 is a schematic diagram of a wiring track provided in an embodiment of the present application;
fig. 2 is a schematic diagram of a wiring on a wiring track according to an embodiment of the present application;
fig. 3 is a schematic diagram of another wiring on a wiring track according to an embodiment of the present application;
fig. 4 is a schematic diagram of another wiring on a wiring track according to an embodiment of the present application;
fig. 5 is an internal structural diagram of a computer device according to an embodiment of the present application;
fig. 6 is a flowchart of a method for generating a chip wiring design file according to an embodiment of the present application;
FIG. 7 is a flowchart of a process for adjusting a current layout of a plurality of routing tracks according to a width of a routed line according to an embodiment of the present application;
fig. 8 is a schematic diagram of another wiring on a wiring track according to an embodiment of the present application;
fig. 9 is a schematic diagram of another wiring on a wiring track according to an embodiment of the present application;
fig. 10 is a block diagram of an apparatus for generating a chip wiring design file according to an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
In the chip manufacturing process, a chip manufacturer often needs to manufacture various lines (e.g., power lines, etc.) in a chip according to the design of the chip wiring in a chip wiring design file provided by a chip demander.
In order to make the reader easily understand the technical solution provided in the embodiment of the present application, in the following, the embodiment of the present application will briefly describe an acquisition process of a chip wiring design file:
the chip wiring design software can generate a plurality of parallel wiring tracks, please refer to fig. 1, which is a schematic diagram of an exemplary plurality of parallel wiring tracks. After a plurality of wiring tracks which are parallel to each other are generated, wiring can be conducted on the wiring tracks, and the wiring result obtained after wiring is the chip wiring design file. For example, after a plurality of mutually parallel wiring tracks shown in fig. 1 are generated, wiring may be performed on the wiring tracks 1 to 6, respectively, and the wiring result obtained after the wiring is completed is a chip wiring design file.
In the related art, the track distance between a plurality of mutually parallel wiring tracks generated by chip wiring design software generally corresponds to a single-line width. In this case, if the width of the line laid on each wiring track is a single-line width, the distance between any two adjacent lines laid is larger than the minimum manufacturing pitch, and if the width of the line laid on a certain wiring track is larger than the single-line width, the wiring cannot be performed on the wiring track adjacent to the wiring track, otherwise, there is a problem that the distance between two adjacent lines laid is smaller than the minimum manufacturing pitch.
Referring to fig. 2, the track distance between any two adjacent wiring tracks of the parallel wiring tracks 1 to 6 corresponds to a single-line width, and as shown in fig. 2, if the width of the line laid on each wiring track 1 to 6 is a single-line width, the distance between any two adjacent lines is greater than the minimum manufacturing pitch.
Referring to fig. 3, if the track distance between any two adjacent wiring tracks among the wiring tracks 1 to 6 parallel to each other corresponds to the single-line width, as shown in fig. 3, if the width of the lines laid on the wiring tracks 1 and 6 is greater than the single-line width while the wiring tracks 2 and 5 are wired, the distance between the lines laid on the wiring track 1 and the lines laid on the wiring track 2 is smaller than the minimum manufacturing pitch, and the distance between the lines laid on the wiring track 5 and the lines laid on the wiring track 6 is smaller than the minimum manufacturing pitch, which may cause an error in the chip manufacturing process.
Referring to fig. 4, the track distance between any two adjacent wiring tracks among the wiring tracks 1 to 6 parallel to each other corresponds to a single-line width, and if the width of the lines laid on the wiring tracks 1 and 6 is larger than the single-line width as shown in fig. 4, in order to avoid a problem that the distance between two adjacent lines laid is smaller than the minimum manufacturing pitch, it is necessary to not perform wiring on the wiring tracks 2 and 5.
In practical application, the fact that the wiring cannot be carried out on some wiring tracks causes waste of the manufacturing area of the chip, and therefore the manufacturing cost of the chip is increased.
In view of the above, embodiments of the present application provide a method for generating a chip wiring design file, in which after receiving a chip wiring design command, a plurality of parallel wiring tracks are generated, where a distance between any two adjacent wiring tracks is a preset track distance, and then wiring is performed on each wiring track, where if it is detected that a width of a wire to be laid does not correspond to the preset track distance during wiring of a first wiring track, a current layout of the plurality of wiring tracks is adjusted according to the width of the wire to be laid, and the wiring tracks that are not wired in the plurality of wiring tracks after the adjustment of the layout are continuously wired, and then after the wires are uniformly distributed in each wiring track, the chip wiring design file is generated based on a result of the wiring, because the current layout of the plurality of wiring tracks generated before can be adjusted under the condition that the width of the distributed wires is not corresponding to the preset track distance, the track distance between the first wiring track and the wiring track adjacent to the first wiring track can be changed based on the adjustment of the layout, and the track distance is changed, the distance between the wires distributed on the first wiring track and the wires distributed on the wiring track adjacent to the first wiring track can be ensured not to be smaller than the minimum manufacturing distance, thus, the wires can be simultaneously distributed on the first wiring track and the wiring track adjacent to the first wiring track, the problem that the wires cannot be distributed on some wiring tracks can be avoided, the manufacturing area of chips can be prevented from being wasted, and the manufacturing cost of the chips can be reduced.
The method for generating the chip wiring design file provided by the embodiment of the application can be applied to computer equipment provided with chip wiring design software, for example, the computer equipment can be a server, a desktop computer, a tablet computer and the like, and the embodiment of the application does not limit the specific type of the computer equipment.
Referring to fig. 5, an internal structure diagram of a computer device provided in an embodiment of the present application is shown. As shown in fig. 5, the computer device includes a processor and a memory connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The computer program is executed by a processor to implement a method for generating a chip wiring design file.
Those skilled in the art will appreciate that the architecture shown in fig. 5 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
Referring to fig. 6, a flowchart of a method for generating a chip wiring design file according to an embodiment of the present application is shown, where the method for generating a chip wiring design file can be applied to the computer device described above. As shown in fig. 6, the method for generating a chip wiring design file may include the following steps:
In one possible implementation, the chip wiring design software may be provided with wiring design options, and the computer device may receive the chip wiring design instructions after the wiring design options are triggered.
In another possible implementation manner, the chip wiring design software may be preset with a wiring design command, and after the wiring design command input by a user is recognized by the chip wiring design software, the computer device may receive the chip wiring design command.
After receiving a chip wiring design instruction, the computer device may generate, through chip wiring design software, a plurality of mutually parallel wiring tracks according to a default generation strategy, where a distance between any two adjacent wiring tracks in the generated plurality of mutually parallel wiring tracks is a preset track distance.
It is noted that in an alternative embodiment of the present application, the preset track distance may correspond to a single line width. It should be further noted that the plurality of wiring tracks parallel to each other generated in step 601 are the same as those shown in fig. 1, and the embodiments of the present application are not separately illustrated in the drawings.
In an alternative embodiment of the present application, the computer device may be wired on the respective wiring tracks by chip wiring design software. In an alternative embodiment of the present application, the chip wiring design software may be preset with wiring commands, and after the user-input wiring commands are recognized by the chip wiring design software, the computer device may perform wiring on the respective wiring tracks based on the user-input wiring commands.
In one possible implementation, the computer device may route wires on the respective routing tracks in turn. For example, if the computer device generates the wiring tracks 1 to 6 in step 601, the computer device may first wire on the wiring track 1, then wire on the wiring track 2, then wire on the wiring track 3, and so on, and finally wire on the wiring track 6 in step 602.
In another possible implementation, the computer device may route wires on the respective routing tracks simultaneously. For example, if the computer device generates the wiring tracks 1 to 6 in step 601, the computer device may simultaneously perform wiring on the wiring tracks 1 to 6 in step 602.
In yet another possible implementation, the computer device may first perform wiring on some or one wiring track, then perform wiring on some or one other wiring track, and then continue to perform wiring on some or one other wiring track until the wiring is completed. For example, if the computer device generated wiring tracks 1 to 6 in step 601, then in step 602 the computer device may first route wiring on wiring tracks 1 and 2, then the computer device may route wiring on wiring tracks 3 and 4, and then the computer device may route wiring on wiring tracks 5 and 6.
In the process of wiring each wiring track, the computer device may detect whether the width of the wired line and the preset track distance correspond to each other. For example, in the case where the preset track distance corresponds to the single line width, the computer apparatus may detect whether the width of the laid line is the single line width in the course of wiring each wiring track.
If, for the first wiring track, which is any one of the plurality of wiring tracks generated in step 601, the computer device detects that the width of the wired line does not correspond to the preset track distance, the computer device may adjust the current layout of the plurality of wiring tracks according to the width of the wired line.
It should be noted that, if the first routing track is a routing track generated in step 601, where the width of the first wire laid in the plurality of routing tracks does not correspond to the preset track distance, the current layout of the plurality of routing tracks may refer to the initial, unadjusted layout of the plurality of routing tracks.
If the first routing track is a routing track in which the width of the n-th (n is an integer greater than 1) routed line in the plurality of routing tracks generated in step 601 does not correspond to the preset track distance, the current layout of the plurality of routing tracks may refer to the layout of the plurality of routing tracks after the last adjustment.
In an alternative embodiment of the present application, adjusting the layout of the plurality of routing tracks may refer to: the relative positional relationship of the plurality of wiring tracks is adjusted, wherein the relative positional relationship includes the distance between the wiring tracks. In addition, in the process of adjusting the layout of the plurality of wiring tracks, the positions of the wires laid on the wiring tracks also need to be adjusted in accordance with the adjustment of the positions of the corresponding wiring tracks.
In an alternative embodiment of the present application, the chip wiring design software may be pre-configured with track layout modification commands. The computer device may automatically generate a track layout change command according to the width of the wire laid on the first routing track, or the computer device may receive a user-input track layout change command. After the track layout change command is identified by the chip wiring design software, the computer device can adjust the current layout of the plurality of wiring tracks according to the track layout change command.
After the current layout of the plurality of wiring tracks is adjusted, the computer equipment can also continue to route the wiring tracks which are not routed in the plurality of wiring tracks after the layout is adjusted through the chip wiring design software.
In other words, after the wires are distributed uniformly for each wiring track, the computer device may generate a chip wiring design file based on the wires distributed on the wiring tracks.
In the method for generating a chip wiring design file provided by this embodiment, after receiving a chip wiring design instruction, a plurality of wiring tracks parallel to each other are generated, where a distance between any two adjacent wiring tracks is a preset track distance, and then wiring is performed on each wiring track, where if it is detected that a width of a wired line does not correspond to the preset track distance in a process of wiring a first wiring track, a current layout of the plurality of wiring tracks is adjusted according to the width of the wired line, and wiring is continued on a wiring track that is not wired in the plurality of wiring tracks after the adjustment of the layout, and then, after wires are uniformly distributed on each wiring track, a chip wiring design file is generated based on a result of the wiring, because in a case that it is detected that the width of the wired line does not correspond to the preset track distance, the current layout of a plurality of wiring tracks generated before can be adjusted, based on the adjustment of the layout, the track distance between the first wiring track and the wiring track adjacent to the first wiring track can be changed, and the track distance is changed, so that the distance between the wire distributed on the first wiring track and the wire distributed on the wiring track adjacent to the first wiring track can be ensured to be not less than the requirement of the minimum manufacturing interval, thus, the wiring can be ensured to be simultaneously carried out on the first wiring track and the wiring track adjacent to the first wiring track, therefore, the problem that the wiring can not be carried out on certain wiring tracks can be avoided, the manufacturing area of chips can be prevented from being wasted, and the manufacturing cost of the chips can be reduced.
In the following, an exemplary technical process of "adjusting the current layout of a plurality of routing tracks according to the width of the routed wires" will be briefly described in the embodiments of the present application, and as shown in fig. 7, the technical process may include the following steps:
In an alternative embodiment of the present application, the computer device may query a track distance database according to the width of the laid line, wherein the track distance database stores therein a plurality of correspondences between line widths and track distances. The computer device may obtain the target track distance according to the query result.
It should be noted that the track distance corresponding to a certain line width may be determined according to the certain line width, the line width corresponding to the preset track distance, and the minimum manufacturing distance between lines in the chip.
The track distance corresponding to a certain line width can ensure that the distance between two distributed lines is greater than the minimum manufacturing distance under the condition that the line with the certain line width and the line with the line width corresponding to the preset track distance are respectively distributed on two adjacent wiring tracks.
Please refer to table 1, which is an example of a correspondence relationship between a line width and a track distance stored in a track distance database.
TABLE 1
| Line width | a | b | c | …… |
| Track distance | L1 | L2 | L3 | …… |
As shown in table 1, if the width of the laid line is a, the target track distance corresponding to the width of the laid line may be L1.
Among the plurality of wiring tracks after the layout is adjusted, the distance between the first wiring track and the adjacent second wiring track is the target track distance, and the distance between the adjacent wiring tracks except the first wiring track and the second wiring track is the same as the distance when the layout is not adjusted.
Referring to fig. 8, a schematic diagram of wiring on the wiring track 5 (in this case, the wiring track 5 is the first wiring track) and adjusting the current layout of the 6 generated wiring tracks according to the width of the wires laid on the wiring track 5 is shown.
As shown in fig. 8, the distance between the wiring rail 5 and the wiring rail 4 (one second wiring rail adjacent to the first wiring rail) is a target rail distance, the distance between the wiring rail 5 and the wiring rail 6 (another second wiring rail adjacent to the first wiring rail) is a target rail distance, and the distance between adjacent wiring rails other than the wiring rail 4, the wiring rail 5, and the wiring rail 6 is the same as the distance when the layout is not adjusted.
In the following, the present embodiment will be described with reference to two cases, in which a technical process of adjusting the current layout of a plurality of wiring tracks according to a target track distance by a computer device is described.
In the first case, the number of second wiring tracks adjacent to the first wiring track is 1.
In this case, the computer device may first adjust the current position of the second wiring track based on the target track distance, where the distance between the position-adjusted second wiring track and the first wiring track is the same as the target track distance.
For example, referring to fig. 9, if wiring is performed on the wiring track 1 (in this case, the wiring track 1 is the first wiring track), and the current layout of the generated 6 wiring tracks is adjusted according to the width of the wire laid on the wiring track 1, since the second wiring track adjacent to the wiring track 1 includes only the wiring tracks 2, the number of which is 1, the computer apparatus may first adjust the current position of the wiring track 2 based on the target track distance, where the distance between the wiring track 2 after position adjustment and the wiring track 1 is the same as the target track distance.
After the current position of the second wiring track is adjusted, the computer device may sequentially adjust the current position of each wiring track located on the first side. The first side is the side of the second wiring track far away from the first wiring track. After the position is adjusted, the distance between any adjacent two of the wiring tracks on the first side is the same as the distance when the layout is not adjusted.
For example, please refer to fig. 9 again, as shown in fig. 9, the side in the x direction is a first side, which is a side of the wiring track 2 away from the wiring track 1, wherein the wiring tracks 3 to 6 are all located on the first side, the computer can sequentially adjust the current positions of the wiring tracks 3 to 6, after the positions are adjusted, the distance between any two adjacent wiring tracks of the wiring tracks 3 to 6 is the same as the distance when the layout is not adjusted, that is, the distance between any two adjacent wiring tracks of the wiring tracks 3 to 6 is a preset track distance, and meanwhile, the distance between the wiring track 3 and the wiring track 2 is also the preset track distance.
In the second case, the number of second wiring tracks adjacent to the first wiring track is 2.
In this case, the computer device may first adjust the current position of the first wiring track based on the target track distance, where a distance between the position-adjusted first wiring track and one of the second wiring tracks is the same as the target track distance.
For example, referring to fig. 8, if wiring is performed on the wiring track 5 (in this case, the wiring track 5 is the first wiring track), and the current layout of the generated 6 wiring tracks is adjusted according to the width of the wire laid on the wiring track 5, since the second wiring track adjacent to the wiring track 5 includes the wiring tracks 4 and the wiring tracks 6, and the number thereof is 2, the computer device may first adjust the current position of the wiring track 5 based on the target track distance, where the distance between the wiring track 5 and the wiring track 4 after the position adjustment is the same as the target track distance.
After adjusting the current position of the first routing track, the computer device may then adjust the current position of another second routing track based on the target track distance, wherein the distance between the position-adjusted another second routing track and the first routing track is the same as the target track distance.
For example, with continued reference to fig. 8, after adjusting the current position of the routing track 5, the computer device may then adjust the current position of the routing track 6 based on the target track distance, wherein the distance between the position-adjusted routing track 6 and the routing track 5 is the same as the target track distance.
After adjusting the current position of the other second routing track, the computer device may sequentially adjust the position of each routing track located on the second side. The second side is a side of the other second wiring track far away from the first wiring track. After the position adjustment, the distance between any adjacent two of the wiring tracks on the second side is the same as the distance when the layout is not adjusted.
For example, please refer to fig. 8 again, one side of the y direction shown in fig. 8 is a second side, which is a side of the wiring track 6 away from the wiring track 5, the wiring track is not drawn on the second side in fig. 8, the computer may sequentially adjust the positions of the wiring tracks on the second side, after the positions are adjusted, the distance between any two adjacent wiring tracks on the second side is the same as the distance when the layout is not adjusted, that is, the distance between any two adjacent wiring tracks on the second side is the preset track distance.
Referring to fig. 10, a block diagram of an apparatus 1000 for generating a chip wiring design file according to an embodiment of the present application is shown, where the apparatus 1000 for generating a chip wiring design file can be configured in a computer device. As shown in fig. 10, the apparatus 1000 for generating a chip wiring design file may include: a first generation module 1001, a routing module 1002, and a second generation module 1003.
The first generating module 1001 is configured to generate a plurality of parallel wiring tracks after receiving a chip wiring design instruction, where a distance between any two adjacent wiring tracks is a preset track distance.
The wiring module 1002 is configured to perform wiring on each of the wiring tracks, wherein if it is detected that the width of the wired line does not correspond to the preset track distance in the process of wiring the first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the wired line, and the wiring tracks that are not wired in the plurality of wiring tracks after the layout is adjusted are continuously wired, wherein the first wiring track is any one of the plurality of wiring tracks.
The second generating module 1003 is configured to generate a chip wiring design file based on a wiring result after wires are distributed uniformly on each wiring track.
In an optional embodiment of the present application, the routing module 1002 is specifically configured to: acquiring a target track distance corresponding to the width of the distributed lines; adjusting the current layout of the plurality of wiring tracks according to the target track distance; among the plurality of wiring tracks after the layout is adjusted, the distance between the first wiring track and the adjacent second wiring track is the target track distance, and the distance between the adjacent wiring tracks except the first wiring track and the second wiring track is the same as the distance when the layout is not adjusted.
In an optional embodiment of the present application, the routing module 1002 is specifically configured to: if the number of the second wiring tracks adjacent to the first wiring track is 1, adjusting the current position of the second wiring track based on the target track distance, wherein the distance between the second wiring track and the first wiring track after position adjustment is the same as the target track distance; and sequentially adjusting the position of each wiring track on a first side, wherein the first side is the side of the second wiring track far away from the first wiring track, and after the position is adjusted, the distance between any two adjacent wiring tracks on the first side is the same as the distance when the layout is not adjusted.
In an optional embodiment of the present application, the routing module 1002 is specifically configured to: if the number of the second wiring tracks adjacent to the first wiring track is 2, adjusting the current position of the first wiring track based on the target track distance, wherein the distance between the first wiring track after position adjustment and one of the second wiring tracks is the same as the target track distance; adjusting the current position of another second wiring track based on the target track distance, wherein the distance between the another second wiring track after position adjustment and the first wiring track is the same as the target track distance; and sequentially adjusting the position of each wiring track on a second side, wherein the second side is one side of the other second wiring track far away from the first wiring track, and after the position is adjusted, the distance between any two adjacent wiring tracks on the second side is the same as the distance when the layout is not adjusted.
In an optional embodiment of the present application, the routing module 1002 is specifically configured to: inquiring a track distance database according to the width of the distributed line, wherein the track distance database stores a plurality of corresponding relations between the line width and the track distance; and obtaining the target track distance according to the query result.
In an optional embodiment of the present application, the preset track distance is a track distance corresponding to a single line width, and the routing module 1002 is specifically configured to: if it is detected that the width of the laid line is not the single-line width during the course of laying the first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the laid line.
In an alternative embodiment of the present application, the routing module 1002 is specifically configured to: receiving a track layout change command, the track layout change command being generated according to the width of the laid lines; and adjusting the current layout of the plurality of wiring tracks according to the track layout change command.
The device for generating the chip wiring design file provided by the embodiment of the application can realize the method embodiment, the realization principle and the technical effect are similar, and the details are not repeated.
For specific limitations of the device for generating the chip wiring design file, reference may be made to the above limitations on the method for generating the chip wiring design file, and details are not repeated here. The modules in the device for generating the chip wiring design file can be wholly or partially realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment of the present application, there is provided a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the following steps when executing the computer program:
after a chip wiring design instruction is received, generating a plurality of wiring tracks which are parallel to each other, wherein the distance between any two adjacent wiring tracks is a preset track distance; wiring on each wiring track, wherein if the width of the wired line is detected not to correspond to the preset track distance in the process of wiring a first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the wired line, and the wiring tracks which are not wired in the plurality of wiring tracks after the layout is adjusted are continuously wired, wherein the first wiring track is any one of the plurality of wiring tracks; and after the wires are uniformly distributed on each wiring track, generating a chip wiring design file based on the wiring result.
In one embodiment of the application, the processor when executing the computer program further performs the steps of: acquiring a target track distance corresponding to the width of the distributed lines; adjusting the current layout of the plurality of wiring tracks according to the target track distance; among the plurality of wiring tracks after the layout is adjusted, the distance between the first wiring track and the adjacent second wiring track is the target track distance, and the distance between the adjacent wiring tracks except the first wiring track and the second wiring track is the same as the distance when the layout is not adjusted.
In one embodiment of the application, the processor when executing the computer program further performs the steps of: if the number of the second wiring tracks adjacent to the first wiring track is 1, adjusting the current position of the second wiring track based on the target track distance, wherein the distance between the second wiring track and the first wiring track after position adjustment is the same as the target track distance; and sequentially adjusting the position of each wiring track on a first side, wherein the first side is the side of the second wiring track far away from the first wiring track, and after the position is adjusted, the distance between any two adjacent wiring tracks on the first side is the same as the distance when the layout is not adjusted.
In one embodiment of the application, the processor when executing the computer program further performs the steps of: if the number of the second wiring tracks adjacent to the first wiring track is 2, adjusting the current position of the first wiring track based on the target track distance, wherein the distance between the first wiring track after position adjustment and one of the second wiring tracks is the same as the target track distance; adjusting the current position of another second wiring track based on the target track distance, wherein the distance between the another second wiring track after position adjustment and the first wiring track is the same as the target track distance; and sequentially adjusting the position of each wiring track on a second side, wherein the second side is one side of the other second wiring track far away from the first wiring track, and after the position is adjusted, the distance between any two adjacent wiring tracks on the second side is the same as the distance when the layout is not adjusted.
In one embodiment of the application, the processor when executing the computer program further performs the steps of: inquiring a track distance database according to the width of the distributed line, wherein the track distance database stores a plurality of corresponding relations between the line width and the track distance; and obtaining the target track distance according to the query result.
In an embodiment of the application, the preset track distance is a track distance corresponding to a single line width, and the processor executes the computer program to further implement the following steps: if it is detected that the width of the laid line is not the single-line width during the course of laying the first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the laid line.
In one embodiment of the application, the processor when executing the computer program further performs the steps of: receiving a track layout change command, the track layout change command being generated according to the width of the laid lines; and adjusting the current layout of the plurality of wiring tracks according to the track layout change command.
The implementation principle and technical effect of the computer device provided by the embodiment of the present application are similar to those of the method embodiment described above, and are not described herein again.
In an embodiment of the application, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of:
after a chip wiring design instruction is received, generating a plurality of wiring tracks which are parallel to each other, wherein the distance between any two adjacent wiring tracks is a preset track distance; wiring on each wiring track, wherein if the width of the wired line is detected not to correspond to the preset track distance in the process of wiring a first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the wired line, and the wiring tracks which are not wired in the plurality of wiring tracks after the layout is adjusted are continuously wired, wherein the first wiring track is any one of the plurality of wiring tracks; and after the wires are uniformly distributed on each wiring track, generating a chip wiring design file based on the wiring result.
In one embodiment of the application, the computer program when executed by the processor further performs the steps of: acquiring a target track distance corresponding to the width of the distributed lines; adjusting the current layout of the plurality of wiring tracks according to the target track distance; among the plurality of wiring tracks after the layout is adjusted, the distance between the first wiring track and the adjacent second wiring track is the target track distance, and the distance between the adjacent wiring tracks except the first wiring track and the second wiring track is the same as the distance when the layout is not adjusted.
In one embodiment of the application, the computer program when executed by the processor further performs the steps of: if the number of the second wiring tracks adjacent to the first wiring track is 1, adjusting the current position of the second wiring track based on the target track distance, wherein the distance between the second wiring track and the first wiring track after position adjustment is the same as the target track distance; and sequentially adjusting the position of each wiring track on a first side, wherein the first side is the side of the second wiring track far away from the first wiring track, and after the position is adjusted, the distance between any two adjacent wiring tracks on the first side is the same as the distance when the layout is not adjusted.
In one embodiment of the application, the computer program when executed by the processor further performs the steps of: if the number of the second wiring tracks adjacent to the first wiring track is 2, adjusting the current position of the first wiring track based on the target track distance, wherein the distance between the first wiring track after position adjustment and one of the second wiring tracks is the same as the target track distance; adjusting the current position of another second wiring track based on the target track distance, wherein the distance between the another second wiring track after position adjustment and the first wiring track is the same as the target track distance; and sequentially adjusting the position of each wiring track on a second side, wherein the second side is one side of the other second wiring track far away from the first wiring track, and after the position is adjusted, the distance between any two adjacent wiring tracks on the second side is the same as the distance when the layout is not adjusted.
In one embodiment of the application, the computer program when executed by the processor further performs the steps of: inquiring a track distance database according to the width of the distributed line, wherein the track distance database stores a plurality of corresponding relations between the line width and the track distance; and obtaining the target track distance according to the query result.
In an embodiment of the application, the predetermined track distance is a track distance corresponding to a single line width, and the computer program when executed by the processor further performs the steps of: if it is detected that the width of the laid line is not the single-line width during the course of laying the first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the laid line.
In one embodiment of the application, the computer program when executed by the processor further performs the steps of: receiving a track layout change command, the track layout change command being generated according to the width of the laid lines; and adjusting the current layout of the plurality of wiring tracks according to the track layout change command.
The implementation principle and technical effect of the computer-readable storage medium provided by this embodiment are similar to those of the above-described method embodiment, and are not described herein again.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in M forms, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), synchronous Link (SyMchliMk) DRAM (SLDRAM), RaMbus (RaMbus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for generating a chip wiring design file is characterized by comprising the following steps:
after a chip wiring design instruction is received, generating a plurality of wiring tracks which are parallel to each other, wherein the distance between any two adjacent wiring tracks is a preset track distance;
wiring on each wiring track, wherein if the width of the wired line is detected not to correspond to the preset track distance in the process of wiring a first wiring track, the current layout of the plurality of wiring tracks is adjusted according to the width of the wired line, and the wiring tracks which are not wired in the plurality of wiring tracks after the layout is adjusted are continuously wired, wherein the first wiring track is any one of the plurality of wiring tracks;
and after the wires are uniformly distributed on each wiring track, generating a chip wiring design file based on the wiring result.
2. The method of claim 1, wherein said adjusting a current layout of said plurality of routing tracks according to a width of said routed wires comprises:
acquiring a target track distance corresponding to the width of the distributed lines;
adjusting the current layout of the plurality of wiring tracks according to the target track distance;
and in the plurality of wiring tracks after the layout is adjusted, the distance between the first wiring track and the adjacent second wiring track is the target track distance, and the distance between the adjacent wiring tracks except the first wiring track and the second wiring track is the same as the distance when the layout is not adjusted.
3. The method of claim 2, wherein said adjusting the current layout of the plurality of routing tracks based on the target track distance comprises:
if the number of the second wiring tracks adjacent to the first wiring track is 1, adjusting the current position of the second wiring track based on the target track distance, wherein the distance between the second wiring track and the first wiring track after position adjustment is the same as the target track distance;
and sequentially adjusting the positions of the wiring tracks on a first side, wherein the first side is the side of the second wiring track far away from the first wiring track, and after the positions are adjusted, the distance between any two adjacent wiring tracks on the first side is the same as the distance when the layout is not adjusted.
4. The method of claim 2, wherein said adjusting the current layout of the plurality of routing tracks based on the target track distance comprises:
if the number of the second wiring tracks adjacent to the first wiring track is 2, adjusting the current position of the first wiring track based on the target track distance, wherein the distance between the first wiring track after position adjustment and one of the second wiring tracks is the same as the target track distance;
adjusting the current position of another second wiring track based on the target track distance, wherein the distance between the position-adjusted another second wiring track and the first wiring track is the same as the target track distance;
and sequentially adjusting the positions of the wiring tracks on a second side, wherein the second side is one side of the other second wiring track far away from the first wiring track, and after the positions are adjusted, the distance between any two adjacent wiring tracks on the second side is the same as the distance when the layout is not adjusted.
5. The method of claim 2, wherein said obtaining a target track distance corresponding to a width of the laid line comprises:
inquiring a track distance database according to the width of the distributed line, wherein a plurality of corresponding relations between the line width and the track distance are stored in the track distance database;
and obtaining the target track distance according to the query result.
6. The method of claim 1, wherein the predetermined track distance is a track distance corresponding to a single line width, and if it is detected that the width of the laid line does not correspond to the predetermined track distance during the process of laying the first routing track, the adjusting the current layout of the plurality of routing tracks according to the width of the laid line comprises:
and if the width of the distributed line is detected not to be the single-line width in the process of distributing the first distribution track, adjusting the current layout of the plurality of distribution tracks according to the width of the distributed line.
7. The method of claim 1, wherein said adjusting a current layout of said plurality of routing tracks according to a width of said routed wires comprises:
receiving a track layout change command, wherein the track layout change command is generated according to the width of the distributed lines;
and adjusting the current layout of the plurality of wiring tracks according to the track layout change command.
8. An apparatus for generating a chip wiring design file, the apparatus comprising:
the first generation module is used for generating a plurality of parallel wiring tracks after receiving a chip wiring design instruction, wherein the distance between any two adjacent wiring tracks is a preset track distance;
a wiring module, configured to perform wiring on each of the wiring tracks based on a wiring command, wherein if it is detected that a width of a wired line does not correspond to the preset track distance in a process of wiring a first wiring track, a current layout of the plurality of wiring tracks is adjusted according to the width of the wired line, and the wiring track that is not wired in the plurality of wiring tracks after the layout is adjusted is continuously wired, wherein the first wiring track is any one of the plurality of wiring tracks;
and the second generation module is used for generating a chip wiring design file based on a wiring result after wires are uniformly distributed on each wiring track.
9. A computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, implements the method of generating a chip wiring design file according to any one of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the method of generating a chip wiring design file according to any one of claims 1 to 7.
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| CN202011043926.0A CN112115674A (en) | 2020-09-28 | 2020-09-28 | Method, device and equipment for generating chip wiring design file and storage medium |
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| CN116629193A (en) * | 2023-05-30 | 2023-08-22 | 深圳鸿芯微纳技术有限公司 | Wiring method, device, equipment and storage medium for integrated circuit |
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Application publication date: 20201222 |