CN112104355A - Configurable bias circuit of source buffer - Google Patents

Abstract

The invention discloses a source buffer configurable bias circuit which comprises a bias circuit and a current digital-to-analog converter (IDAC), wherein the input end of the bias circuit is connected with the output end of the IDAC. The source buffer provided by the invention can be configured with the bias circuit, so that the working currents in different areas can be flexibly adjusted, the consistency of circuit channels of the buffer is improved, and the display effect is further improved; the working current of different areas can be dynamically adjusted according to the characteristics of a display picture, such as dynamic or static images, so that the working current and the power consumption of a chip can be saved while the display performance is improved; the designed current digital-to-analog converter IDAC with multi-path current output can reuse main devices in the same circuit, the area of a chip can be saved through high-low segmentation, and the number of channels of output current can be flexibly configured.

Description

A source buffer configurable bias circuit

technical field

The present invention relates to the technical field of source buffer circuits, in particular to a source buffer configurable bias circuit.

Background technique

In the display driver chip, one of the very important functional modules is the source driver module, as shown in Figure 3 and Figure 4, its driving part is also called the source buffer circuit, which is implemented with an analog circuit and is used to drive the screen. source line. Depending on the display resolution, the number of channels driven by the source will vary, but the number is generally on the order of hundreds to thousands.

According to the requirements of the output driving voltage range of the buffer, the source buffer circuit is basically implemented with devices whose working voltage is above 5V. There are some problems in this implementation method: the first one is the device with 5V or above. Poor matching performance between channels will lead to poor consistency between channels. One of the solutions is to increase the area of the device. However, due to the large number of channels, the area of the chip will be significantly increased, thereby increasing the cost of the chip. The second is that the number of buffer channels is hundreds to thousands. The distance between the channels at both ends of the chip is very long. The gradient caused by the chip production will seriously affect the consistency between channels, which will seriously affect the display screen. display effect.

How to improve the consistency between buffer circuits without significantly increasing the chip area, thereby improving the display effect of the display screen has become an urgent problem for those skilled in the art. Based on this, a source buffer configurable source buffer is proposed. bias circuit.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a source buffer configurable bias circuit, which can flexibly adjust the working current in different regions, improve the consistency of the buffer circuit channels, thereby improve the display effect, and save the working current and power consumption of the chip , the area of the chip can be saved, and the number of channels of the output current can be flexibly configured to solve the problem of how to improve the consistency between the buffer circuits and improve the display effect of the display screen without significantly increasing the chip area. The problem.

In order to achieve the above purpose, the present invention provides the following technical solutions: a source buffer configurable bias circuit, including a bias circuit and a current digital-to-analog converter IDAC, the input end of the bias circuit and the output of the current digital-to-analog converter IDAC The terminals are connected to each other; the bias circuit is connected with several, and the several bias circuits are respectively recorded as bias circuit A, bias circuit B-bias circuit N, and the current digital-to-analog converter IDAC is connected with several, respectively Denoted as current digital-to-analog converter IDACa, current digital-to-analog converter IDACb-current digital-to-analog converter IDACn, the input end of bias circuit A is connected to the output end of current digital-to-analog converter IDACa, and the input end of bias circuit B is connected to The output end of the current digital-to-analog converter IDACb is connected, and so on, the input end of the bias circuit N is connected to the output end of the current digital-to-analog converter IDACn.

Preferably, the current digital-to-analog converter IDAC includes MOS transistors PM1-MOS transistor PM26, switches K1-switch K8, the sources of the MOS transistors PM1-MOS transistor PM13 are connected to the high level VDD, and the gates of the MOS transistor PM1-MOS transistor PM13 are connected to the high level VDD. Turn on and connect in turn, the drain of MOS tube PM1 is connected to the gate and then connected to the source of MOS tube PM14, the drain of MOS tube PM2 is connected to the source of MOS tube PM15, and the drain of MOS tube PM3 is connected to On the source of the MOS tube PM16, the drain of the MOS tube PM4 is connected to the source of the MOS tube PM17, the drain of the MOS tube PM5 is connected to the source of the MOS tube PM18, and the drain of the MOS tube PM6 is connected to the MOS tube On the source of PM19, the drain of MOS transistor PM7 is connected to the source of MOS transistor PM20, the drain of MOS transistor PM8 is connected to the source of MOS transistor PM21, and the drain of MOS transistor PM9 is connected to the source of MOS transistor PM22. On the source, the drain of the MOS tube PM10 is connected to the source of the MOS tube PM23, the drain of the MOS tube PM11 is connected to the source of the MOS tube PM24, and the drain of the MOS tube PM12 is connected to the source of the MOS tube PM25 The drain of the MOS tube PM13 is connected to the source of the MOS tube PM26; the gates of the MOS tube PM14-MOS tube PM26 are turned on and connected in turn, and the drain of the MOS tube PM14 is connected to the gate and then connected to the IBP Input terminal; the drain of the MOS transistor PM15 is connected to the input terminal of the switch K1, the drain of the MOS transistor PM16 is connected to the input terminal of the switch K2, and the drain of the MOS transistor PM17 is connected to the input terminal of the switch K3 , the drain of the MOS transistor PM18 is connected to the input end of the switch K4, the drain of the MOS transistor PM23 is connected to the input end of the switch K5, the drain of the MOS transistor PM24 is connected to the input end of the switch K6, so The drain of the MOS transistor PM25 is connected to the input end of the switch K7, the drain of the MOS transistor PM26 is connected to the input end of the switch K8, the drain of the MOS transistor PM20, the switch K1, the switch K2, the switch K7 and the switch The output terminal of K8 is connected to the IBPO2 terminal for output; the drain of the MOS tube PM21, the output terminals of switch K3, switch K4, switch K5 and switch K6 are connected to the IBPO1 terminal for output.

Preferably, the current digital-to-analog converter IDAC further includes a bias MOS transistor PM27-bias MOS transistor PM30, the drain of the bias MOS transistor PM27 is connected to the drain of the MOS transistor PM19, and the drain of the bias MOS transistor PM28 connected to the drain of the MOS tube PM22; the gate of the bias MOS tube PM27 is connected to the gate of the bias MOS tube PM29, the source of the bias MOS tube PM27 is connected to the drain of the bias MOS tube PM28, and the bias MOS tube PM27 is connected to the drain of the bias MOS tube PM28. The source of the MOS tube PM29 is connected to the drain of the bias MOS tube PM30, the gate of the bias MOS tube PM28 is connected to the gate of the bias MOS tube PM30, and the source of the bias MOS tube PM28 is connected to the bias MOS tube The sources of PM30 are all grounded to VSS.

Preferably, the bias current of the bias circuit comes from the current digital-to-analog converter IDAC2, the magnitude of the output current is configured by a digital signal, and the bit width of the digital control signal is selected according to the adjustment range and adjustment precision.

Preferably, the implementation method of the current digital-to-analog converter IDACa-current digital-to-analog converter IDACn multiplexes the main devices in the same circuit to realize multiple configurable current outputs.

Compared with the prior art, the beneficial effects of the present invention are: the source buffer configurable bias circuit proposed by the present invention has the following advantages:

1. According to the change of the chip production process, the working current in different areas can be flexibly adjusted to improve the consistency of the buffer circuit channels, thereby improving the display effect.

2. According to the characteristics of the display screen, such as dynamic or static images, the working current of different areas can be dynamically adjusted to improve the display performance and save the working current and power consumption of the chip.

3. The designed current digital-to-analog converter IDAC with multi-channel current output can reuse the main devices in the same circuit. The area of the chip can be saved by segmenting high and low bits, and the number of output current channels can also be flexibly configured.

Description of drawings

1 is a schematic structural diagram of a configurable bias circuit of the present invention;

2 is a schematic structural diagram of a current-capable digital-to-analog conversion circuit of the present invention;

3 is a schematic diagram of a prior art circuit structure;

FIG. 4 is a schematic structural diagram of a conventional driver chip.

In the figure: 1. Bias circuit; 2. Current digital-to-analog converter IDAC.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Referring to Figure 1, a source buffer configurable bias circuit includes a bias circuit 1 and a current digital-to-analog converter IDAC2. The input end of the bias circuit 1 is connected to the output end of the current digital-to-analog converter IDAC2; the bias There are several circuits connected to the circuit 1, and the several bias circuits 1 are respectively recorded as current digital-to-analog converter IDACa, current digital-to-analog converter IDACb-current digital-to-analog converter IDACn, and circuit wiring and components of several current digital-to-analog converters IDAC2. The size and model are the same, the input end of bias circuit A is connected to the output end of the current digital-to-analog converter IDACa, the input end of the bias circuit B is connected to the output end of the current digital-to-analog converter IDACb, and so on, the bias circuit N The input end is connected to the output end of the current digital-to-analog converter IDACn.

Please refer to Figure 2, the current digital-to-analog converter IDAC2 includes MOS transistor PM1-MOS transistor PM26, switch K1-switch K8, the source of MOS transistor PM1-MOS transistor PM13 is connected to high-level VDD, and the MOS transistor PM1-MOS transistor PM13 is connected to the source. The gates are turned on and connected in turn, the drain of the MOS tube PM1 is connected to the gate and then connected to the source of the MOS tube PM14, the drain of the MOS tube PM2 is connected to the source of the MOS tube PM15, and the drain of the MOS tube PM3 It is connected to the source of MOS tube PM16, the drain of MOS tube PM4 is connected to the source of MOS tube PM17, the drain of MOS tube PM5 is connected to the source of MOS tube PM18, and the drain of MOS tube PM6 is connected to On the source of the MOS tube PM19, the drain of the MOS tube PM7 is connected to the source of the MOS tube PM20, the drain of the MOS tube PM8 is connected to the source of the MOS tube PM21, and the drain of the MOS tube PM9 is connected to the MOS tube On the source of PM22, the drain of MOS tube PM10 is connected to the source of MOS tube PM23, the drain of MOS tube PM11 is connected to the source of MOS tube PM24, and the drain of MOS tube PM12 is connected to the source of MOS tube PM25. On the source; the drain of the MOS transistor PM13 is connected to the source of the MOS transistor PM26.

Please refer to FIG. 2 , the gates of the MOS transistor PM14 to the MOS transistor PM26 are turned on and connected in turn, the drain of the MOS transistor PM14 is connected to the gate and then connected to the input end of the IBP; the drain of the MOS transistor PM15 is connected to the switch K1 The drain of the MOS transistor PM16 is connected to the input terminal of the switch K2, the drain of the MOS transistor PM17 is connected to the input terminal of the switch K3, and the drain of the MOS transistor PM18 is connected to the input terminal of the switch K4 terminal, the drain of the MOS transistor PM23 is connected to the input terminal of the switch K5, the drain of the MOS transistor PM24 is connected to the input terminal of the switch K6, the drain of the MOS transistor PM25 is connected to the input terminal of the switch K7, The drain of the MOS transistor PM26 is connected to the input end of the switch K8, the drain of the MOS transistor PM20, the output ends of the switch K1, the switch K2, the switch K7 and the switch K8 are connected to the IBPO2 terminal for output; The drain, the output terminals of the switch K3, the switch K4, the switch K5 and the switch K6 are connected and then connected to the output of the IBPO1 terminal.

Referring to FIG. 2, the current digital-to-analog converter IDAC2 further includes a bias MOS transistor PM27-bias MOS transistor PM30, the drain of the bias MOS transistor PM27 is connected to the drain of the MOS transistor PM19, and the bias MOS transistor PM28 has a drain The drain is connected to the drain of the MOS tube PM22; the gate of the bias MOS tube PM27 is connected to the gate of the bias MOS tube PM29, and the source of the bias MOS tube PM27 is connected to the drain of the bias MOS tube PM28 , the source of the bias MOS tube PM29 is connected to the drain of the bias MOS tube PM30, the gate of the bias MOS tube PM28 is connected to the gate of the bias MOS tube PM30, the source of the bias MOS tube PM28 and the bias The sources of the MOS transistor PM30 are all grounded to VSS.

The source buffer can be configured with a bias circuit, and several bias circuits 1 are respectively connected to the source buffer. As shown in Fig. 1, each source buffer is denoted as S1, S2-Sn, from the source buffer S1 to the source buffer. Between the channels of the Sn, each a certain number of channels are relatively uniformly inserted into the bias circuit 1, and the number of bias circuits 1 can be increased or decreased according to the number of channels, and each bias circuit 1 is responsible for the adjacent A number of source buffers provide bias circuit 1 .

The bias current of the bias circuit 1 comes from the current digital-to-analog converter IDAC2. The magnitude of the output current is configured by the digital signal, and the bit width of the digital control signal can be selected according to the adjustment range and adjustment accuracy; by adopting the above scheme, the bias circuit A bias current of 1 can be allocated configuration size by region:

First, it can adapt to the change of the gradient distribution in the chip production process. For example, from the source buffer S1 to the source buffer Sn, due to the influence of the gradient, the current of each channel decreases in turn, then the current digital-to-analog converter IDAC2 can be configured. The current output from the current digital-to-analog converter IDACa-current digital-to-analog converter IDACn increases sequentially, so that the variation of the channel current can be compensated, thereby improving the consistency between the channels.

Second, the operating current of different regions or the whole can be dynamically adjusted according to the characteristics of the screen display, such as dynamic or static images, so as to improve the display performance and save the operating current and power consumption of the chip.

Please refer to Figure 2. The implementation method of the current digital-to-analog converter IDACa-current digital-to-analog converter IDACn can reuse the main circuit to realize multiple configurable current outputs, which sets two configurable current outputs, namely IBPO1 And IBPO2, each configurable current is divided into two sections by high and status, the two sections are high 2 bits and low 2 bits respectively, high 2 bits and low 2 bits adjust the weight through MN1 and MN2, the high and low bits are divided into The number of segments and the channels of output current can be flexibly configured according to actual needs.

To sum up, the source buffer configurable bias circuit proposed by the present invention has the following advantages:

1. According to the change of the chip production process, the working current in different areas can be flexibly adjusted to improve the consistency of the buffer circuit channels, thereby improving the display effect.

2. According to the characteristics of the display screen, such as dynamic or static images, the working current of different areas can be dynamically adjusted to improve the display performance and save the working current and power consumption of the chip.

3. The designed current digital-to-analog converter IDAC2 with multi-channel current output can reuse the main devices in the same circuit. The area of the chip can be saved by segmenting high and low bits, and the number of output current channels can also be flexibly configured.

The above description is only a preferred embodiment of the present invention, but the protection scope of the present invention is not limited to this. The equivalent replacement or change of the inventive concept thereof shall be included within the protection scope of the present invention.

Claims (5)

1. A source buffer configurable bias circuit, characterized by comprising a bias circuit (1) and a current digital-to-analog converter IDAC (2), an input end of the bias circuit (1) and a current digital-to-analog converter The output ends of the IDAC (2) are connected; the bias circuit (1) is connected with several, and the several bias circuits (1) are respectively denoted as bias circuit A, bias circuit B-bias circuit N, the There are several current digital-to-analog converters IDAC (2) connected, which are respectively recorded as current digital-to-analog converter IDACa, current digital-to-analog converter IDACb-current digital-to-analog converter IDACn, the input end of bias circuit A and current digital-to-analog converter The output terminal of the bias circuit B is connected to the output terminal of the current digital-to-analog converter IDACb, and so on, the input terminal of the bias circuit N is connected to the output terminal of the current digital-to-analog converter IDACn. 2. A source buffer configurable bias circuit according to claim 1, wherein the current digital-to-analog converter IDAC (2) comprises a MOS transistor PM1-MOS transistor PM26, a switch K1-switch K8, The sources of the MOS transistor PM1-MOS transistor PM13 are connected to the high level VDD, the gates of the MOS transistor PM1-MOS transistor PM13 are turned on and connected in turn, and the drain of the MOS transistor PM1 is connected to the gate and then connected to the source of the MOS transistor PM14 On the top, the drain of MOS tube PM2 is connected to the source of MOS tube PM15, the drain of MOS tube PM3 is connected to the source of MOS tube PM16, the drain of MOS tube PM4 is connected to the source of MOS tube PM17, The drain of the MOS tube PM5 is connected to the source of the MOS tube PM18, the drain of the MOS tube PM6 is connected to the source of the MOS tube PM19, the drain of the MOS tube PM7 is connected to the source of the MOS tube PM20, and the MOS tube The drain of PM8 is connected to the source of MOS tube PM21, the drain of MOS tube PM9 is connected to the source of MOS tube PM22, the drain of MOS tube PM10 is connected to the source of MOS tube PM23, and the drain of MOS tube PM11 is connected to the source of MOS tube PM23. The drain is connected to the source of the MOS tube PM24, the drain of the MOS tube PM12 is connected to the source of the MOS tube PM25; the drain of the MOS tube PM13 is connected to the source of the MOS tube PM26; the MOS tube PM14- The gate of the MOS tube PM26 is turned on and connected in turn, and the drain of the MOS tube PM14 is connected to the gate and then connected to the input end of the IBP; the drain of the MOS tube PM15 is connected to the input end of the switch K1, and the MOS tube PM16 The drain of the MOS transistor PM17 is connected to the input terminal of the switch K2, the drain of the MOS transistor PM17 is connected to the input terminal of the switch K3, the drain of the MOS transistor PM18 is connected to the input terminal of the switch K4, and the drain of the MOS transistor PM23 is connected to the input terminal of the switch K4. The pole is connected to the input terminal of the switch K5, the drain of the MOS transistor PM24 is connected to the input terminal of the switch K6, the drain of the MOS transistor PM25 is connected to the input terminal of the switch K7, and the drain of the MOS transistor PM26 is connected to the input terminal of the switch K7. To the input end of the switch K8, the drain of the MOS tube PM20, the output end of the switch K1, the switch K2, the switch K7 and the switch K8 are connected to the IBPO2 terminal for output; the drain of the MOS tube PM21, the switch K3, the switch K4, The output terminals of the switch K5 and the switch K6 are connected to the IBPO1 terminal output after being connected. 3. The source buffer configurable bias circuit according to claim 2, wherein the current digital-to-analog converter IDAC (2) further comprises a bias MOS transistor PM27-bias MOS transistor PM30, so The drain of the bias MOS transistor PM27 is connected to the drain of the MOS transistor PM19, and the drain of the bias MOS transistor PM28 is connected to the drain of the MOS transistor PM22; the gate of the bias MOS transistor PM27 is connected to the bias MOS transistor PM27. The gate of PM29 is connected to the gate of the bias MOS tube PM27, the source of the bias MOS tube PM27 is connected to the drain of the bias MOS tube PM28, the source of the bias MOS tube PM29 is connected to the drain of the bias MOS tube PM30, and the The gate is connected to the gate of the bias MOS transistor PM30, and the source of the bias MOS transistor PM28 and the source of the bias MOS transistor PM30 are both grounded to VSS. 4. The source buffer configurable bias circuit according to claim 1, wherein the bias current of the bias circuit (1) comes from the current digital-to-analog converter IDAC2, and the output is configured by a digital signal The size of the current, the bit width of the digital control signal is selected according to the adjustment range and adjustment accuracy. 5. The source buffer configurable bias circuit according to claim 1, wherein the implementation method of the current digital-to-analog converter IDACa-current digital-to-analog converter IDACn multiplexes main devices in the same circuit , to achieve multi-channel configurable current output.

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