CN112103332B - A kind of static random access memory and its manufacturing method - Google Patents

Abstract

The invention provides a static random access memory and a manufacturing method thereof, comprising the following steps: the semiconductor device comprises a substrate, wherein the substrate comprises a plurality of isolation structures, and active regions distributed at intervals are isolated in the substrate by the isolation structures; a first gate structure located on the active region; the second grid structure is positioned on the isolation structure, and a projection area of the second grid structure in the substrate direction is positioned in the isolation structure; the doped region is positioned in the substrate of the active region and positioned at two sides of the first gate structure; the interlayer dielectric layer is positioned on the substrate and covers the first grid structure and the second grid structure; and the contact electrode is positioned in the interlayer dielectric layer, and the bottom of the contact electrode is connected with part of the second grid structure and part of the isolation structure. The static random access memory provided by the invention can avoid electric leakage and improve the yield of products.

Description

A kind of static random access memory and its manufacturing method

technical field

The present invention relates to the technical field of storage, and in particular, to a static random access memory and a manufacturing method thereof.

Background technique

Random access memory elements can be mainly divided into dynamic random access memory (Dynamic Random Access Memory, DRAM) and static random access memory (SRAM). The advantages of the SRAM are fast operation and low power consumption. Compared with the dynamic random access memory, the static random access memory does not require periodic charging and updating, and is simpler in design and manufacture. Therefore, SRAM is widely used in information electronic products.

For a low-power/low-voltage SRAM, a SRAM with six transistors (6T) as a memory cell has high stability. The 6T SRAM is, for example, a full complementary metal-oxide-semiconductor transistor static random access memory (Full CMOS SRAM). Two pull-up transistors are usually connected, but when two pull-up transistors are connected, it may cause leakage of the pull-up transistor.

SUMMARY OF THE INVENTION

In view of the above-mentioned defects of the prior art, the present invention provides a static random access memory and a manufacturing method thereof, so as to improve the leakage of the pull-up transistor and improve the yield of the static random access memory.

In order to achieve the above object and other objects, the present invention proposes a static random access memory, comprising:

a substrate, the substrate includes a plurality of isolation structures, and the isolation structures isolate active regions distributed at intervals in the substrate;

a first gate structure, located on the active region;

a second gate structure is located on the isolation structure, and a projection area of the second gate structure in the direction of the substrate is located in the isolation structure;

a doped region located in the substrate in the active region and located on both sides of the first gate structure;

an interlayer dielectric layer, located on the substrate, covering the first gate structure and the second gate structure;

a contact electrode, located in the interlayer dielectric layer, the bottom of the contact electrode is connected to part of the second gate structure and part of the isolation structure;

Wherein, the length of the connection between the contact electrode and the isolation structure is greater than or equal to the length of the doped region.

Further, a source electrode and a drain electrode are also included, and the source electrode and the drain electrode are located in the active region and located on both sides of the first gate structure.

Further, a silicide layer is also included, and the silicide layer is located on the top of the source electrode, the drain electrode, the first gate structure and the second gate structure, respectively.

Further, the contact electrode is also connected to the source electrode or the drain electrode.

Further, both sides of the first gate structure and the second gate structure further include spacer structures, and the spacer structures are located on the doped regions.

Further, the present invention also provides a method for manufacturing a static random access memory, comprising:

A substrate is provided, the substrate includes a plurality of isolation structures, the isolation structures isolate spaced active regions in the substrate;

forming a first gate structure and a second gate structure on the substrate; wherein the first gate structure is located on the active region, the second gate structure is located on the isolation structure, and the projection area of the second gate structure in the direction of the substrate is located in the isolation structure;

forming doped regions in the substrate of the active region and located on both sides of the first gate structure;

forming spacer structures on both sides of the first gate structure and the second gate structure;

forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the first gate structure and the second gate structure;

A contact hole is formed in the interlayer dielectric layer, and the contact hole exposes a part of the top of the second gate structure and a part of the top of the isolation structure, wherein the second gate structure is close to the One side of the first gate structure also has residual spacers;

A contact electrode is formed in the contact hole, and the bottom of the contact electrode is connected to part of the second gate structure and part of the isolation structure; and the length of the connection between the contact electrode and the isolation structure is greater than or equal to the the length of the doped region.

Further, the step of forming the side wall structure includes:

forming a nitride layer on the substrate, the nitride layer covering the first gate structure and the second gate structure;

removing part of the nitride layer on top of the first gate structure and the second gate structure by dry etching to form a spacer structure;

Wherein, after the dry etching, the nitride layer remains on the substrate, the top of the first gate structure and the top of the second gate structure.

Further, before forming the interlayer dielectric layer, a source electrode and a drain electrode are also formed on both sides of the first gate structure, and the step of forming the source electrode and the drain electrode includes:

ion doping the substrate on both sides of the first gate structure to form the source and the drain in the substrate;

Wherein, the source electrode or the drain electrode is close to the second gate structure.

Further, a silicide layer is further formed on top of the first gate structure, the second gate structure, the source electrode and the drain electrode, and the step of forming the silicide layer includes:

A metal layer is formed on top of the first gate structure, the second gate structure, the source electrode and the drain electrode;

performing a first annealing to make metal atoms in the metal layer react with silicon atoms to form an intermediate silicide layer;

performing a second anneal to convert the intermediate silicide layer to the silicide layer;

Wherein, the temperature of the second annealing is greater than the temperature of the first annealing.

Further, the step of forming the doped region includes:

performing ion doping on both sides of the first gate structure to form a first doping region;

performing ion doping on the first doping region to form a second doping region in the first doping region;

Wherein, the ion doping type of the first doping region is different from the ion doping type of the second doping region.

In summary, the present invention provides a static random access memory and a method for manufacturing the same. The first gate structure is formed on the active region, the second gate structure is formed on the isolation structure, and the second gate structure is formed on the isolation structure. The projection area of the pole structure in the direction of the substrate is completely located in the isolation structure, so there are isolation structures on both sides of the second gate structure, and the length of the isolation structure is greater than or equal to the length of the doping area, so it cannot be used in the second gate structure. Doping regions are formed on both sides of the structure, so when the contact holes are formed, the structure of the doping regions will not be destroyed, and at the same time, there are residual sidewalls on the side of the second gate structure close to the first gate structure, The remaining sidewall spacers are located on the isolation structure, and the remaining sidewall spacers can protect the second gate structure; therefore, when the contact hole is formed, the leakage phenomenon of the second gate structure will not be caused, and when the contact electrode is formed in the contact hole, it can be Improve the yield of static random access memory.

Description of drawings

Figure 1: The circuit diagram of the static random access memory in this embodiment.

Figure 2: A partial layout of the SRAM in this embodiment.

FIG. 3 is a flowchart of the manufacturing method of the static random access memory in this embodiment.

Fig. 4 is a schematic structural diagram corresponding to step S1.

FIG. 5: Schematic diagram of the structure of forming the polysilicon layer.

Fig. 6 is a schematic structural diagram corresponding to step S2.

Fig. 7 is a schematic structural diagram corresponding to step S3.

FIG. 8: A schematic diagram of the process of forming a silicide layer.

Figure 9: A schematic diagram of the process of forming doped regions.

Figure 10: Schematic diagram of the structure of forming the nitrided layer.

Fig. 11 is a schematic structural diagram corresponding to step S4.

Figure 12: Schematic diagram of the structure for forming the source and drain electrodes.

Fig. 13 is a schematic structural diagram corresponding to step S5.

Figure 14: Schematic illustration of thinning of the interlayer dielectric layer.

Figure 15: Schematic illustration of the thickening of the interlayer dielectric layer.

Figure 16: Schematic diagram of the structure for forming the advanced patterning layer and capping layer.

Figure 17: Schematic diagram of the structure of forming a patterned photoresist layer.

Fig. 18 is a schematic structural diagram corresponding to step S6.

Fig. 19 is a schematic structural diagram corresponding to step S7.

Symbol Description

101: substrate; 102: shallow trench isolation structure; 1021: active region; 103: polysilicon layer; 104: first gate structure; 105: second gate structure; 105: second gate structure; 106: 107: nitride layer; 108: spacer; 109a: source electrode; 109b: drain electrode; 110: interlayer dielectric layer; 111: advanced patterning layer; 112: capping layer; 113: anti-reflection layer; 114: patterned photoresist layer; 115: residual spacer; 116: contact hole; 117: contact electrode; 1041: silicide layer; 104a: nickel layer; 104b: Ni ₂ Si layer; 1061: first doping region; 1062: second doped region; PU1: first pull-up transistor; PU2: second pull-up transistor; PD1: first pull-down transistor; PD2: second pull-down transistor; PG1: first pass-gate transistor; PG2 : second pass gate transistor; INV1: first inverter; INV2: second inverter; Q1, Q2: output terminal; BL, BLB: bit line; WL: word line.

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

It should be noted that the drawings provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, so the drawings only show the components related to the present invention rather than the number, shape and the number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

As shown in FIG. 1, FIG. 1 shows a circuit diagram of a static random access memory. The SRAM includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, and a first channel gate Transistor (Pass Gate transistor) PG1 and second pass gate transistor PG2. The first pull-up transistor PU1 and the first pull-down transistor PD1 form a first inverter INV1, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form a second inverter INV2. The first inverter INV1 is selectively activated in response to the operation of the second pass gate transistor PG2. The second inverter INV2 is selectively activated in response to the operation of the first pass gate transistor PG1. The first inverter INV1 and the second inverter INV2 are alternately coupled, that is, the output Q1 of the first inverter INV1 is connected to the input of the second inverter INV2, and the output of the second inverter INV2 The terminal Q2 is connected to the input terminal of the first inverter INV1.

As shown in FIG. 1 , the drain of the first pass-gate transistor PG1 is coupled to the output terminal Q1 of the first inverter, and the source of the first pass-gate transistor PG1 is coupled to the bit line BL. The drain of the second pass-gate transistor PG2 is coupled to the output terminal Q2 of the second inverter, and the source of the second pass-gate transistor PG2 is coupled to the bit line BLB. The first pass gate transistor PG1 and the second pass gate transistor PG2 are coupled to the word line WL.

As shown in FIG. 1 , the sources of the first pull-up transistor PU1 and the second pull-up transistor PU2 are coupled to the voltage terminal VDD. Sources of the first pull-down transistor PD1 and the second pull-down transistor PD2 are coupled to the voltage terminal GND. The first pass-gate transistor PG1 and the second pass-gate transistor PG2 are, for example, N-type metal-oxide-semiconductor transistors, and the first pull-up transistor PU1 and the second pull-up transistor PU2 are, for example, P-type metal-oxide-semiconductor transistors. The first pull-down transistor PD1 and the second pull-down transistor PD2 are, for example, N-type metal-oxide-semiconductor transistors; that is, the first inverter and the second inverter may be complementary metal-oxide-semiconductor transistors. The P-type metal-oxide-semiconductor transistor and the N-type metal-oxide-semiconductor transistor may use fin field effect transistors.

As shown in FIG. 2, FIG. 2 shows a partial layout of a static random access memory. The first pull-up transistor PU1 is connected to the second pull-up transistor PU2 through the output terminal Q1. The output terminal Q1 may also be called a contact electrode, that is to say, the contact electrode connects the gate of the first pull-up transistor PU1 and the source of the second pull-up transistor PU2. Both the first pull-up transistor PU1 and the second pull-up transistor PU2 are located on the substrate.

As shown in FIG. 3 , this embodiment also provides a method for manufacturing a static random access memory, including:

S1: Provide a substrate, the substrate includes a plurality of isolation structures, and the isolation structures isolate active regions distributed at intervals in the substrate;

S2: forming a first gate structure and a second gate structure on the substrate; wherein the first gate structure is located on the active region, and the second gate structure is located on the isolation structure on, and the projection area of the second gate structure in the direction of the substrate is located in the isolation structure;

S3: forming doped regions in the substrate of the active region and located on both sides of the first gate structure;

S4: forming spacer structures on the first gate structure and on both sides of the second gate structure;

S5: forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the first gate structure and the second gate structure;

S6: Form a contact hole in the interlayer dielectric layer, the contact hole exposes a part of the top of the second gate structure, and exposes a part of the top of the isolation structure, wherein the second gate The side of the pole structure close to the first gate structure also has a residual spacer;

S7: forming a contact electrode in the contact hole, the bottom of the contact electrode is connected to part of the second gate structure and part of the isolation structure; and the length of the connection between the contact electrode and the isolation structure is greater than or equal to the length of the doped region.

The following will take FIG. 4 to FIG. 19 as examples to illustrate the manufacturing process of the SRAM. The cross-sectional views shown in FIGS. 4 to 19 are cross-sectional views taken along the direction A-A in FIG. 2 .

As shown in FIG. 4 , in step S1 , a substrate 101 is first provided, and then a plurality of shallow trench isolation structures 102 are formed in the substrate 101 , and the shallow trench isolation structures 102 isolate a plurality of shallow trench isolation structures 102 in the substrate 101 Active regions 1021 are arranged at intervals. The material of the substrate 101 may include but not limited to single crystal or polycrystalline semiconductor material, the substrate 101 may also include an intrinsic single crystal silicon substrate or a doped silicon substrate; the substrate 101 includes the first doping type substrate, the first doping type can be either P-type or N-type. In this embodiment, only the first doping type is P-type as an example, that is, in this embodiment, the substrate The bottom 101 is only exemplified by a P-type substrate. In this embodiment, the substrate 101 may also be doped to form an N well region.

As shown in FIG. 4 , in this embodiment, the shallow trench isolation structure 102 may be formed by forming a trench (not shown) in the substrate 101 and then filling the trench with an isolation material layer. . The material of the shallow trench isolation structure 102 may include silicon nitride, silicon oxide or silicon oxynitride, and the like, and the material of the shallow trench isolation structure 102 may include silicon oxide. The shape of the longitudinal section of the shallow trench isolation structure 102 can be set according to actual needs. In FIG. 4 , the shape of the longitudinal section of the shallow trench isolation structure 102 includes an inverted trapezoid as an example; The shape of the longitudinal section of the trench isolation structure 102 may also be U-shaped or the like.

It should be noted that, the specific number of the active regions 1021 isolated by the shallow trench isolation structure 102 in the substrate 101 can be set according to actual needs, which is not limited here. In FIG. 4 , only two active regions 1021 in the substrate 101 are illustrated as an example. Several of the active regions 1021 can be arranged in parallel and spaced apart, or can be arranged arbitrarily according to actual needs.

As shown in FIG. 5, in step S2, a polysilicon layer 103 is formed on the substrate 101, and the polysilicon layer 103 may be a polysilicon layer of the second doping type, that is, the doping type of the polysilicon layer 103 is the same as that of the substrate. The doping type of 101 is different; the second doping type can be P-type or N-type, when the first doping type is P-type, the second doping type is N-type, when When the first doping type is N type, the second doping type is P type; the thickness of the polysilicon layer 103 can be set according to actual needs, and the thickness of the polysilicon layer 103 can be between 200nm~ between 500nm. It should be noted that, before forming the polysilicon layer 103, a dielectric layer (not shown in the figure) is also formed on the substrate 101, and the material of the dielectric layer may include but not limited to silicon oxide or silicon oxynitride. The dielectric layer may be formed via a furnace tube oxidation process, a chemical vapor deposition process, a spin-glass process, or other suitable methods.

As shown in FIG. 5-FIG. 6, after the polysilicon layer 103 is formed, a photoresist is formed on the polysilicon layer 103, and then the photoresist is patterned to form a patterned photoresist layer. The patterned photoresist layer exposes the surface of the polysilicon layer 103 to be etched, and then using the patterned photoresist layer as a mask, the polysilicon layer 103 is etched to form the first gate structure 104 and the second gate Structure 105. The polysilicon layer 103 may be etched by a dry etching process, a wet etching process, or a combination of the dry etching process and the wet etching process. For example, the polysilicon layer 103 may be anisotropically etched by a dry etching process. . It should be noted that the structures of the first gate structure 104 and the second gate structure 105 are the same. The first gate structure 104 may include a gate dielectric layer and a gate electrode on the gate dielectric layer.

As shown in FIG. 6 , the first gate structure 104 is located on the active region 1021 , and the second gate structure 105 is located on the shallow trench isolation structure 102 . The projection of the second gate structure 105 in the direction of the substrate 101 completely falls within the shallow trench isolation structure 102 . In this embodiment, the first gate structure 104 is used to form a first transistor, for example, the second gate structure 105 is used to form a second transistor, and the first transistor and the second transistor can be defined as first pull-up transistors . It can be seen from FIG. 6 that the width of the top of the shallow trench isolation structure 102 is larger than the width of the second gate structure 105 , and because the projection of the second gate structure 105 in the direction of the substrate 101 completely falls into the shallow trench In the isolation structure 102, both sides of the second gate structure 105 have shallow trench isolation structures 102 with a certain length. Of course, in some embodiments, the first gate structure 104 may be located on the shallow trench isolation structure 102 and the second gate structure 105 may be located on the active region 1021 .

As shown in FIG. 7 to FIG. 8 , in this embodiment, after the first gate structure 104 and the second gate structure 105 are formed, the top of the first gate structure 104 and the second gate structure 105 are then formed silicide layer 1041. A suicide layer 1041 is located on top of the first gate structure 104 and the second gate structure 105 . The silicide layer 1041 is, for example, a metal silicide such as cobalt silicide, titanium silicide, or nickel silicide, which has low resistance and good adhesion to silicon materials. The silicide layer 1041 can be used as a contact structure of the transistor. In this embodiment, the silicide layer 1041 is formed in the first gate structure 104 as an example for description, and the silicide layer 1041 is nickel silicide as an example for description. The step of forming the silicide layer 1041 may include, firstly, forming a nickel layer 104a on the first gate structure 104 by sputtering technology, and then performing a first annealing process on the nickel layer 104a, and the first annealing process is about 300-380 ℃, through the first annealing process, the silicon atoms in the first gate structure 104 react with the nickel atoms in the nickel layer 104a to form the Ni ₂ Si layer 104b, which can also be called the Ni ₂ Si layer 104b. For the intermediate silicide layer. The thickness of the Ni ₂ Si layer 104b is, for example, 150-400 angstroms. Specifically, the first annealing process can be performed by using a sputtering device. When nickel is deposited by using a sputtering device, the first annealing process can be performed by using an in-situ process after the nickel is deposited, or an ex-situ process can be used. A first annealing process is performed. After the Ni ₂ Si layer 104b is formed, the unreacted nickel layer 104a is selectively removed, and a second annealing process is performed on the Ni ₂ Si layer 104b. The second annealing temperature is higher than the first annealing temperature. Specifically, the second annealing temperature is, for example, 400-500°C. After the second annealing process, the Ni ₂ Si layer 104b is transformed into a silicide layer 1041, and the silicide layer 1041 has thermal stability. The silicide layer 1041 can reduce the resistance of the first gate structure 104 and the second gate structure 105 and improve the performance of the device. In some embodiments, other metals, such as at least one of cobalt, tungsten, platinum, manganese, titanium, and tantalum, may also be formed on the first gate structure 104 .

As shown in FIG. 7 and FIG. 9 , in step S3 , after the silicide layer 1041 is formed on the top of the first gate structure 104 and the second gate structure 105 , for the first gate structure 104 and the second gate structure The substrate 101 on both sides of 105 is doped to form doped regions 106 . The doped region 106 may include a first doped region 1061 and a second doped region 1062 . Both the first doped region 1061 and the second doped region 1062 are located in the substrate 101 . When forming the doped regions 106 , firstly, the first doped regions 1061 are formed, and then the second doped regions 1062 are formed in the first doped regions 1061 . The ion doping type of the first doped region 1061 and the ion doping type of the second doped region 1062 are different. The doping ions of the first doping region 1061 may be P or As. The doping ions of the second doping region 1062 may be B. The step of forming the first doped region 1061 may include using N-type impurities such as arsenic ions as impurities, the implantation energy may be 60-80KeV, for example, 70-75KeV, and the implantation dose may be 10 ¹³ atmos/cm ² . First doped regions 1061 are formed in the substrate 101 on both sides of the pole structure 104 , and the first doped regions 1061 may be N-type pocket doped regions. Then a rapid annealing process is performed to activate the impurities in the first doped region 1061 and suppress the transient enhanced diffusion effect. Then, using a P-type impurity such as boron or boron fluoride (BF ₂ ⁺ ) as an impurity, the implantation energy can be 2-3KeV, and the implant dose can be 1.5´10 ¹⁵ atmos/cm ² , so that the first gate structure 104 is on both sides of the first gate structure 104 A second doped region 1062 is formed in the first doped region 1061 of the first doped region, and then a rapid annealing process is performed to activate the impurities in the second doped region 1061 . The second doped region 1062 may be a PLDD doped region. It should be noted that, before forming the doped region 106, the substrate 101 also needs to be doped to form an N-well region, and the implanted ions may be N-type ions, such as phosphorus.

As shown in FIG. 7 , when the substrate 101 on both sides of the first gate structure 104 is doped, the substrate 101 on both sides of the second gate structure 105 is doped at the same time, because the second gate structure There are shallow trench isolation structures 102 with a certain length on both sides of 105, and the length of the shallow trench isolation structures 102 located on both sides of the second gate structure 105 is greater than or equal to the length of the doped region 106. When the two sides of the structure 105 are doped, the doped regions 106 are located in the shallow trench isolation structure 102. Since the filling material in the shallow trench isolation structure 102 is an insulating material, the doping in the shallow trench isolation structure 102 The region 106 cannot form a conductive region, so it can be considered that there is no doped region 106 on both sides of the second gate structure 105 .

As shown in FIGS. 10-11 , in step S4, after forming the doped region 106, a nitride layer 107 is formed on the substrate 101, and the nitride layer 107 may be silicon nitride. The nitride layer 107 covers the first gate structure 104 and the second gate structure 105 . Then, the nitride layer 107 is etched through a plasma etching process. Since the plasma etching process has a good etching direction, the nitride layers on the surfaces of the first gate structure 104 and the second gate structure 105 107 is etched away, leaving the nitride layer 107 on both sides of the first gate structure 104 and the second gate structure 105, thereby forming sidewalls on both sides of the first gate structure 104 and the second gate structure 105 Wall (offset spacer) 108 . In this embodiment, the spacers 108 located on both sides of the first gate structure 104 are located on the doped region 106 , and the spacers 108 located on both sides of the second gate structure 105 are located on the shallow trench isolation structure 102 . While forming the sidewall spacers 108, the etching process also etches the nitride layer 107 between the shallow trench isolation structure 102 and the doped region 106, thereby reducing the thickness of the nitride layer 107; The thickness of the nitride layer 107 on the first gate structure 104 and the second gate structure 105 is also reduced. It can be seen from FIG. 11 that after the etching process, the nitride layer 107 still covers the first gate structure 104 and the second gate structure 105, and covers other regions of the substrate 101, that is, the nitride layer 107 The entire substrate 101 is covered. It can be seen from FIG. 11 that the inclined surface of the side wall 108 may be an arc surface, and the width of the side wall 108 gradually increases from the top to the bottom. Of course, in some embodiments, the inclined surface of the side wall 108 may also be a straight surface, and the side wall 108 may also be defined as a side wall structure. In some embodiments, the material of the spacer 108 can also be a combination of a nitride layer and an oxide layer, for example, the nitride layer is deposited by a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process, and a normal pressure chemical vapor deposition process is used to deposit the nitride layer. The oxide layer is deposited by a deposition process, a low pressure chemical vapor deposition process or a plasma enhanced chemical vapor deposition process.

As shown in FIG. 12 , after the spacers 108 are formed, regions on both sides of the spacers 108 are ion-doped to form source electrodes 109 a and drain electrodes 109 b in the substrate 101 . The method for forming the source electrode 109 a and the drain electrode 109 b may include, firstly, using the first gate structure 104 and the spacer 108 as masks, ion implantation is performed on the substrate 101 on both sides of the spacer 108 , so as to form in the substrate 101 . Ion doping region, the ion doping type can be N-type or P-type. In this embodiment, the source electrode 109 a and the drain electrode 109 b are located in the active region 1021 .

As shown in FIG. 12, in this embodiment, the source electrode 109a and the drain electrode 109b are located on two sides of the first gate structure 104, respectively, and the source electrode 109a is close to the shallow trench isolation structure 102, or the source electrode 109a is close to the second gate In the gate structure 105 , the drain 109 b is far away from the shallow trench isolation structure 102 , or the drain 109 b is close to the second gate structure 105 . Of course, the drain electrode 109b can also be defined to be close to the second gate structure 102 and the source electrode 109a to be far away from the second gate structure 105 .

As shown in FIG. 12, after the source electrode 109a and the drain electrode 109b are formed, a silicide layer 1041 may also be formed on the source electrode 109a and the drain electrode 109b, and the formation process of the silicide layer 1041 can be referred to the above description. The silicide layer 1041 can prevent the source electrode 109a or the drain electrode 109b from being broken down or leaked, thereby improving the stability of the device.

As shown in FIG. 13 , in step S5 , after the source electrode 109 a and the drain electrode 109 b are formed, an interlayer dielectric layer 110 is then formed on the nitride layer 107 . The interlayer dielectric layer 110 covers the nitride layer 107 , that is, the interlayer dielectric layer 110 covers the first gate structure 104 and the second gate structure 105 . In this embodiment, an interlayer dielectric layer 110 may be formed on the nitride layer 107 by, for example, high-density plasma chemical vapor deposition, and the interlayer dielectric layer 110 completely covers the first gate structure 104 and the second gate structure 105 . The thickness of the interlayer dielectric layer 110 may be 6000-8000 angstroms. The material of the interlayer dielectric layer 110 may be silicon dioxide.

As shown in FIG. 14 , after the interlayer dielectric layer 110 is formed, since the surface of the interlayer dielectric layer 110 is uneven, the surface of the interlayer dielectric layer 110 is planarized. After the planarization process, the thickness of the interlayer dielectric layer 110 may be 1500-2000 angstroms. Meanwhile, after the planarization process, the interlayer dielectric layer 110 still covers the first gate structure 104 and the second gate structure 105 .

As shown in FIG. 15 , after the planarization process, the interlayer dielectric layer 110 is deposited again on the interlayer dielectric layer 110 to increase the thickness of the interlayer dielectric layer 110 . At this time, the thickness of the interlayer dielectric layer 110 may be 3000- 4000 angstroms.

In some embodiments, the material of the interlayer dielectric layer 110 formed for the first time may be phosphosilicate glass, the material of the interlayer dielectric layer 110 formed for the second time is undoped silica glass, and the material of the undoped silica glass High hardness. The interlayer dielectric layer 110 formed for the second time is denser than the interlayer dielectric layer 110 formed for the first time, and the surface uniformity of the interlayer dielectric layer 110 formed for the second time is good, which can improve the performance of the device.

As shown in FIG. 16 , an advanced patterning layer (Advanced Patterning Film, APF) 111 is formed on the interlayer dielectric layer 110 by a conformal chemical vapor deposition process, and then a capping layer 112 is formed on the advanced patterning layer 111. The capping layer 112 A silicon oxynitride layer and a silicon oxide layer may be included. The thickness of the advanced patterning layer 111 may be 1500-2000 angstroms, eg, 1900 angstroms. The thickness of the capping layer 112 may be 300-400 angstroms; the thickness of the silicon oxynitride layer may be 320 angstroms, and the thickness of the silicon oxide layer may be 50 angstroms.

As shown in FIG. 17 , an anti-reflection layer 113 and a patterned photoresist layer 114 are sequentially formed on the cover layer 112 , and the patterned photoresist layer 114 exposes the anti-reflection layer 113 to be etched, so that the anti-reflection layer 113 can be etched. etching.

As shown in FIGS. 17-18 , in step S6 , using the patterned photoresist layer 114 as a mask layer, the anti-reflection layer 113 , the cover layer 112 and the advanced patterning layer 111 are sequentially etched, so that the substrate 101 is etched in sequence. A contact hole 116 is formed thereon, and the contact hole 116 is located between the first gate structure 104 and the second gate structure 105 . The contact hole 116 exposes the source electrode 109a, the second gate structure 105 is close to the sidewall spacer 108 of the first gate structure 104, and also exposes part of the top of the second gate structure 105, and also exposes part of the shallow trench isolation Structure 102 . After etching, there is still a residual spacer 115 on the side of the second gate structure 105 close to the first gate structure 104 , and the residual spacer 115 is located on the exposed shallow trench isolation structure 102 . The spacers 115 are also in contact with the second gate structure 105 , and the remaining spacers 115 can protect the bottom of the second gate structure 105 from being etched. The remaining spacers 115 do not completely cover the shallow trench isolation structure 102 on the side of the second gate structure 105 , that is to say, after the etching process, the second gate structure 105 close to the first gate structure is also exposed The part of the shallow trench isolation structure 102 on one side of 104 , and the length of the exposed part of the shallow trench isolation structure 102 may be greater than or equal to the length of the doped region 106 . Since the doped regions 106 are not formed on both sides of the second gate structure 105 , when the contact hole 116 is formed, the leakage of the second gate structure 105 will not be caused. In this embodiment, the contact hole 116 does not expose the doped region 106 on one side of the first gate structure 104 .

As shown in FIGS. 18-19 , in step S7, after the contact hole 116 is formed, a contact electrode 117 is formed in the contact hole 116, and the contact electrode 117 is used to connect the first pull-up transistor and the second pull-up transistor . In this embodiment, the first gate structure 104, the doped regions 106 on both sides of the first gate structure 104, the source 109a and the drain 109b on both sides of the first gate structure 104, are located on the first gate structure The spacers 108 on both sides of the 104 and the interlayer dielectric layer 110 on the first gate structure 104 define a first transistor. The second gate structure 105 is defined as a second transistor, and the first and second transistors are defined as first pull-up transistors. The gate of the first pull-up transistor may be connected to the source of the second pull-up transistor. That is, the gate of the first pull-up transistor is connected to the source of the second pull-up transistor through the contact electrode 117 , that is, the second gate structure 105 is connected to the source of the second pull-up transistor through the contact electrode 117 . Since the length of the part of the shallow trench isolation structure 102 exposed by the contact hole 116 is greater than or equal to the length of the doped region 106 , the length of the contact electrode 117 connecting the shallow trench isolation structure 102 is greater than or equal to the length of the doped region 106 . At the same time, since the doped regions 106 are not formed on both sides of the second gate structure 105, the leakage of the second gate structure 105 will not be caused, that is, the first pull-up transistor will not leak, so the yield of the device can be improved. The material of the contact electrode 117 can be a metal material, such as copper or tungsten.

As shown in FIG. 19 , the present embodiment also provides a static random access memory, the memory includes a substrate 101 , and the substrate 101 has a shallow trench isolation structure 102 , and the substrate 101 is separated by the shallow trench isolation structure 102 . Bottom 101 is isolated into active region 1021 . A first gate structure 104 and a second gate structure 105 are formed on the substrate 101, the first gate structure 104 is located on the active region 1021, the second gate structure 105 is located on the shallow trench isolation structure 102, and the first gate structure 104 is located on the active region 1021. The projection area of the two gate structures 105 in the direction of the substrate 101 is completely located in the shallow trench isolation structure 102 .

As shown in FIG. 19 , in this embodiment, doped regions 106 are further formed in the active region 1021 of the substrate 101 , and the doped regions 106 are located on both sides of the first gate structure 104 . A source electrode 109a and a drain electrode 109b are further formed in the active region 1021 of the substrate 101, the source electrode 109a and the drain electrode 109b are located on both sides of the first gate structure 104, and the source electrode 109a is located close to the second gate structure On one side of 105 , the drain 109b is located on the side away from the second gate structure 105 . The doped region 106 is located between the source 109a/drain 109b and the first gate structure 104 . The top of the source electrode 109a and the top of the drain electrode 109b also have a silicide layer 1041, and the silicide layer 1041 can improve the performance of the device. The silicide layer 1041 is made of metal silicide, such as cobalt silicide, titanium silicide or nickel silicide. In some embodiments, the source electrode 109 a can also be disposed on a side away from the second gate structure 105 , and the drain electrode 109 b can be disposed on a side close to the second gate structure 105 .

As shown in FIG. 19 , in this embodiment, the tops of the first gate structure 104 and the second gate structure 105 have silicide layers 1041 , and both sides of the first gate structure 104 have spacers 108 , Spacers 108 are located on the doped regions 106 . The second gate structure 105 has a spacer 108 on the side away from the first gate structure 104 , and has a residual spacer 115 on the side of the second gate structure 105 close to the first gate structure 104 . 115 can protect the bottom of the second gate structure 115 from being etched. There is also a nitride layer 107 on the substrate 101, and the nitride layer 107 is located on the drain electrode 109b. A nitride layer 107 is also provided on top of the first gate structure 104 , and a portion of the nitride layer 107 is also provided on top of the second gate structure 105 .

As shown in FIG. 19 , in this embodiment, an interlayer dielectric layer 110 is further formed on the first gate structure 104 and the second gate structure 105 , and the interlayer dielectric layer 110 covers the first gate structure 104 and the second gate structure 105 . In the second gate structure 105 , a contact hole 116 is further formed on the interlayer dielectric layer 110 . The contact hole 116 is located between the first gate structure 104 and the second gate structure 105, and the contact hole exposes the side of the second gate structure 105 close to the first gate structure 104, and also exposes part of the shallow trench isolation structure 102 , and the length of the exposed shallow trench isolation structure 102 is greater than or equal to the length of the doped region 106 . A contact electrode 117 is formed in the contact hole 116 , and the length of the contact electrode 117 in contact with the shallow trench isolation structure 102 may be greater than or equal to the length of the doped region 106 . The contact electrode 117 contacts the second gate structure 105 and the source electrode 109a. In this embodiment, the first gate structure 104, the doped regions 106 on both sides of the first gate structure 104, the source electrode 109a, the drain electrode 109b, and the sidewall spacer 108 are defined as the first transistor, and the second gate electrode is defined as the first transistor. The pole structure 105 is defined as a second transistor, and the first transistor and the second transistor may be defined as a first pull-up transistor.

As shown in FIGS. 1-2, 18-19, in this embodiment, the gate of the first pull-up transistor PU1 is connected to the source of the second pull-up transistor PU2 through the output terminal Q1, and the contact electrode 117 is equivalent to At the output end Q1 , the second gate structure 105 is equivalent to the gate of the first pull-up transistor PU1 , so the second gate structure 105 is connected to the second pull-up transistor PU2 through the contact electrode 117 . In this embodiment, since the doped regions 106 are not formed on both sides of the second gate structure 105 , when the contact holes 116 are formed, the doped regions 106 cannot be etched, so the first pull-up will not be caused Leakage of transistor PU1.

In summary, the present invention provides a static random access memory and a method for manufacturing the same. The first gate structure is formed on the active region, the second gate structure is formed on the isolation structure, and the second gate structure is formed on the isolation structure. The projection area of the pole structure in the direction of the substrate is completely located in the isolation structure, so there are isolation structures on both sides of the second gate structure, and the length of the isolation structure is greater than or equal to the length of the doping area, so it cannot be used in the second gate structure. Doping regions are formed on both sides of the structure, so when the contact holes are formed, the structure of the doping regions will not be destroyed, and at the same time, there are residual sidewalls on the side of the second gate structure close to the first gate structure, The remaining sidewall spacers are located on the isolation structure, and the remaining sidewall spacers can protect the second gate structure; therefore, when the contact hole is formed, the leakage phenomenon of the second gate structure will not be caused, and when the contact electrode is formed in the contact hole, it can be Improve the yield of static random access memory.

Reference throughout this specification to "one embodiment," "anembodiment," or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment includes In at least one embodiment of the invention, and not necessarily in all embodiments. Thus, the phrases "in one embodiment", "in an embodiment" or "in a specific embodiment" are used in various places throughout the specification. Appearances are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any particular embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered part of the spirit and scope of the invention.

It should also be understood that one or more of the elements shown in the figures may also be implemented in a more discrete or integrated manner, or even removed as inoperable in certain circumstances or as may be useful according to a particular application. Provided.

Additionally, any identifying arrows in the accompanying drawings should be regarded as illustrative only and not restrictive unless expressly indicated otherwise. In addition, the term "or" as used herein is generally intended to mean "and/or" unless stated otherwise. Combinations of components or steps will also be considered to have been specified where the term is foreseen because the ability to provide separation or combination is unclear.

As used in the description herein and throughout the claims below, "a (a)," "an (an)," and "the (the)" include plural references unless otherwise indicated. Likewise, as used in the description herein and throughout the claims below, unless otherwise specified, the meaning of "in" includes "in" and "on" .

The above description of illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise form disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as those skilled in the art will recognize and appreciate of. As indicated, these modifications may be made to the present invention in light of the foregoing description of the described embodiments of the present invention and are intended to be within the spirit and scope of the present invention.

The systems and methods have generally been described herein with details that are helpful in understanding the invention. Furthermore, various specific details have been set forth in order to provide a general understanding of embodiments of the present invention. One skilled in the relevant art will recognize, however, that embodiments of the invention may be practiced without one or more of the specific details, or with other devices, systems, accessories, methods, components, materials, parts, etc. practice. In other instances, well-known structures, materials and/or operations have not been specifically shown or described in detail to avoid obscuring aspects of the embodiments of the invention.

Thus, although the invention has been described herein with reference to specific embodiments thereof, freedom of modification, various changes and substitutions are intended to be within the above disclosure, and it should be understood that, in certain circumstances, without departing from the scope and scope of the proposed invention, Some features of the present invention will be employed without the corresponding use of other features in the spirit of the present invention. Therefore, many modifications may be made to adapt a particular environment or material to the essential scope and spirit of the invention. It is not intended that the invention be limited to the specific terms used in the following claims and/or the specific embodiments disclosed as the best modes contemplated for carrying out the invention, but the invention is to be included within the scope of the appended claims any and all embodiments and equivalents within. Accordingly, the scope of the present invention should be determined only by the appended claims.

Claims (9)

1. A static random access memory, characterized in that, comprising: a substrate, the substrate includes a plurality of isolation structures, and the isolation structures isolate active regions distributed at intervals in the substrate; a first gate structure, located on the active region; a second gate structure is located on the isolation structure, and a projection area of the second gate structure in the direction of the substrate is located in the isolation structure; a doped region located in the substrate in the active region and located on both sides of the first gate structure; an interlayer dielectric layer, located on the substrate, covering the first gate structure and the second gate structure; a contact electrode, located in the interlayer dielectric layer, the bottom of the contact electrode is connected to part of the second gate structure and part of the isolation structure; the residual spacer is located at the bottom of the second gate structure, exposing a side of the second gate structure close to the first gate structure; Wherein, the length of the connection between the contact electrode and the isolation structure is greater than or equal to the length of the doped region; Wherein, the contact electrode is also connected to a side of the second gate structure close to the first gate structure; Wherein, the doping region includes a first doping region and a second doping region, and the ion doping type of the first doping region is different from the ion doping type of the second doping region; Wherein, the length of the isolation structure located on both sides of the second gate structure is greater than the length of the doped region. 2 . The SRAM of claim 1 , further comprising a source electrode and a drain electrode, the source electrode and the drain electrode being located in the active region and located at the first gate electrode. 3 . both sides of the structure. 3. The SRAM according to claim 2, further comprising a silicide layer, wherein the silicide layer is located on the source electrode, the drain electrode, the first gate structure and the the top of the second gate structure. 4. The SRAM of claim 2, wherein the contact electrode is further connected to the source electrode or the drain electrode. 5 . The SRAM of claim 1 , wherein two sides of the first gate structure further comprise spacer structures, and the spacer structures are located on the doped region. 6 . 6. A method of manufacturing a static random access memory, comprising: A substrate is provided, the substrate includes a plurality of isolation structures, the isolation structures isolate spaced active regions in the substrate; forming a first gate structure and a second gate structure on the substrate; wherein, the first gate structure is located on the active region, and the second gate structure is located on the isolation structure, and the projection area of the second gate structure in the direction of the substrate is located in the isolation structure; forming doped regions in the substrate of the active region and located on both sides of the first gate structure; forming spacer structures on both sides of the first gate structure and the second gate structure; forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the first gate structure and the second gate structure; A contact hole is formed in the interlayer dielectric layer, and the contact hole exposes a part of the top of the second gate structure and a part of the top of the isolation structure, wherein the second gate structure is close to the One side of the first gate structure also has a residual spacer, the residual spacer is located at the bottom of the second gate structure and exposes the second gate structure close to the first gate structure one side; A contact electrode is formed in the contact hole, and the bottom of the contact electrode is connected with part of the second gate structure and part of the isolation structure; and the length of the connection between the contact electrode and the isolation structure is greater than or equal to the the length of the doped region; wherein, the contact electrode is also connected to the side of the second gate structure close to the first gate structure; Wherein, the step of forming the doped region includes: performing ion doping on both sides of the first gate structure to form a first doping region; performing ion doping on the first doping region to form a second doping region in the first doping region; Wherein, the ion doping type of the first doping region is different from the ion doping type of the second doping region; Wherein, the length of the isolation structure located on both sides of the second gate structure is greater than the length of the doped region. 7. The manufacturing method according to claim 6, wherein the step of forming the sidewall structure comprises: forming a nitride layer on the substrate, the nitride layer covering the first gate structure and the second gate structure; removing part of the nitride layer on top of the first gate structure and the second gate structure by dry etching to form a spacer structure; Wherein, after the dry etching, the nitride layer remains on the substrate, the top of the first gate structure and the top of the second gate structure. 8 . The manufacturing method according to claim 6 , wherein before forming the interlayer dielectric layer, a source electrode and a drain electrode are also formed on both sides of the first gate structure, and the source electrode and the all electrode are formed. 9 . The steps of describing the drain include: ion doping the substrate on both sides of the first gate structure to form the source and the drain in the substrate; Wherein, the source electrode or the drain electrode is close to the second gate structure. 9 . The manufacturing method according to claim 8 , wherein a silicide layer is further formed on top of the first gate structure, the second gate structure, the source electrode and the drain electrode, The step of forming the silicide layer includes: A metal layer is formed on top of the first gate structure, the second gate structure, the source electrode and the drain electrode; performing a first annealing to make metal atoms in the metal layer react with silicon atoms to form an intermediate silicide layer; performing a second anneal to convert the intermediate silicide layer to the silicide layer; Wherein, the temperature of the second annealing is greater than the temperature of the first annealing.

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