CN112103302B - Packaging structure and packaging method thereof - Google Patents

Abstract

A packaging structure and a packaging method thereof, the packaging structure comprising: a photosensitive wafer, comprising a first substrate and a first dielectric layer located on the first substrate, the photosensitive wafer comprising a first guard ring region and a scribing region surrounding the first guard ring region, the first guard ring region comprising a first top-layer interconnection line located in the first dielectric layer; a protection plug, penetrating the first substrate of the first guard ring region and extending at least into the first dielectric layer, the protection plug being located on a side of the first top-layer interconnection line close to the scribing region, and the protection plug being connected to the first top-layer interconnection line. The protection plug can shield cutting stress and moisture, thereby reducing the probability of damage to the effective circuit in the internal area of the first chip, thereby improving the packaging yield and reliability, and correspondingly improving the performance of the image sensor.

Description

Packaging structure and packaging method thereof

Technical Field

The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a packaging structure and a packaging method thereof.

Background Art

With the development of semiconductor technology, image sensors have been widely used in various fields that require digital imaging. According to the working principle and physical architecture, image sensors can generally be divided into two categories: charge coupled device (CCD) image sensor and complementary metal oxide semiconductor image sensor (CMOS image sensor, CIS). Among them, CMOS image sensors are increasingly widely used due to their low power consumption, low cost and compatibility with CMOS technology.

As the pixel value of image sensor chips increases, the physical size of pixel units decreases, making it difficult for image sensor chips to be manufactured in the same process as signal processing modules. In addition, as the photosensitive area of pixel units decreases, in order to prevent image distortion, pixel units also have strict restrictions on the amount of incident photons. If the chip is packaged from the back, photons pass through the metal interconnect layer to enter the pixel photosensitive area. The complex metal interconnect layer often blocks some photons, causing the number of photons obtained in the photosensitive area to fail to meet the imaging requirements.

Therefore, in the current manufacturing process, stacked chip technology (for example, 3D stacked chip technology) is usually used to make the image sensor module in one chip and the signal processing module in another chip, and then the chips are stacked together through bonding between wafers to form an image sensor. After the stacked chip is completed, the chips in the wafer are cut apart through thinning and dicing processes.

At the same time, a back-side illuminated (BSI) process is used to form a back-illuminated CMOS image sensor. The back-illuminated CMOS image sensor not only has the advantages of low cost, small size and high performance, but also, based on traditional image sensor technology, transfers the circuit part originally located between the lens and the photosensitive semiconductor to the vicinity or below the photosensitive semiconductor, so that light can directly enter the photosensitive semiconductor, thereby preventing the metal interconnection layer from blocking the light and greatly improving the light utilization efficiency of the pixel unit.

Summary of the invention

The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method thereof to improve the performance of an image sensor.

To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a photosensitive wafer, including a first substrate and a first dielectric layer located on the first substrate, the photosensitive wafer including a first guard ring area and a dicing area surrounding the first guard ring area, the first guard ring area including a first top-level interconnection line located in the first dielectric layer; a protection plug, penetrating the first substrate of the first guard ring area and extending at least into the first dielectric layer, the protection plug being located on a side of the first top-level interconnection line close to the dicing area, and the protection plug being connected to the first top-level interconnection line.

Correspondingly, an embodiment of the present invention also provides a packaging method, comprising: providing a photosensitive wafer, comprising a first substrate and a first dielectric layer located on the first substrate, the photosensitive wafer comprising a first guard ring area, and a dicing area surrounding the first guard ring area, the first guard ring area comprising a first top-layer interconnection line located in the first dielectric layer; etching at least the first substrate and a partial thickness of the first dielectric layer in the first guard ring area along a direction from the first substrate to the first dielectric layer to form an opening that penetrates the first substrate and extends at least into the first dielectric layer, the opening being located on a side of the first top-layer interconnection line close to the dicing area, and the opening exposing the first top-layer interconnection line; and forming a protective plug in the opening.

Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

In the embodiment of the present invention, a protective plug is arranged in the photosensitive wafer, the protective plug penetrates the first substrate of the first protection ring region and extends at least into the first dielectric layer, the protective plug is located on the side of the first top interconnection line close to the scribe line, and the protective plug is connected to the first top interconnection line; the photosensitive wafer generally includes a plurality of chip regions, the chip region includes a chip internal region and a first protection ring region surrounding the chip internal region, the protective plug can protect the chip internal region of the photosensitive wafer, on the one hand, when the photosensitive wafer is subsequently cut along the scribe region, the cracks caused by the damage to the scribe region are shielded by the protective plug, thereby reducing the probability of the cracks extending along the first substrate to the chip internal region, and correspondingly reducing the influence of the cutting stress on the effective circuit in the chip internal region, on the other hand, after the cutting is completed, the protective plug can also prevent moisture from penetrating into the chip internal region through the first substrate, and correspondingly also reduces the probability of the effective circuit in the chip internal region being damaged. In summary, the embodiment of the present invention improves the packaging yield and reliability through the protective plug, thereby improving the performance of the image sensor.

In an optional solution, the packaging structure also includes: a signal processing wafer bonded to the photosensitive wafer, the signal processing wafer including a second substrate and a second dielectric layer located on the second substrate, the second dielectric layer facing the first dielectric layer, the signal processing wafer including a second guard ring area, the second guard ring area corresponding to the position of the first guard ring area, the second guard ring area including a second top-layer interconnection line located in the second dielectric layer, and the second top-layer interconnection line corresponding to the position of the first top-layer interconnection line, the protection plug correspondingly passes through the first substrate and the first dielectric layer of the first guard ring area, and extends into the second dielectric layer of the second guard ring area, and the protection plug is also connected to the second top-layer interconnection line; by connecting the protection plug to both the first top-layer interconnection line and the second top-layer interconnection line, the internal area of the first chip is placed in a closed cavity, thereby further improving the protection effect of the protection plug on the effective circuit in the internal area of the first chip, thereby further improving the performance of the image sensor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a partial top view of a wafer;

FIG2 is a cross-sectional view of a packaging structure in a guard ring area and a dicing area;

FIG3 is a cross-sectional view after cutting along the dicing area in FIG2 ;

FIG4 is a partial top view of a photosensitive wafer according to an embodiment of the present invention;

FIG5 is a partial top view of a signal processing wafer according to an embodiment of the present invention;

6 is a cross-sectional view of a packaging structure in a guard ring region and a dicing region according to an embodiment of the present invention;

7 to 13 are schematic structural diagrams corresponding to the steps in an embodiment of a packaging method of the present invention.

DETAILED DESCRIPTION

At present, the performance of image sensors still needs to be improved. Now, a packaging structure is combined to analyze the reasons why the performance of image sensors still needs to be improved.

Referring to FIG. 1 , a partial top view of a wafer is shown.

The wafer includes a plurality of chip regions 10 a , wherein the chip region 10 a includes a chip inner region (not labeled) and a guard ring region (not labeled) surrounding the chip inner region. The plurality of chip regions 10 a are surrounded by a dicing region 10 b .

3D stacked back-illuminated CMOS image sensors are usually made by bonding a photosensitive wafer and a logic wafer. After the bonding process between the wafers is completed, thinning and dicing processes are required to cut the chips on the wafers, and then packaging and final testing are performed. As shown in Figure 1, when dicing, it is necessary to cut along the dicing area 10b between the chip area 10a in the x-direction and y-direction.

2 , a cross-sectional view of a packaging structure in a guard ring region and a dicing region is shown.

As shown in FIG. 2 , the packaging structure includes: a logic wafer 20 ; and a photosensitive wafer 30 , which is inverted on the logic wafer 20 and bonded to the logic wafer 20 .

The photosensitive wafer 30 includes a first substrate 31 and a first dielectric layer 32 located on the first substrate 31 , and the logic wafer 20 includes a second substrate 21 and a second dielectric layer 22 located on the second substrate 21 , and the second dielectric layer 22 and the first dielectric layer 32 are arranged opposite to each other.

Each wafer includes a chip region 10a (as shown in FIG. 1 ), the chip region 10a includes a chip internal region (not shown) and a guard ring region 10s surrounding the chip internal region, a dicing region 10b surrounds the plurality of chip regions 10a, and a first interconnect structure 35 is provided in a first dielectric layer 32 of the guard ring region 10s, and a second interconnect structure 25 is provided in a second dielectric layer 22 of the guard ring region 10s. Both the first interconnect structure 35 and the second interconnect structure 25 are used as guard rings.

The internal area of the chip of the photosensitive wafer 30 is the location of the effective circuit. However, due to the use of a back-illuminated process, the top of the back-illuminated CMOS image sensor corresponds to the first substrate 31 of the photosensitive wafer 30. The protection ring formed by the back end ofline (BEOL) process is located in the first dielectric layer 32 and the second dielectric layer 22 below the first substrate 31, and the first substrate 31 is not provided with a protection ring. Therefore, when the wafer is subsequently cut along the dicing area 10b, the cutting stress is applied to the photosensitive wafer 30, and the first substrate 31 is easily damaged due to the cutting stress.

As shown in Fig. 3, a cross-sectional view after cutting along the dicing area 10b in Fig. 2 is shown. Since the edge of the dicing area 10b after cutting is easily damaged, these damages are easy to evolve into cracks 33, and the cracks 33 are easy to extend from the edge of the dicing area 10b after cutting along the first substrate 31 to the chip internal area of the photosensitive wafer 30, thereby causing damage to the effective circuit in the chip internal area, thereby causing the performance of the image sensor to deteriorate.

Moreover, after the cutting process is completed, moisture is also easy to penetrate from the edge of the cut dicing area 10b along the first substrate 31 to the internal area of the chip of the photosensitive wafer 30, which is also easy to reduce the performance of the image sensor.

In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, including: a photosensitive wafer, including a first substrate and a first dielectric layer located on the first substrate, the photosensitive wafer including a first guard ring area and a dicing area surrounding the first guard ring area, the first guard ring area including a first top-level interconnection line located in the first dielectric layer; a protection plug, penetrating the first substrate of the first guard ring area and extending at least into the first dielectric layer, the protection plug being located on a side of the first top-level interconnection line close to the dicing area, and the protection plug being connected to the first top-level interconnection line.

The protective plug protects the chip internal area of the photosensitive wafer. On the one hand, when the photosensitive wafer is subsequently cut along the dicing area, the protective plug can shield the cracks caused by damage to the dicing area, thereby reducing the probability of the cracks extending along the first substrate to the chip internal area, and correspondingly reducing the impact of the cutting stress on the effective circuit in the chip internal area. On the other hand, after the cutting is completed, the protective plug can also prevent moisture from penetrating into the chip internal area through the first substrate, and correspondingly reduces the probability of damage to the effective circuit in the chip internal area. In summary, the packaging yield and reliability are improved through the protective plug, thereby improving the performance of the image sensor.

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

4 to 6 , FIG. 4 is a partial top view of a photosensitive wafer according to an embodiment of the present invention, FIG. 5 is a partial top view of a signal processing wafer according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view of a packaging structure in a guard ring area and a dicing area according to an embodiment of the present invention.

The packaging structure includes: a photosensitive wafer 100, including a first substrate 110 and a first dielectric layer 120 located on the first substrate 110, the photosensitive wafer 100 includes a plurality of first chip regions 100a (as shown in FIG. 4 ), the first chip region 100a includes a first chip internal region (not shown) and a first guard ring region 100s surrounding the first chip internal region (as shown in FIG. 6 ), the plurality of first chip regions 100a are surrounded by a first dicing region 100b, the first guard ring region 100s includes A first interconnection layer structure 130 (as shown in FIG. 6 ) located in the first dielectric layer 120, the first interconnection layer structure 130 includes a first top-layer interconnection line 132 (as shown in FIG. 6 ); a protection plug 300 (as shown in FIG. 6 ) penetrating the first substrate 110 of the first protection ring area 100s and extending at least into the first dielectric layer 120, the protection plug 300 being located on a side of the first top-layer interconnection line 132 close to the first dicing area 100b, and the protection plug 300 being connected to the first top-layer interconnection line 132.

The protection plug 300 can protect the first chip internal area of the photosensitive wafer 100. On the one hand, when the photosensitive wafer 100 is subsequently cut along the first dicing area 100b, the cracks caused by the damage to the first dicing area 100b are shielded by the protection plug 300, thereby reducing the probability of the cracks extending along the first substrate 110 to the first chip internal area, and correspondingly reducing the impact of the cutting stress on the effective circuit in the first chip internal area. On the other hand, after the cutting is completed, the protection plug 300 can also prevent moisture from penetrating into the first chip internal area through the first substrate 110, and correspondingly reduces the probability of the effective circuit in the first chip internal area being damaged. In summary, the protection plug 300 improves the packaging yield and reliability, thereby improving the performance of the image sensor.

The packaging structure provided by the present invention will be described in detail below with reference to the accompanying drawings.

In this embodiment, the packaging structure is a 3D stacked back-illuminated CMOS image sensor, and therefore, the packaging structure at least includes a photosensitive wafer 100 .

The photosensitive wafer 100 has a plurality of image sensor chips therein, and the image sensor chips are used to receive light signals and convert the light signals into electrical signals. In this embodiment, the image sensor chips are CMOS image sensor chips.

In the packaging process, after the photosensitive wafer 100 and the signal processing wafer are bonded, the photosensitive wafer 100 and the signal processing wafer are stacked together to form an image sensor.

In this embodiment, the photosensitive wafer 100 includes a first substrate 110 .

In this embodiment, the first substrate 110 is a silicon substrate. In other embodiments, the material of the first substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

Referring to FIG. 4 , FIG. 4 is a partial top view of the photosensitive wafer 100, wherein the photosensitive wafer 100 includes a plurality of first chip regions 100a, wherein the first chip region 100a includes a first chip internal region (not shown) and a first guard ring region 100s surrounding the first chip internal region (as shown in FIG. 6 ), and a first dicing region 100b surrounds the plurality of first chip regions. When dicing the photosensitive wafer 100, it is necessary to perform cutting in the X direction and the Y direction along the first dicing region 100b between the first chip regions 100a, so as to obtain a single image sensor chip.

A variety of CMOS devices are formed in the inner region of the first chip, and the CMOS devices include but are not limited to transistors and photodiodes.

A first interconnection structure (not marked) located in the first dielectric layer 120 is also formed in the internal area of the first chip. The first interconnection structure includes a first interconnection layer structure 130 composed of multiple layers of interconnection lines and a first through-hole structure (not marked) for connecting each layer of interconnection lines. The first interconnection structure is used to achieve electrical connection with the CMOS device in the photosensitive wafer 100.

During the manufacturing process of the photosensitive wafer 100, while the first interconnect structure is formed in the first chip internal area, the first interconnect structure is also formed in the first guard ring area 100s. Therefore, the first guard ring area 100s includes a first interconnect layer structure 130 located in the first dielectric layer 120, and the first interconnect layer structure 130 includes a first top interconnect line 132. The first top interconnect line 132 refers to: the interconnect line in the first interconnect layer structure 130 that is farthest from the first substrate 110.

In this embodiment, the first interconnect layer structure 130 and the first through-hole structure in the first guard ring region 100 s are used as a guard ring for the photosensitive wafer 100 .

As shown in FIG6 , in this embodiment, the first interconnection layer structure 130 further includes: a first interlayer interconnection line 131, which is located between the first top-layer interconnection line 132 and the first substrate 110. In the extension direction of the first top-layer interconnection line 132, the first top-layer interconnection line 132 has a first end p1 facing the first scribing region 100b, and the first interlayer interconnection line 131 has a second end p2 facing the first scribing region 100b, and the second end p2 is located on a side of the first end p1 away from the first scribing region 100b.

The process of forming the protection plug 300 generally includes an etching process. By positioning the second end p2 on a side of the first end p1 away from the first dicing area 100 b , etching of the first interlayer interconnection line 131 is avoided, thereby reducing the process difficulty of forming the protection plug 300 .

It should be noted that the distance d1 from the second end p2 to the first end p1 should not be too small or too large. If the distance d1 is too small, it is easy to cause the etching process of forming the protection plug 300 to cause mis-etching of the first interlayer interconnection line 131, or it is easy to cause the protection plug 300 to fail to contact the first top layer interconnection line 132, which correspondingly reduces the process window for forming the protection plug 300; if the distance d1 is too large, it will cause the width of the first protection ring area 100s to be too large, thereby causing the size of the packaging structure to be too large, which is not conducive to improving the chip integration, or it will cause the length of the first interlayer interconnection line 131 to be too small, which will correspondingly increase the process difficulty of forming the first interlayer interconnection line 131. For this reason, in this embodiment, the distance d1 from the second end p2 to the first end p1 is 5 microns to 10 microns.

The first dielectric layer 120 is used to achieve electrical isolation of the first interconnect structure.

The material of the first dielectric layer 120 can be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6), thereby effectively reducing the parasitic capacitance between the first interconnect structures and thereby reducing the RC delay of the device.

The material of the first dielectric layer 120 may be SiOH, SiOCH, fluorine-doped silicon dioxide (FSG), boron-doped silicon dioxide (BSG), phosphorus-doped silicon dioxide (PSG), boron-phosphorus-doped silicon dioxide (BPSG), hydrogenated silsesquioxane (HSQ, (HSiO _1.5 ) _n ) or methyl silsesquioxane (MSQ, (CH ₃ SiO _1.5 ) _n ). In this embodiment, the material of the first dielectric layer 120 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing holes.

The protection plug 300 is also used as a protection ring for the photosensitive wafer 100 .

In this embodiment, the protection plug 300 and the first top-layer interconnection line 132 have an overlapping portion, so that the protection plug 300 can protect the internal area of the first chip.

Moreover, the process of forming the protection plug 300 generally includes an etching process. During the etching process, the surface of the first top-layer interconnect line 132 facing the first substrate 110 is used to define the etching stop position, thereby improving the over-etching problem of the first dielectric layer 120, so that the morphology, position and size of the protection plug 300 can meet the process requirements.

However, the length d5 (as shown in FIG. 6 ) of the portion of the first top-layer interconnection line 132 that overlaps with the protection plug 300 should not be too small or too large. If the length d5 is too small, it is easy for the protection plug 300 to fail to contact the first top-layer interconnection line 132, which correspondingly reduces the process window for forming the protection plug 300; if the length d5 is too large, it is easy for the etching process for forming the protection plug 300 to cause mis-etching of the first inter-layer interconnection line 131, or cause the width of the first protection ring area 100s to be too large, thereby causing the size of the package structure to be too large. For this reason, in this embodiment, the length d5 of the portion of the first top-layer interconnection line 132 that overlaps with the protection plug 300 is 0.5 microns to 2 microns.

In this embodiment, the material of the protection plug 300 is a metal material. The hardness and density of the metal material are relatively high, which improves the shielding effect of the protection plug 300 on the cutting stress and the barrier effect on moisture, thereby improving the protection effect of the protection plug 300 on the internal area of the first chip. In addition, the protection plug 300 is in contact with the first top-layer interconnection line 132, so by selecting a metal material, the adhesion between the protection plug 300 and the first top-layer interconnection line 132 is correspondingly improved.

The material of the protection plug 300 may be a metal material commonly used in the art. In this embodiment, the material of the protection plug 300 is copper. Copper has filling properties and is a commonly used material in the current back-end process, which is conducive to improving the compatibility of the formation process of the protection plug 300.

In this embodiment, the packaging structure is a 3D stacked back-illuminated CMOS image sensor. Therefore, the packaging structure further includes: a signal processing (digital signal processor, DSP) wafer 200 bonded to the photosensitive wafer 100 .

The signal processing wafer 200 has a plurality of signal processing chips, and the signal processing chips have logic circuits such as signal control, readout and processing, and the signal processing chips are used to process the electrical signals converted from the optical signals. Accordingly, in this embodiment, the signal processing wafer 200 is a logic wafer.

Among them, the image sensor chip and the signal processing chip are arranged relative to each other, and the image sensor chip and the signal processing chip are less restricted by each other, which makes it easy for both the image sensor chip and the signal processing chip to obtain the best performance, thereby improving the packaging performance. At the same time, the image sensor chip and the signal processing chip can be combined arbitrarily, making the packaging structure more flexible.

Moreover, since the image sensor chip and the signal processing chip are not arranged on the same chip, the area of the image sensor chip is smaller, thereby reducing the design cost of the image sensor chip and correspondingly reducing the packaging cost.

In addition, the signal processing wafer 200 can also support the photosensitive wafer 100. During the process of forming the protective plug 300 and thinning the photosensitive wafer 100, the signal processing wafer 200 can improve the mechanical strength of the photosensitive wafer 100 and reduce the probability of the photosensitive wafer 100 breaking, thereby improving the reliability of the packaging structure.

In this embodiment, the signal processing wafer 200 includes a second substrate 210 and a second dielectric layer 220 located on the second substrate 210 , and the second dielectric layer 220 faces the first dielectric layer 120 .

The size of the signal processing wafer 200 is consistent with that of the photosensitive wafer 100. Accordingly, in combination with reference to Figure 5, the signal processing wafer 200 includes a plurality of second chip areas 200a, the second chip area 200a includes a second chip internal area (not shown) and a second guard ring area 200s surrounding the second chip internal area (as shown in Figure 6), and the plurality of second chip areas 200a are surrounded by a second dicing area 200b.

When dicing the signal processing wafer 200 , it is necessary to perform cutting in the X direction and the Y direction along the second dicing region 200 b between the second chip regions 200 a , so as to obtain a single signal processing chip.

To this end, the second chip internal region corresponds to the first chip internal region, the second guard ring region 200s corresponds to the first guard ring region 100s (as shown in FIG. 6 ), and the second dicing region 200b corresponds to the first dicing region 100b.

As shown in FIG6 , in this embodiment, the second guard ring region 200s includes a second interconnect layer structure 230 located in the second dielectric layer 220, and the second interconnect layer structure 230 includes a second top-layer interconnect line 232, and the second top-layer interconnect line 232 corresponds to the position of the first top-layer interconnect line 132. In other words, the projection of the first top-layer interconnect line 132 on the first substrate 110 is close to or has an overlapping portion with the projection of the second top-layer interconnect line 232 on the first substrate 110, so that the protection plug 300 can be connected to the first top-layer interconnect line 132 and the second top-layer interconnect line 232 at the same time.

Specifically, a second interconnect structure (not labeled) located in the second dielectric layer 220 is formed in the second guard ring region 200s, the second interconnect structure includes a second interconnect layer structure 230 composed of multiple layers of interconnect lines and a second through-hole structure (not labeled) for connecting each layer of interconnect lines, and the second interconnect structure is used to achieve electrical connection with the CMOS device in the signal processing wafer 200. The second top-layer interconnect line 232 refers to: the interconnect line in the second interconnect layer structure 230 that is farthest from the second substrate 210.

In this embodiment, the second interconnection layer structure 230 further includes: a second interlayer interconnection line 231 located between the second top-layer interconnection line 232 and the second substrate 210 .

In this embodiment, the second interconnect layer structure 230 and the second through-hole structure in the second guard ring region 200 s are used as a guard ring of the signal processing wafer 200 .

For the detailed description of the second substrate 210 , the second dielectric layer 220 and the second interconnect layer structure 230 , reference may be made to the aforementioned corresponding description of the photosensitive wafer 100 , which will not be repeated here.

In this embodiment, the protection plug 300 penetrates the first substrate 110 and the first dielectric layer 120 of the first guard ring region 100s and extends into the second dielectric layer 220 of the second guard ring region 200s. The protection plug 300 is also connected to the second top-layer interconnect line 232.

By connecting the protection plug 300 to both the first top-layer interconnection line 132 and the second top-layer interconnection line 232, the first chip internal area (not shown) is placed in a closed cavity, thereby further improving the protection effect of the protection plug 300 on the effective circuit in the first chip internal area, thereby further improving the performance of the image sensor.

In this embodiment, along the extension direction of the first top-layer interconnection line 132 , the second top-layer interconnection line 232 has a third end p3 facing the first dicing region 100 b , and the first end p1 is located on a side of the third end p3 away from the first dicing region 100 b .

The process of forming the protection plug 300 generally includes an etching process. By making the first end p1 located on a side of the third end p3 away from the first slicing area 100b, etching of the first top-layer interconnection line 132 is avoided, and the protection plug 300 is easily brought into contact with the second top-layer interconnection line 232, thereby reducing the process difficulty of forming the protection plug 300.

Correspondingly, in this embodiment, the protective plug 300 includes: a first plug portion 310, which is directed from the photosensitive wafer 100 to the signal processing wafer 200, and the first plug portion 310 penetrates the first substrate 110 and the first dielectric layer 120 above the first top-level interconnection line 132; a second plug portion 320, which is directed from the photosensitive wafer 100 to the signal processing wafer 200, and the second plug portion 320 penetrates the remaining first dielectric layer 120 below the first plug portion 310 and the second dielectric layer 220 above the second top-level interconnection line 232, and in a direction parallel to the surface of the first substrate 110, the line width dimension of the second plug portion 320 is smaller than the line width dimension of the first plug portion 310. Among them, the first plug portion 310 has an overlapping portion with the first top-level interconnection line 132, the second plug portion 320 is located on one side of the first top-level interconnection line 132 and is isolated from the first top-level interconnection line 132, and the projection of the second plug portion 320 on the second top-level interconnection line 232 is located within the second top-level interconnection line 232.

The steps of forming the protection plug 300 generally include: forming a groove and a through hole that penetrate each other, the groove exposing a portion of the surface of the first top-layer interconnection line 132 and a portion of the first dielectric layer 120 on one side of the first top-layer interconnection line 132, and the through hole exposing a portion of the surface of the second top-layer interconnection line 232, and the groove and the through hole are used to form an opening; forming the protection plug 300 in the opening, the portion of the protection plug 300 located in the groove is used as the first plug portion 310, and the portion of the protection plug 300 located in the through hole is used as the second plug portion 320.

The second plug portion 320 is located at one side of the first top interconnect line 132 and isolated from the first top interconnect line 132 , thereby providing a larger process window for forming the through hole and reducing the probability of the first top interconnect line 132 being mistakenly etched.

The projection of the second plug portion 320 on the second top-layer interconnection line 232 is located within the second top-layer interconnection line 232. During the etching process for forming the through hole, the problem of mis-etching of the second dielectric layer 220 is reduced, so that the dimensions and morphologies of the protection plug can meet the process requirements; moreover, it is beneficial to improve the sealing of the protection plug 300, thereby further improving the protection effect of the protection plug 300 on the effective circuit in the internal area of the first chip; in addition, the problem of the second protection ring area 200s being too large can be avoided.

It should be noted that the bottom line width dimension d3 (as shown in FIG6 ) of the first plug portion 310 should not be too small or too large. If the bottom line width dimension d3 of the first plug portion 310 is too small, on the one hand, it is easy to reduce the protection performance of the first plug portion 310, and on the other hand, it is easy to increase the process difficulty of forming the second plug portion 320, and it is also easy to cause the top line width dimension d4 of the second plug portion 320 to be too small, thereby easily reducing the protection performance of the second plug portion 320; if the bottom line width dimension d3 of the first plug portion 310 is too large, it will correspondingly cause the width of the first guard ring area 100s and the second guard ring area 200s to be too large, thereby causing the size of the packaging structure to be too large, which is not conducive to improving the integration of the chip. For this reason, in this embodiment, the bottom line width dimension d3 of the first plug portion 310 is 2 microns to 5 microns.

It should also be noted that the top line width dimension d4 (as shown in FIG. 6 ) of the second plug portion 320 should not be too small or too large. If the top line width dimension d4 of the second plug portion 320 is too small, it will not only increase the process difficulty of forming the second plug portion 320, but also reduce the protection performance of the second plug portion 320; if the top line width dimension d4 of the second plug portion 320 is too large, it will cause the bottom line width dimension d3 of the first plug portion 310 to be too large, thereby causing the width of the first guard ring area 100s and the second guard ring area 200s to be too large, and further causing the size of the packaging structure to be too large. For this reason, in this embodiment, the top line width dimension d4 of the second plug portion 320 is 1 micron to 3 microns.

In addition, the first plug portion 310 has a first boundary (not marked) at the bottom away from the first top-layer interconnection line 132, and the second plug portion 320 has a second boundary (not marked) at the top away from the first top-layer interconnection line 132. The distance d2 from the first boundary to the second boundary (as shown in FIG. 6) should not be too small or too large. If the distance d2 is too small, it is easy to increase the difficulty of controlling the overlay accuracy, and the process window for forming the groove or through hole will be reduced accordingly; if the distance d2 is too large, the width of the first guard ring area 100s and the second guard ring area 200s will be too large, which will lead to an overly large size of the packaging structure. For this reason, in this embodiment, the distance d2 from the first boundary to the second boundary is 1 micron to 3 microns.

In this embodiment, the packaging structure further includes: an isolation layer 160 located between the protection plug 300 and the first substrate 110 .

The material of the protection plug 300 is a metal material, that is, the protection plug 300 is conductive, and the first substrate 110 is also conductive. The isolation layer 160 is used to achieve electrical isolation between the protection plug 300 and the first substrate 110, thereby ensuring the normal performance of the packaging structure.

Specifically, the isolation layer 160 is made of silicon dioxide, which is a commonly used insulating material with low process cost and low stress, so that the adhesion between the isolation layer 160 and the first substrate 110 and between the isolation layer 160 and the protection plug 300 is good.

The thickness of the isolation layer 160 should not be too small or too large. If the thickness of the isolation layer 160 is too small, it is easy to cause the electrical isolation effect of the isolation layer 160 to be poor; if the thickness of the isolation layer 160 is too large, it is easy to cause the width of the first guard ring area 100s and the second guard ring area 200s to be too large, thereby causing the size of the packaging structure to be too large. For this reason, in this embodiment, the thickness of the isolation layer 160 is to For example, the thickness of the isolation layer 160 is or

It should be noted that the isolation layer 160 is formed after etching the first substrate 110 , and the isolation layer 160 is usually formed by deposition. Therefore, the isolation layer 160 is also located on the surface of the first substrate 110 facing away from the first dielectric layer 110 .

In this embodiment, the packaging structure further includes: a barrier layer 140 covering the first substrate 110 and the protection plug 300 ; and a passivation layer 150 covering the barrier layer 140 .

The passivation layer 150 is used to protect the protection plug 300 and prevent the protection plug 300 from being oxidized due to being exposed to the outside, so the material of the passivation layer 1150 is an insulating material. In this embodiment, the material of the passivation layer is silicon dioxide.

In this embodiment, in order to ensure the protection effect of the passivation layer 150 and avoid the problem of excessive thickness of the packaging structure, the thickness of the passivation layer 150 is to For example, the thickness of the passivation layer 150 is or

The material of the protection plug 300 is a metal material, and the barrier layer 140 is used to prevent the diffusion of the metal material in the protection plug 300, thereby reducing defects and preventing the surface of the packaging structure from being conductive, thereby ensuring the normal performance of the packaging structure.

In this embodiment, the material of the barrier layer 140 is silicon nitride. Silicon nitride has a high density, so that the barrier effect of the barrier layer 140 is better.

In this embodiment, in order to ensure the barrier effect of the barrier layer 140 and avoid the problem of excessive thickness of the packaging structure, the thickness of the barrier layer 140 is to For example, the thickness of the barrier layer 140 is or

It should be noted that the isolation layer 160 is also located on the surface of the first substrate 110 facing away from the first dielectric layer 110 , so the barrier layer 140 covers the isolation layer 160 and the protection plug 300 .

It should also be noted that, in this embodiment, the overlapping portion between the protection plug 300 and the first top interconnection line 132 is used as an example for description. In other embodiments, according to actual conditions, the protection plug may also contact the side wall of the first top interconnection line facing the first dicing area.

Correspondingly, the present invention further provides a packaging method. Referring to Figures 7 to 13, schematic structural diagrams corresponding to each step in an embodiment of the packaging method of the present invention are shown.

Referring to Figure 7 and in combination with Figure 4, Figure 4 is a partial top view of the photosensitive wafer of the present embodiment, and a photosensitive wafer 100 is provided, including a first substrate 110 and a first dielectric layer 120 located on the first substrate 110, the photosensitive wafer 100 includes a plurality of first chip areas 100a (as shown in Figure 4), the first chip area 100a includes a first chip internal area (not shown) and a first guard ring area 100s surrounding the first chip internal area, the plurality of first chip areas are surrounded by a first dicing area 100b, the first guard ring area 100s includes a first interconnection layer structure 130 located in the first dielectric layer 120, the first interconnection layer structure 130 includes a first top-level interconnection line 132.

The photosensitive wafer 100 has a plurality of image sensor chips therein, and after the photosensitive wafer 100 and the signal processing wafer are bonded, the photosensitive wafer 100 and the signal processing wafer are used to form a 3D stacked back-illuminated CMOS image sensor. For this purpose, the image sensor chip is a CMOS image sensor chip.

The photosensitive wafer 100 includes a first substrate 110. In this embodiment, the first substrate 110 is a silicon substrate. In other embodiments, the material of the first substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

With reference to FIG4 , the photosensitive wafer 100 includes a plurality of first chip regions 100a, the first chip region 100a includes a first chip internal region (not shown) and a first guard ring region 100s surrounding the first chip internal region, and a first dicing region 100b surrounds the plurality of first chip regions. When the photosensitive wafer 100 is subsequently diced, it is necessary to perform cutting in the X direction and the Y direction along the first dicing region 100b between the first chip regions 100a, so as to obtain a single image sensor chip.

Various CMOS devices are formed in the internal area of the first chip, including but not limited to transistors and photodiodes, etc. A first interconnection structure (not shown) located in the first dielectric layer 120 is also formed in the internal area of the first chip, and the first interconnection structure includes a first interconnection layer structure 130 composed of multiple layers of interconnection lines and a first through-hole structure (not shown) for connecting each layer of interconnection lines, and the first interconnection structure is used to achieve electrical connection with the CMOS devices in the photosensitive wafer 100.

During the manufacturing process of the photosensitive wafer 100, while the first interconnection structure is formed in the first chip internal area, the first interconnection structure is also formed in the first guard ring area 100s. Therefore, the first guard ring area 100s includes a first interconnection layer structure 130 located in the first dielectric layer 120, and the first interconnection layer structure 130 includes a first top-layer interconnection line 132. The first interconnection layer structure 130 and the first through-hole structure in the first guard ring area 100s are used as a guard ring for the photosensitive wafer 100.

In this embodiment, the first interconnection layer structure 130 further includes: a first interlayer interconnection line 131 located between the first top-layer interconnection line 132 and the first substrate 110 .

Specifically, along the extension direction of the first top-level interconnection line 132, the first top-level interconnection line 132 has a first end p1 facing the first slicing area 100b, and the first interlayer interconnection line 131 has a second end p2 facing the first slicing area 100b, and the second end p2 is located on the side of the first end p1 away from the first slicing area 100b.

The subsequent process also includes: etching at least the first substrate 110 of the first guard ring area 100s and a partial thickness of the first dielectric layer 120 to form an opening that penetrates the first substrate 110 and extends at least into the first dielectric layer 120, and by making the second end p2 be located on a side of the first end p1 away from the first dicing area 100b, in the process of forming the opening, etching of the first interlayer interconnection line 131 is avoided, thereby reducing the process difficulty of forming the opening.

The distance d1 from the second end p2 to the first end p1 should not be too small or too large. If the distance d1 is too small, it is easy to cause the etching process for forming the opening to cause mis-etching of the first interlayer interconnection line 131, or it is easy to cause the opening to fail to expose the first top-layer interconnection line 131, which correspondingly reduces the process window for forming the opening; if the distance d1 is too large, it will cause the width of the first guard ring area 100s to be too large, thereby causing the size of the subsequent package structure to be too large, which is not conducive to improving the chip integration, or it will cause the length of the first interlayer interconnection line 131 to be too small, which will correspondingly increase the process difficulty of forming the first interlayer interconnection line 131. For this reason, in this embodiment, the distance d1 from the second end p2 to the first end p1 is 5 microns to 10 microns.

The first dielectric layer 120 is used to achieve electrical isolation of the first interconnect structure.

The material of the first dielectric layer 120 may be a low-k dielectric material or an ultra-low-k dielectric material, thereby reducing RC delay. In this embodiment, the material of the first dielectric layer 120 is an ultra-low-k dielectric material, and the ultra-low-k dielectric material is SiOCH containing holes.

It should be noted that the method for preparing the photosensitive wafer 100 may be various methods commonly used in the art, which will not be described in detail in this embodiment.

In this embodiment, the packaging method also includes: providing a signal processing wafer 200, wherein the signal processing wafer 200 includes a second substrate 210 and a second dielectric layer 220 located on the second substrate 210; making the first dielectric layer 120 face the second dielectric layer 220, placing the photosensitive wafer 100 upside down on the signal processing wafer 200, and achieving bonding between the photosensitive wafer 100 and the signal processing wafer 200.

The signal processing wafer 200 has a plurality of signal processing chips therein, and the signal processing chips are used to process the electrical signals converted from the optical signals. In this embodiment, the signal processing wafer 200 is a logic wafer.

By first bonding the photosensitive wafer 100 to the signal processing wafer 200, the signal processing wafer 200 supports the photosensitive wafer 100. In the subsequent process, the signal processing wafer 200 can improve the mechanical strength of the photosensitive wafer 100 and reduce the probability of the photosensitive wafer 100 breaking, thereby improving the reliability of the formed packaging structure.

In this embodiment, the signal processing wafer 200 and the photosensitive wafer 100 are bonded by a bonding process. Specifically, the bonding process can be a fusion bonding process. By adopting the fusion bonding process, the signal processing wafer 200 and the photosensitive wafer 100 are bonded by Si-O bonds, thereby improving the bonding strength of the signal processing wafer 200 and the photosensitive wafer 100.

In this embodiment, the size of the signal processing wafer 200 is consistent with the size of the photosensitive wafer 100. Accordingly, in conjunction with reference to FIG5, a partial top view of the signal processing wafer 200 of this embodiment is shown. The signal processing wafer 200 includes a plurality of second chip regions 200a, and the second chip region 200a includes a second chip internal region (not shown) and a second guard ring region 200s surrounding the second chip internal region (as shown in FIG7). The plurality of second chip regions 200a are surrounded by second dicing regions 200b. When the signal processing wafer 200 is subsequently diced, it is necessary to cut along the second dicing regions 200b between the second chip regions 200a in the X direction and the Y direction to obtain a single signal processing chip.

In this embodiment, the second chip internal region corresponds to the first chip internal region, the second guard ring region 200s corresponds to the first guard ring region 100s, and the second scribing region 200b corresponds to the first scribing region 100b.

As shown in FIG7 , in this embodiment, the second guard ring region 200s includes a second interconnect layer structure 230 located in the second dielectric layer 220, and the second interconnect layer structure 230 includes a second top interconnect line 232, and the second top interconnect line 232 corresponds to the position of the first top interconnect line 132. In other words, the projection of the first top interconnect line 132 on the first substrate 110 is close to or has an overlapping portion with the projection of the second top interconnect line 232 on the first substrate 110, so that the subsequently formed through hole can expose the first top interconnect line 132 and the second top interconnect line 232 at the same time, and further connect the protection plug formed in the opening to the first top interconnect line 132 and the second top interconnect line 232.

Specifically, the second guard ring region 200s is formed with a second interconnect structure (not labeled) located in the second dielectric layer 220, the second interconnect structure includes a second interconnect layer structure 230 composed of multiple layers of interconnect lines and a second through-hole structure (not labeled) for connecting each layer of interconnect lines, and the second interconnect structure is used to achieve electrical connection with the CMOS device in the signal processing wafer 200. The second top-layer interconnect line 232 refers to: the interconnect line in the second interconnect layer structure 230 that is farthest from the second substrate 210.

It should be noted that, during the manufacturing process of the signal processing wafer 200, an etch stop layer (not shown) is usually formed on the top of the second top interconnect line 232, and the etch stop layer is used to define the etching stop position during the subsequent etching of the second dielectric layer 220 above the second top interconnect line 232. Specifically, the material of the etch stop layer is usually silicon nitride.

In this embodiment, the second interconnection layer structure 230 further includes: a second interlayer interconnection line 231 located between the second top-layer interconnection line 232 and the second substrate 210 .

In this embodiment, the second interconnect layer structure 230 and the second through-hole structure in the second guard ring region 200 s are used as a guard ring of the signal processing wafer 200 .

For the description of the second substrate 210, the second dielectric layer 220 and the second interconnect layer structure 230, reference may be made to the corresponding description of the photosensitive wafer 100, and the method for preparing the signal processing wafer 200 may be selected from various methods commonly used in the art, which will not be repeated here.

In this embodiment, along the extension direction of the first top-layer interconnection line 132 , the second top-layer interconnection line 232 has a third end p3 facing the first dicing region 100 b , and the first end p1 is located on a side of the third end p3 away from the first dicing region 100 b .

By locating the first end p1 on a side of the third end p3 away from the first dicing area 100b, etching of the first top-layer interconnection line 132 can be avoided during the subsequent etching process for forming a through hole, making it easy to expose the second top-layer interconnection line 232 through the through hole, thereby reducing the process difficulty of forming the through hole.

It should be noted that after the photosensitive wafer 100 is bonded to the signal processing wafer 200 , the process further includes: performing a grinding process on the surface of the first substrate 110 that is opposite to the first dielectric layer 120 .

By first performing the thinning process, the thickness of the first substrate 110 is reduced, thereby reducing the difficulty of subsequent etching for forming openings.

Specifically, the thinning process can be performed by grinding or wet etching.

With reference to Figures 8 to 12, along the direction from the first substrate 110 to the first dielectric layer 120, at least the first substrate 110 in the first guard ring area 100s (as shown in Figure 7) and a partial thickness of the first dielectric layer 120 are etched to form an opening 540 (as shown in Figure 12) that penetrates the first substrate 110 and extends at least into the first dielectric layer 120. The opening 540 is located on a side of the first top-layer interconnect line 132 close to the first dicing area 100b (as shown in Figure 7), and the opening 540 exposes the first top-layer interconnect line 132.

The opening 540 is used to provide a space for the subsequent formation of a protection plug, so as to achieve the connection between the protection plug and the first top-layer interconnection line 132. The protection plug is used to protect the effective circuit in the internal area of the first chip.

In this embodiment, the opening 540 exposes a portion of the surface of the first top-layer interconnection line 132. The process of forming the opening 540 generally includes an etching process, during which the surface of the first top-layer interconnection line 132 facing the first substrate 110 is used to define an etching stop position, thereby improving the over-etching problem of the first dielectric layer 120.

However, the length d6 (as shown in FIG. 12 ) of the first top-layer interconnection line 132 exposed by the opening 540 should not be too small or too large. If the length d6 is too small, the opening 540 will easily expose only the first dielectric layer 120 on one side of the first top-layer interconnection line 132, which will correspondingly reduce the process window for forming the opening 540; if the length d5 is too large, the etching process for forming the opening 540 will easily cause the first interlayer interconnection line 131 to be etched by mistake, or the width of the first guard ring area 100s will be too large. For this reason, in this embodiment, the length d6 of the first top-layer interconnection line 132 exposed by the opening 540 is 0.5 microns to 2 microns.

In this embodiment, in the step of forming the opening 540, the first substrate 110, the first dielectric layer 120 of the first guard ring area 100s and the partial thickness second dielectric layer 220 of the second guard ring area 200s (as shown in FIG. 7) are etched in sequence, and the opening 540 also exposes the second top-layer interconnect line 232.

By exposing the second top-layer interconnection line 232 through the opening 540, the protection plug subsequently formed in the opening 540 can be connected to the second top-layer interconnection line 232, so that the internal area of the first chip (not shown) is located in a closed cavity, so as to further improve the protection effect of the protection plug on the effective circuit of the internal area of the first chip, thereby further improving the performance of the image sensor.

To this end, in the step of forming the opening 540, the opening 540 includes a groove 520 (as shown in FIG. 12 ) and a through hole 530 (as shown in FIG. 12 ) that penetrate each other. The groove 520 penetrates the first substrate 110 and the first dielectric layer 120 above the first top-layer interconnection line 132, and the groove 520 exposes a portion of the surface of the first top-layer interconnection line 132; the through hole 530 penetrates the remaining first dielectric layer 120 at the bottom of the groove 520 and the second dielectric layer 220 above the second top-layer interconnection line 232, and the through hole 530 is located on one side of the first top-layer interconnection line 132 and is isolated from the first top-layer interconnection line 132. In the direction parallel to the surface of the first substrate 110, the line width of the through hole 530 is smaller than the line width of the groove 520.

The through hole 530 is located at one side of the first top interconnect line 132 and isolated from the first top interconnect line 132 , thereby providing a larger process window for forming the through hole 530 and reducing the probability of the first top interconnect line 132 being mistakenly etched.

Moreover, the through hole 530 penetrates the remaining first dielectric layer 120 at the bottom of the groove 520 and the second dielectric layer 220 above the second top-layer interconnection line 232, that is, the projection of the through hole 530 on the second top-layer interconnection line 232 is located inside the second top-layer interconnection line 232. Therefore, during the etching process for forming the through hole 530, the surface of the etch stop layer on the top of the second top-layer interconnection line 232 is used to define the etching stop position, so that the dimensions and morphologies of the opening 540 can meet the process requirements; moreover, it is beneficial to improve the sealing of the formed protection plug, thereby further improving the protection effect of the protection plug on the effective circuit in the internal area of the first chip; in addition, it can also avoid the problem of the second protection ring area 200s being too large in width.

It should be noted that the bottom opening size d7 of the groove 520 should not be too small or too large. If the bottom opening size d7 of the groove 520 is too small, on the one hand, the width of the subsequent protection plug located in the groove 520 is too small, which is easy to reduce the protection performance of the protection plug. On the other hand, it is easy to increase the process difficulty of forming the through hole 530, and it is also easy to cause the top opening size d8 of the through hole 530 to be too small, which is easy to cause the width of the subsequent protection plug located in the through hole 530 to be too small, which is easy to reduce the protection performance of the protection plug; if the bottom opening size d7 of the groove 520 is too large, it is easy to cause the width of the first protection ring area 100s and the second protection ring area 200s to be too large, which is not conducive to improving the integration of the chip. For this reason, in this embodiment, the bottom opening size d7 of the groove 520 is 2 microns to 5 microns.

It should also be noted that the top opening size d8 of the through hole 530 should not be too small or too large. If the top opening size d8 of the through hole 530 is too small, it will not only increase the process difficulty of forming the through hole 530, but also reduce the protection performance of the subsequent protection plug located in the through hole 530; if the top opening size d8 of the through hole 530 is too large, it will easily cause the width of the first protection ring area 100s and the second protection ring area 200s to be too large, thereby causing the size of the packaging structure to be too large. For this reason, in this embodiment, the top opening size d8 of the through hole 530 is 1 micron to 3 microns.

In addition, on the side away from the first top interconnection line 132, the width d9 of the first dielectric layer 120 at the bottom of the groove 520 should not be too small or too large. If the width d9 is too small, it is easy to increase the difficulty of controlling the overlay accuracy, and the process window for forming the groove 520 or the through hole 530 will be reduced accordingly; if the width d9 is too large, the width of the first guard ring area 100s and the second guard ring area 200s will be too large, which will lead to an oversized size of the packaging structure. For this reason, in this embodiment, on the side away from the first top interconnection line 132, the width d9 of the first dielectric layer 120 at the bottom of the groove 520 is 1 micron to 3 microns.

In this embodiment, a plasma dry etching process is used to form the opening 540 . The plasma dry etching process is an anisotropic etching process, which is beneficial to improving the morphology quality of the cross section of the opening 540 .

The steps of forming the opening 540 are described in detail below with reference to the accompanying drawings.

8 , the first substrate 110 in the first guard ring region 100 s (as shown in FIG. 7 ) is etched to form an initial trench 115 in the first substrate 110 .

The initial trench 115 is used to prepare for subsequent trench formation.

By forming the initial trench 115 first, it is helpful to reduce the difficulty of the subsequent etching process for forming through holes and trenches.

Specifically, the step of forming the initial trench 115 includes: forming a patterned first photoresist layer 410 on the first substrate 110; and etching the first substrate 110 using the first photoresist layer 410 as a mask.

A first mask opening 430 is formed in the first photoresist layer 410 , and the first mask opening 430 is used to define the shape, size and position of subsequent trenches.

In this embodiment, after the initial trench 115 is formed, the process further includes: removing the first photoresist layer 410 .

With reference to FIG. 9 , after removing the first photoresist layer 410 , the process further includes: forming an isolation layer 160 conformally covering the sidewalls and the bottom of the initial trench 115 , wherein the isolation layer 160 also covers the first substrate 110 .

After the opening is subsequently formed, the metal material formed in the opening is used as a protection plug. Therefore, the protection plug has conductivity, the first substrate 110 also has conductivity, and the isolation layer 160 is used to achieve electrical isolation between the protection plug and the first substrate 110, thereby ensuring the normal performance of the packaging structure.

In this embodiment, the material of the isolation layer 160 is silicon dioxide. Silicon dioxide is a commonly used insulating material with low process cost and low stress, so that the adhesion between the isolation layer 160 and the first substrate 110 and between the isolation layer 160 and the protection plug is good; in addition, by using silicon dioxide, the isolation layer 160 is easy to be etched in the subsequent etching process.

In this embodiment, an atomic layer deposition process is used to form the isolation layer 160. The isolation layer 160 is deposited in the form of an atomic layer, which is beneficial to improving the thickness uniformity of the isolation layer 160 and the structural uniformity in the isolation layer 160, and the isolation layer 160 has good conformal coverage.

The thickness of the isolation layer 160 should not be too small or too large. If the thickness of the isolation layer 160 is too small, it is easy to cause the electrical isolation effect of the isolation layer 160 to be poor; if the thickness of the isolation layer 160 is too large, it is easy to cause the width of the first guard ring area 100s and the second guard ring area 200s to be too large, thereby causing the size of the packaging structure to be too large. For this reason, in this embodiment, the thickness of the isolation layer 160 is to For example, the thickness of the isolation layer 160 is or

Referring to Figure 10, the first dielectric layer 120 at the bottom of the initial groove 115 (as shown in Figure 9) and the second dielectric layer 220 above the second top-level interconnect line 232 are etched in sequence to form an initial through hole 116, which is located on one side of the first top-level interconnect line 232.

A portion of the initial through holes 116 is used as through holes.

By forming the initial through hole 116 first, the difficulty of the subsequent trench formation process is reduced.

Specifically, a second photoresist layer 460 is formed to fill the initial groove 115, and the second photoresist layer 460 also covers the first substrate 110; a second mask opening 465 is formed in the second photoresist layer 460 through a photolithography process, and the second mask opening 465 exposes a portion of the bottom of the initial groove 115; using the second photoresist layer 460 as a mask, the first dielectric layer 120 and the second dielectric layer 220 above the second top-layer interconnect line 232 are etched in sequence to form the initial through hole 116.

The second mask opening 465 is used to define the size, position and shape of the subsequent through hole. To this end, in this embodiment, the size of the second mask opening 465 is smaller than the size of the first mask opening 430 (as shown in FIG. 8 ).

It should be noted that, during the manufacturing process of the signal processing wafer 200, an etch stop layer (not shown) is usually formed on the top of the second top-layer interconnect line 232. Therefore, in the process of forming the initial through hole 116, the etch stop layer on the top of the second top-layer interconnect line 232 is used to define the stop position of the etching process, that is, a portion of the surface of the etch stop layer is exposed at the bottom of the initial through hole 116.

In this embodiment, after the initial through hole 116 is formed, the process further includes: removing the second photoresist layer 460 .

11 , a protection layer 470 is filled in the initial through hole 116 (as shown in FIG. 10 ), and the top of the protection layer 470 is lower than the bottom of the initial trench 115 (as shown in FIG. 8 ).

In the subsequent step of forming a groove by etching process, the protection layer 470 is used to protect the second top-layer interconnection line 232 at the bottom of the initial through hole 116, and is also used to protect the side wall of the initial through hole 116, so as to ensure the morphology quality of the subsequent through hole.

Therefore, the material of the protection layer 470 has good filling properties, the protection layer 470 is easy to be etched, and the protection layer 470 is easy to be removed from the initial through hole 116 later.

In this embodiment, the material of the protection layer 470 is a BARC (bottom anti-reflective coating) material. In other embodiments, the material of the protection layer may also be an ODL (organic dielectric layer) material.

In this embodiment, the top of the protective layer 470 is lower than the bottom of the initial trench 115, so as to avoid the protective layer 470 having an adverse effect on the etching process when the first dielectric layer 120 exposed by the initial trench 115 is subsequently etched. The distance from the top of the protective layer 470 to the bottom of the initial trench 115 can be determined according to actual process conditions.

Specifically, the steps of forming the protective layer 470 include: filling a protective material layer in the initial groove 115 and the initial through hole 116, and the protective material layer also covers the isolation layer 160; performing a planarization treatment on the protective material layer to remove the protective material layer above the surface of the isolation layer 160; after the planarization treatment, forming a third photoresist layer 480 covering the first substrate 110 and the isolation layer 160, and the third photoresist layer 480 exposes the protective material layer; after forming the third photoresist layer 480, etching back the remaining protective material layer so that the top of the remaining protective material layer is lower than the bottom of the initial groove 115, and retaining the protective material layer in the initial through hole 116 as the protective layer 470.

The third photoresist layer 480 is used to protect the isolation layer 160 during the process of etching back the remaining protective material layer, and is also used as an etching mask for subsequent etching of the first dielectric layer 110 .

Wherein, by forming the third photoresist layer 480 after the planarization treatment, a planar surface is provided for the formation of the third photoresist layer 480 .

Referring to Figure 12, after the protection layer 470 (as shown in Figure 11) is formed, the first dielectric layer 120 is etched along the initial groove 115 (as shown in Figure 11), and a groove 520 exposing the first top-layer interconnect line 132 is formed in the first substrate 110 and the first dielectric layer 120, and the remaining initial through hole 116 (as shown in Figure 10) connected to the groove 520 serves as the through hole 530, and the groove 520 and the through hole 530 are used to form the opening 540.

Specifically, the first dielectric layer 120 exposed by the initial trench 115 is etched using the third photoresist layer 480 (as shown in FIG. 11 ) as a mask.

In the process of forming the groove 520 , the top of the first top-layer interconnection line 132 is used to define the stop position of the etching process. Therefore, the bottom of the groove 520 exposes a portion of the surface of the first top-layer interconnection line 132 .

It should be noted that an etch stop layer (not shown) is formed on the top of the second top-layer interconnect line 232, and the etch stop layer is exposed at the bottom of the initial through hole 116. Therefore, before exposing the first top-layer interconnect line 132, it also includes: removing the protective layer 470 to expose the etch stop layer, so that the etch stop layer is etched while continuing to etch the remaining first dielectric layer 120. Accordingly, after the groove 520 is formed, the through hole 530 can expose the second top-layer interconnect line 232.

It should also be noted that after forming the opening 540, the forming method further includes: removing the third photoresist layer 480. In this embodiment, the third photoresist layer 480 is removed by an ashing process.

In addition, in other embodiments, according to actual conditions, the groove may also expose the sidewall of the first top-layer interconnection line facing the first dicing area, and the bottom of the groove may expose a portion of the first dielectric layer in contact with the first top-layer interconnection line.

13 , a protection plug 300 is formed in the opening 540 (shown in FIG. 12 ).

The protection plug 300 can protect the first chip internal area of the photosensitive wafer 100. On the one hand, when the photosensitive wafer 100 is subsequently cut along the first dicing area 100b, the cracks caused by the damage to the first dicing area 100b are shielded by the protection plug 300, thereby reducing the probability of the cracks extending along the first substrate 110 to the first chip internal area, which correspondingly reduces the impact of the cutting stress on the effective circuit in the first chip internal area; on the other hand, after the cutting is completed, the protection plug 300 can also prevent moisture from penetrating into the first chip internal area through the first substrate 110, which correspondingly reduces the probability of the effective circuit in the first chip internal area being damaged. In summary, the protection plug 300 improves the packaging yield and reliability, thereby improving the performance of the image sensor.

Moreover, since the opening 540 also exposes the second top-layer interconnection line 232, the protection plug 300 is connected to the first top-layer interconnection line 132 and the second top-layer interconnection line 232, so that the internal area of the first chip (not shown) is located in a closed cavity, so as to further improve the protection effect of the protection plug 300 on the effective circuit in the internal area of the first chip, thereby further improving the performance of the image sensor.

Specifically, the step of forming the protection plug 300 includes: filling the opening 540 with metal material, the filled metal material also covering the isolation layer 160 ; flattening the metal material, removing the metal material above the top surface of the isolation layer 160 , and retaining the remaining metal material as the protection plug 300 .

The hardness and density of the metal material are relatively high, so the shielding effect of the protection plug 300 on the cutting stress and the barrier effect on moisture are improved, thereby improving the protection effect of the protection plug 300 on the internal area of the first chip. In addition, the protection plug 300 is connected to the first top interconnection line 132 and the second top interconnection line 232. By selecting the metal material, the adhesion of the protection plug 300 to the first top interconnection line 132 and the second top interconnection line 232 is correspondingly improved.

The material of the protection plug 300 may be a metal material commonly used in the art. In this embodiment, the material of the protection plug 300 is copper. Copper has filling properties and is a commonly used material in the current back-end process, which is conducive to improving the compatibility of the formation process of the protection plug 300.

Continuing to refer to FIG. 13 , it should be noted that after forming the protection plug 300 , the packaging method further includes: forming a barrier layer 140 covering the first substrate 110 and the protection plug 300 ; and forming a passivation layer 150 covering the barrier layer 140 .

The passivation layer is used to protect the protection plug 300 and prevent the protection plug 300 from being oxidized due to being exposed to the outside, so the material of the passivation layer is an insulating material. In this embodiment, the material of the passivation layer is silicon dioxide.

In this embodiment, in order to ensure the protection effect of the passivation layer 150 and avoid the problem of excessive thickness of the packaging structure, the thickness of the passivation layer 150 is to For example, the thickness of the passivation layer 150 is or

In this embodiment, the isolation layer 160 is also located on the surface of the first substrate 110 facing away from the first dielectric layer 110 , so the barrier layer 140 covers the isolation layer 160 and the protection plug 300 .

The material of the protection plug 300 is a metal material, and the barrier layer 140 is used to prevent the diffusion of the metal material in the protection plug 300, thereby reducing defects and preventing the surface of the packaging structure from being conductive, thereby ensuring the normal performance of the packaging structure.

In this embodiment, the material of the barrier layer 140 is silicon nitride. Silicon nitride has a high density, so that the barrier effect of the barrier layer 140 is better.

In this embodiment, in order to ensure the barrier effect of the barrier layer 140 and avoid the problem of excessive thickness of the packaging structure, the thickness of the barrier layer 140 is to For example, the thickness of the barrier layer 140 is or

In this embodiment, the barrier layer 140 and the passivation layer 150 are formed by a chemical vapor deposition process.

Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims (29)

1. A package structure, comprising:

The photosensitive wafer comprises a first substrate and a first dielectric layer positioned on the first substrate, wherein the photosensitive wafer comprises a first protection ring area and a scribing area surrounding the first protection ring area, and the first protection ring area comprises a first top layer interconnection line positioned in the first dielectric layer;

the protection plug penetrates through the first substrate of the first protection ring area and at least extends into the first dielectric layer, the protection plug is located on one side, close to the scribing area, of the first top layer interconnection line, the protection plug is connected with the first top layer interconnection line, and the protection plug is used as a protection ring of the photosensitive wafer; the material of the protection plug is a metal material;

The protection plug includes: a first plug portion and a second plug portion connected to the first plug portion and located below the first plug portion; the linewidth dimension of the second plug portion is smaller than the linewidth dimension of the first plug portion in a direction parallel to the first substrate surface; the first plug part and the first top layer interconnection line are provided with an overlapping part and are in contact with each other; the second plug portion is located at one side of the first top-layer interconnection line and isolated from the first top-layer interconnection line.

2. The package structure of claim 1, wherein the first guard ring region further comprises: an interlayer interconnection line between the first top layer interconnection line and the first substrate;

The first top layer interconnection line is provided with a first end part facing the scribing area along the extending direction of the first top layer interconnection line, the interlayer interconnection line is provided with a second end part facing the scribing area, and the second end part is positioned on one side of the first end part away from the scribing area.

3. The package structure of claim 2, wherein a distance from the second end to the first end is 5 microns to 10 microns.

4. The package structure of claim 1, wherein a length of a portion of the first top layer interconnect line that coincides with the protection plug is 0.5 micrometers to 2 micrometers.

5. The package structure of claim 1, wherein the package structure further comprises: the signal processing wafer is bonded with the photosensitive wafer and comprises a second substrate and a second dielectric layer positioned on the second substrate, and the second dielectric layer faces the first dielectric layer.

6. The package structure of claim 5, wherein the signal processing wafer comprises a second guard ring region, the second guard ring region corresponding to a location of the first guard ring region, the second guard ring region comprising a second top layer interconnect line in the second dielectric layer, and the second top layer interconnect line corresponding to a location of the first top layer interconnect line;

The protection plug penetrates through the first substrate and the first dielectric layer of the first protection ring area and extends into the second dielectric layer of the second protection ring area, and the protection plug is further connected with the second top-layer interconnection line.

7. The package structure of claim 6, wherein the first plug portion extends through the first substrate and a first dielectric layer over the first top-level interconnect line; the second plug part penetrates through the residual first dielectric layer below the first plug part and the second dielectric layer above the second top-layer interconnection line;

The projection of the second plug portion on the second top-layer interconnection line is located in the second top-layer interconnection line.

8. The package structure of claim 7, wherein a bottom linewidth dimension of the first plug portion is 2 microns to 5 microns.

9. The package structure of claim 7, wherein a top linewidth dimension of the second plug portion is 1 micron to 3 microns.

10. The package structure of claim 7, wherein the first top layer interconnect line has a first end portion facing the scribe area and the second top layer interconnect line has a third end portion facing the scribe area along an extension direction of the first top layer interconnect line, the first end portion being located on a side of the third end portion away from the scribe area.

11. The package structure of claim 7, wherein the first plug portion bottom has a first boundary on a side away from the first top layer interconnect line, the second plug portion top has a second boundary on a side away from the first top layer interconnect line, and a distance from the first boundary to the second boundary is 1 micron to 3 microns.

12. The package structure of claim 1, wherein the metal material is copper.

13. The package structure of claim 1, wherein the package structure further comprises: and an isolation layer between the protection plug and the first substrate.

14. The package structure of claim 13, wherein the material of the isolation layer is silicon dioxide.

15. The package structure of claim 13, wherein the thickness of the isolation layer isTo the point of

16. The package structure of claim 1, wherein the package structure further comprises: a barrier layer covering the first substrate and the protective plug; and the passivation layer covers the barrier layer.

17. The package structure of claim 16, wherein the material of the barrier layer is silicon nitride and the material of the passivation layer is silicon dioxide.

18. The package structure of claim 16, wherein the barrier layer has a thickness ofTo the point of

19. The package structure of claim 1, wherein the package structure is a 3D stacked backside illuminated CMOS image sensor.

20. The package structure of claim 5, wherein the signal processing wafer is a logic wafer.

21. A method of packaging, comprising:

Providing a photosensitive wafer, wherein the photosensitive wafer comprises a first substrate and a first dielectric layer positioned on the first substrate, the photosensitive wafer comprises a first protection ring area and a scribing area surrounding the first protection ring area, and the first protection ring area comprises a first top layer interconnection line positioned in the first dielectric layer;

Etching at least the first substrate of the first protection ring region and a first dielectric layer with partial thickness along the direction that the first substrate points to the first dielectric layer to form an opening penetrating through the first substrate and extending at least into the first dielectric layer, wherein the opening is positioned at one side of the first top layer interconnection line, which is close to the scribing region, and the opening exposes a partial surface of the first top layer interconnection line;

Filling a metal material into the opening to form a protection plug, wherein the protection plug is used as a protection ring of the photosensitive wafer; the protection plug includes: a first plug portion and a second plug portion connected to the first plug portion and located below the first plug portion; the linewidth dimension of the second plug portion is smaller than the linewidth dimension of the first plug portion in a direction parallel to the first substrate surface; the first plug part and the first top layer interconnection line are provided with an overlapping part and are in contact with each other; the second plug portion is located at one side of the first top-layer interconnection line and isolated from the first top-layer interconnection line.

22. The packaging method of claim 21, wherein the packaging method further comprises: providing a signal processing wafer, wherein the signal processing wafer comprises a second substrate and a second dielectric layer positioned on the second substrate;

And leading the first dielectric layer to face the second dielectric layer, reversely placing the photosensitive wafer on the signal processing wafer, and bonding the photosensitive wafer and the signal processing wafer.

23. The method of packaging of claim 22, wherein in the step of providing a signal processing wafer, the signal processing wafer includes a second guard ring region including a second top layer interconnect line in the second dielectric layer;

After the bonding of the photosensitive wafer and the signal processing wafer is realized, the position of the second top layer interconnection line corresponds to the position of the first top layer interconnection line, and the position of the second protection ring area corresponds to the position of the first protection ring area;

And in the step of forming the opening, etching the first substrate, the first dielectric layer and the second dielectric layer of the second protection ring region in sequence, wherein the second dielectric layer is partially thick in the first protection ring region, and the opening also exposes the second top layer interconnection line.

24. The packaging method of claim 23, wherein in the step of forming the opening, the opening includes a trench and a via that are mutually penetrated;

The trench penetrates through the first substrate and the first dielectric layer above the first top-layer interconnection line, and the trench exposes part of the surface of the first top-layer interconnection line;

The through hole penetrates through the remaining first dielectric layer at the bottom of the groove and the second dielectric layer above the second top-layer interconnection line, the through hole is located at one side of the first top-layer interconnection line and isolated from the first top-layer interconnection line, and the line width dimension of the through hole is smaller than that of the groove in the direction parallel to the surface of the first substrate.

25. The packaging method of claim 24, wherein the step of forming the opening comprises: etching a first substrate of the first protection ring area, and forming an initial groove in the first substrate;

Sequentially etching a first dielectric layer at the bottom of the initial groove part and a second dielectric layer above the second top layer interconnection line to form an initial through hole, wherein the initial through hole is positioned at one side of the first top layer interconnection line;

forming a protective layer in the initial through hole, wherein the top of the protective layer is lower than the bottom of the initial groove;

after the protective layer is formed, etching the first dielectric layer along the initial groove, forming a groove exposing the first top layer interconnection line in the first substrate and the first dielectric layer, and taking the residual initial through holes communicated with the groove as the through holes.

26. The packaging method of claim 25, wherein after forming the initial trench and before forming the initial via, further comprising: an isolation layer is formed conformally covering the initial trench sidewalls and bottom, the isolation layer also covering the first substrate.

27. The packaging method of claim 21, further comprising, after forming a protective plug in the opening: forming a barrier layer covering the first substrate and the protective plug; and forming a passivation layer covering the barrier layer.

28. The packaging method of claim 21, wherein the openings are formed by etching using a plasma dry etching process.

29. The packaging method of claim 21, further comprising, prior to forming the opening: and thinning the surface of the first substrate, which is opposite to the first dielectric layer.