CN112087131B - Charge pump control circuit and battery control circuit - Google Patents
Charge pump control circuit and battery control circuit Download PDFInfo
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- CN112087131B CN112087131B CN202010522112.9A CN202010522112A CN112087131B CN 112087131 B CN112087131 B CN 112087131B CN 202010522112 A CN202010522112 A CN 202010522112A CN 112087131 B CN112087131 B CN 112087131B
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- 238000006243 chemical reaction Methods 0.000 claims description 51
- 238000001514 detection method Methods 0.000 claims description 31
- 238000010586 diagram Methods 0.000 description 18
- 230000000630 rising effect Effects 0.000 description 6
- 238000003708 edge detection Methods 0.000 description 4
- 230000007704 transition Effects 0.000 description 3
- 238000007599 discharging Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
- H02J7/00711—Regulation of charging or discharging current or voltage with introduction of pulses during the charging process
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/00302—Overcharge protection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/00306—Overdischarge protection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/02—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries for charging batteries from AC mains by converters
- H02J7/04—Regulation of charging current or voltage
- H02J7/06—Regulation of charging current or voltage using discharge tubes or semiconductor devices
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/20—Charging or discharging characterised by the power electronics converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Electronic Switches (AREA)
Abstract
The invention provides a charge pump control circuit and a battery control circuit. The charge pump control circuit of the present invention includes: an oscillator that supplies a clock for driving each of a charge pump driver that supplies a 1 st gate voltage to a discharge transistor that controls discharge from a battery and a charge pump driver that supplies a 2 nd gate voltage to a charge transistor that controls charging of the battery; and a drive control circuit that uses the lower one of the 1 st gate voltage and the 2 nd gate voltage as a control target voltage, and controls generation of a clock by the oscillator in accordance with the control target voltage.
Description
Technical Field
The present invention relates to a charge pump control circuit and a battery control circuit.
Background
Conventionally, a battery device is attached to a portable device as a power source for portable operation of the portable device.
The battery device is equipped with a rechargeable battery capable of obtaining a desired battery voltage and a battery control circuit for controlling charge and discharge of the battery.
Fig. 9 is a circuit diagram showing a battery device having a battery control circuit of the conventional example. The battery device 1100 is constituted by a battery 242 and a battery control device 1200. The battery control apparatus 1200 supplies a charging current from the charger to the battery 242 when the connected connection device 930 is a charger, and supplies a driving current (discharging current) from the battery 242 to the load when the connected connection device 930 is a load.
In fig. 9, the charge transistor 216 and the discharge transistor 218 are each n-channel MOS transistors.
It is necessary to boost the gate voltages of the charge transistor 216 and the discharge transistor 218, respectively, so that the gate-source voltages Vgs of the charge transistor 216 and the discharge transistor 218, respectively, exceed the threshold voltage Vth and reduce the channel resistance.
Therefore, the battery control device 1200 includes a charge pump control circuit 1300, and the charge pump control circuit 1300 controls the charge pump circuits 910 and 1110, respectively.
The charge pump circuit 910 boosts the gate voltage of the discharge transistor 218, and on the other hand, the charge pump circuit 1110 boosts the gate voltage of the charge transistor 216.
The V/I conversion circuit 1130 converts the gate voltage of the charge transistor 216 into a sense current and outputs it to the oscillator 906.
In addition, the V/I conversion circuit 904 converts the gate voltage of the discharge transistor 218 into a sense current, and outputs it to the oscillator 906.
The oscillator 906 adjusts the frequency of clocks for driving the charge pump circuits 910 and 1110, respectively, in accordance with the currents obtained by combining the sense currents of the V/I conversion circuits 904 and 1130, respectively, so that the gate voltages of the charge transistor 216 and the discharge transistor 218 are maintained at predetermined voltages.
Accordingly, the gate voltages of the charge transistor 216 and the discharge transistor 218 in the normal operation at the time of charging and discharging the battery 242 are maintained at predetermined voltages equal to or higher than the threshold value.
In addition, a protection element (not shown) is generally provided between the source and the gate of each of the charge transistor 216 and the discharge transistor 218 to prevent dielectric breakdown due to excessive rise of the gate voltage.
Prior art literature
Patent literature
Patent document 1: japanese patent No. 6018749
However, in patent document 1, the impedance of the protection element of each of the charge transistor 216 and the discharge transistor 218 needs to be the same, but the impedance is different because of a general process deviation.
On the other hand, since the respective sense currents of the charge transistor 216 and the discharge transistor 218 are synthesized to generate the frequency of the clock oscillated by the synthesized current, the oscillator 906 oscillates the clock of the frequency corresponding to the averaged sense current.
Therefore, the gate voltages of the charge transistor 216 and the discharge transistor 218 do not become predetermined voltages corresponding to the frequency of the clock.
That is, the gate voltage of the protective element of the charge transistor 216 and the discharge transistor 218 having a lower impedance is lower than a predetermined voltage, and the channel resistance is higher than a desired resistance, or the transistor is turned off, so that a necessary charge current or discharge current cannot be supplied.
Disclosure of Invention
The present invention aims to provide a charge pump control circuit and a battery control circuit, which control the driving of the charge pump circuit in such a way that the gate voltage of the lower one of the resistances of the protection elements becomes a prescribed voltage even if the resistances of the protection elements provided in the gates of the charge transistor and the discharge transistor are different.
The charge pump control circuit according to an embodiment of the present invention is characterized by comprising: a 1 st charge pump driver that supplies a 1 st gate voltage to a discharge transistor that controls discharge from the battery; a 2 nd charge pump driver that provides a 2 nd gate voltage to a charge transistor that controls charging of the battery; an oscillator providing clocks for driving the 1 st charge pump driver and the 2 nd charge pump driver, respectively; and a drive control circuit that uses a lower one of the 1 st gate voltage and the 2 nd gate voltage as a control target voltage, and controls generation of the clock by the oscillator in accordance with the control target voltage.
The battery control circuit according to an embodiment of the present invention is characterized by comprising: a discharge transistor that controls discharge from the battery; a charging transistor that controls charging of the battery; a 1 st voltage conversion circuit that obtains a 1 st gate voltage of the discharge transistor as a 1 st detection voltage corresponding to the 1 st gate voltage; a 2 nd voltage conversion circuit that obtains a 2 nd gate voltage of the charge transistor as a 2 nd detection voltage corresponding to the 2 nd gate voltage; a discharge charge pump driver that supplies the 1 st gate voltage to the discharge transistor; a charge pump driver that supplies the 2 nd gate voltage to the charge transistor; an oscillator providing clocks for driving the discharge charge pump driver and the charge pump driver, respectively; and a drive control circuit that uses a lower one of the 1 st detection voltage and the 2 nd detection voltage as a control target voltage, and controls generation of the clock by the oscillator in accordance with the control target voltage.
According to the present invention, the following charge pump control circuit and battery control circuit can be provided: even if the resistances of the protection elements included in the gates of the charge transistor and the discharge transistor are different, the drive of the charge pump circuit is controlled so that the gate voltage of the lower one of the resistances of the protection elements becomes a predetermined voltage.
Drawings
Fig. 1 is a schematic block diagram showing an example of the structure of a battery device using the charge pump control circuit according to embodiment 1.
Fig. 2 is a circuit diagram showing a configuration example of the switch circuit 51 and the comparator circuit 52 in embodiment 1.
Fig. 3 is a circuit diagram showing a configuration example of the driving circuit 53 in embodiment 1.
Fig. 4 is a circuit diagram showing a configuration example of the 1 st voltage conversion circuit 6 in embodiment 1.
Fig. 5 is a circuit diagram showing a configuration example of the 1 st voltage conversion circuit 6A in embodiment 2.
Fig. 6 is a circuit diagram showing a configuration example of the 1 st voltage conversion circuit 6B in embodiment 2.
Fig. 7 is a schematic block diagram showing a configuration example of a battery device using the charge pump control circuit according to embodiment 3.
Fig. 8 is a block diagram showing a configuration example of oscillator 54C and frequency control circuit 55 in embodiment 3.
Fig. 9 is a circuit diagram showing a battery device having a battery control circuit of the conventional example.
Description of the reference numerals
1. 1C: a battery device;
3: a charge pump driver;
4: a discharge charge pump driver;
5. 5C: a charge pump control circuit;
6: a 1 st voltage conversion circuit;
7: a 2 nd voltage conversion circuit;
10. 10C: a battery control circuit;
11: a discharge transistor;
12: a charging transistor;
20: a battery;
30: a connection device;
51. 51a, 51b: a switching circuit;
51a_1, 51a_2, 51b_1, 51b_2: a switch;
52: a comparison circuit;
53: a driving circuit;
54. 54C: an oscillator;
55: a frequency control circuit;
161. 162: a resistor;
163: an amplifier;
164. 521, 522: a constant current source;
531. 553: an OR circuit;
532: an AND circuit;
551. 552: a rising edge detection circuit;
554: an SR-flip-flop;
555: a delay time generation circuit;
INV: NOT circuit ("NOT" circuit);
n1, N2, N3, P1, P2, P3: and a transistor.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Embodiment 1
Fig. 1 is a schematic block diagram showing an example of the structure of a battery device using the charge pump control circuit according to embodiment 1.
In fig. 1, a battery device 1 includes a battery control circuit 10 and a battery 20. The battery control circuit 10 includes a discharge transistor 11, a charge transistor 12, a charge pump driver 3, a discharge charge pump driver 4, a charge pump control circuit 5, a 1 st voltage conversion circuit 6, and a 2 nd voltage conversion circuit 7. The charge pump control circuit 5 includes a switch circuit 51, a comparator circuit 52, a drive circuit 53, and an oscillator 54. The switch circuit 51, the comparator circuit 52, and the drive circuit 53 constitute a drive control circuit that controls generation of a clock of the oscillator 54.
The discharge transistor 11 is an n-channel MOS transistor, a source is connected to the positive terminal of the connection device 30, a gate is connected to the output terminal of the discharge charge pump driver 4 and the input terminal of the 1 st voltage conversion circuit 6, and a drain is connected to the drain of the charge transistor 12. In addition, a protection element 81 is provided between the source and the gate in the discharge transistor 11.
The charge transistor 12 is an n-channel MOS transistor, and has a source connected to the positive terminal of the battery 20, and a gate connected to the output terminal of the charge pump driver 3 and the input terminal of the 2 nd voltage conversion circuit 7. In addition, a protection element 82 is provided between the source and the gate in the charge transistor 12.
The 1 st input terminal of the charge pump control circuit 5 is connected to the output of the 1 st voltage conversion circuit 6, the 2 nd input terminal is connected to the output terminal of the 2 nd voltage conversion circuit 7, and the output terminal is connected to the input terminals of the charge pump driver 3 and the discharge charge pump driver 4. An output terminal of the charge pump driver 3 is connected to a gate of the charge transistor 12. An output terminal of the discharge charge pump driver 4 is connected to a gate of the discharge transistor 11.
When the charge enable signal en_chg is in the enabled state, the charge pump driver 3 boosts the gate voltage VG2 of the charge transistor 12 from the power supply voltage VDD to a predetermined voltage in accordance with the supplied clock. On the other hand, when the charge enable signal en_chg is in the disabled state, the charge pump driver 3 stops the boosting operation.
When the discharge enable signal en_dsg is in the enabled state, the discharge charge pump driver 4 boosts the gate voltage VG1 of the discharge transistor 11 from the power supply voltage VDD to a predetermined voltage in accordance with the supplied clock. On the other hand, when the discharge enable signal en_dsg is in the disabled state, the discharge charge pump driver 4 stops the boosting operation.
The charge enable signal en_chg is set to an enable state when the power supply voltage VDD is lower than the overcharge voltage, and is set to a disable state when the power supply voltage VDD is equal to or higher than the overcharge voltage.
The discharge enable signal en_dsg is set to a disable state when the power supply voltage VDD is equal to or lower than the overdischarge voltage, and is set to an enable state when the power supply voltage VDD exceeds the overdischarge voltage.
The control of the charge enable signal en_chg and the discharge enable signal en_dsg is performed by a monitor control circuit (not shown) that monitors the power supply voltage VDD of the battery 20.
The 1 st voltage conversion circuit 6 divides the gate voltage VG1 of the input discharge transistor 11 by a predetermined ratio, and outputs the divided voltage as the 1 st detection voltage VDT1 corresponding to the gate voltage VG 1.
The 2 nd voltage conversion circuit 7 divides the gate voltage VG2 of the input charge transistor 12 by a predetermined ratio, and outputs the divided voltage as a 2 nd detection voltage VDT2 corresponding to the gate voltage VG 2.
The charge pump control circuit 5 controls whether or not to clock the charge pump driver 3 and the discharge charge pump driver 4 in accordance with the voltage of the lower one of the 1 st detection voltage VDT1 and the 2 nd detection voltage VDT2 supplied.
In the case where the discharge enable signal en_dsg is in the enabled state, the switching circuit 51 outputs the 1 st detection voltage VDT1 as the 1 st comparison voltage to the comparison circuit 52. On the other hand, in the case where the discharge enable signal en_dsg is in the disabled state, the switching circuit 51 outputs the power supply voltage VDD as the 1 st comparison voltage to the comparison circuit 52.
Further, in a case where the charge enable signal en_chg is in an enabled state, the switching circuit 51 outputs the 2 nd detection voltage VDT2 as the 2 nd comparison voltage to the comparison circuit 52. On the other hand, in the case where the charge enable signal en_chg is in the disabled state, the switching circuit 51 outputs the power supply voltage VDD as the 2 nd comparison voltage to the comparison circuit 52.
The comparison circuit 52 compares each of the 1 st comparison voltage and the 2 nd comparison voltage with the reference voltage Vref. Here, when the voltage of the lower one of the 1 st comparison voltage and the 2 nd comparison voltage is lower than the reference voltage Vref, the comparison circuit 52 sets the drive enable signal to the enable state and outputs the drive enable signal to the drive circuit 53. On the other hand, when the voltage of the lower one of the 1 st comparison voltage and the 2 nd comparison voltage is equal to or higher than the reference voltage Vref, the comparator circuit 52 sets the drive enable signal to the disable state and outputs the disable signal to the drive circuit 53.
In the driving circuit 53, in a case where either one of the discharge enable signal en_dsg and the charge enable signal en_chg is in an enable state and the drive enable signal is in an enable state, the driving signal is output in a drive state.
The oscillator 54 generates a clock with a predetermined frequency and supplies the clock to the charge pump driver 3 and the discharge pump driver 4.
Fig. 2 is a circuit diagram showing a configuration example of the switch circuit 51 and the comparator circuit 52 in embodiment 1.
The switching circuit 51 includes switching circuits 51a and 51b. The switch circuit 51a includes switches 51a_1 and 51a_2. The switch circuit 51b includes switches 51b_1 and 51b_2.
The switches 51a_1 and 51a_2 are connected to the signal line of the charge enable signal en_chg, respectively, to the control terminal TS.
The input terminal TI of the switch 51a_1 is connected TO the signal line of the 2 nd detection voltage VDT2, and the output terminal TO is connected TO the signal line of the 2 nd comparison voltage. The input terminal TI of the switch 51a_2 is connected TO the power supply line of the power supply voltage VDD, and the output terminal TO is connected TO the signal line of the 2 nd comparison voltage.
According to this configuration, in the switch circuit 51a, when the charge enable signal en_chg is in the enable state, the switch 51a_1 is in the on state, the switch 51a_2 is in the off state, and the 2 nd detection voltage VDT2 is output to the comparison circuit 52 as the 2 nd comparison voltage. On the other hand, in the switch circuit 51a, when the charge enable signal en_chg is in the disabled state, the switch 51a_1 is in the off state, the switch 51a_2 is in the on state, and the power supply voltage VDD is output to the comparison circuit 52 as the 2 nd comparison voltage.
The switches 51b_1 and 51b_2 are connected to the signal lines of the charge enable signal en_dsg, respectively, to the control terminal TS.
The input terminal TI of the switch 51b_1 is connected TO the signal line of the 1 st detection voltage VDT1, and the output terminal TO is connected TO the signal line of the 1 st comparison voltage. The input terminal TI of the switch 51b_2 is connected TO the power supply line of the power supply voltage VDD, and the output terminal TO is connected TO the signal line of the 1 st comparison voltage.
According to this configuration, in the switch circuit 51b, when the charge enable signal en_dsg is in the enabled state, the switch 51b_1 is in the on state, the switch 51b_2 is in the off state, and the 1 st detection voltage VDT1 is output to the comparison circuit 52 as the 1 st comparison voltage. On the other hand, in the switching circuit 51b, when the discharge enable signal en_dsg is in the disable state, the switch 51b_1 is in the off state, the switch 51b_2 is in the on state, and the power supply voltage VDD is output to the comparison circuit 52 as the 2 nd comparison voltage.
The comparison circuit 52 includes constant current sources 521 and 522, transistors P1, P2, P3, N1, N2, N3, and a NOT circuit INV.
The transistors P1, P2, and P3 are P-channel type MOS transistors, and the transistors N1, N2, and N3 are N-channel type MOS transistors.
The input terminal TI of the constant current source 521 is connected TO a power supply line of the power supply voltage VDD, and the output terminal TO is connected TO the sources of the transistors P1, P2, and P3.
The constant current source 522 has an input terminal TI connected TO a power supply line of the power supply voltage VDD, and an output terminal TO connected TO a drain of the transistor N3.
The gate of the transistor P1 is connected to the signal line of the 1 st comparison voltage, and the drain is connected to the drain of the transistor N1.
The gate of the transistor P2 is connected to the signal line of the 2 nd comparison voltage, and the drain is connected to the drain of the transistor N1.
The gate of the transistor P3 is applied with the reference voltage Vref, and the drain is connected to the drain and gate of the transistor N2.
The gate of the transistor N1 is connected to the drain and gate of the transistor N2, and the source is connected to a power supply line of a power supply voltage VSS (ground voltage).
The source of the transistor N2 is connected to a power supply line of the power supply voltage VSS.
These transistors N1 and N2 constitute a current mirror circuit.
The drain of the transistor N3 is connected to the input terminal of the NOT circuit INV, the gate is connected to the drain of the transistor N1, and the source is connected to the power supply line of the power supply voltage VSS.
An output terminal of the NOT circuit INV is connected to a signal line of the drive enable signal.
The comparison circuit 52 configured as described above compares the voltage of the lower one of the 1 st comparison voltage and the 2 nd comparison voltage with the reference voltage Vref, and when the voltage is lower than the reference voltage Vref, outputs the drive enable signal in the enable state (for example, the "H" level), and when the voltage is equal to or higher than the reference voltage Vref, outputs the drive enable signal in the disable state (for example, the "L" level).
Fig. 3 is a circuit diagram showing a configuration example of the driving circuit 53 in embodiment 1. The driving circuit 53 includes an or circuit 531 and an and circuit 532.
In the or circuit 531, when either one of the discharge enable signal en_dsg and the charge enable signal en_chg is at the "H" level, the "H" level is output.
When the output of the or circuit 531 is at the "H" level and the drive enable signal is at the "H" level, the and circuit 532 outputs a drive signal at the "H" level indicating the drive state.
Fig. 4 is a circuit diagram showing a configuration example of the 1 st voltage conversion circuit 6 in embodiment 1. The 1 st voltage conversion circuit 6 is configured such that resistors 161 and 162 are connected in series between a signal line of the gate voltage VG1 and a power source line of the power source voltage VSS. When the resistor 161 has a resistance Ra and the resistor 162 has a resistance Rb, the 1 st detection voltage VDT1 is expressed by the following equation (1).
VDT1＝(Rb/(Ra+Rb))VG1…(1)
That is, the 1 st detection voltage VDT1 fluctuates at the ratio Rb/(ra+rb) in accordance with the fluctuation of the gate voltage VG 1.
The 2 nd voltage conversion circuit 7 has the same configuration as the 1 st voltage conversion circuit 6 shown in fig. 4.
As described above, according to embodiment 1, the charge pump driver 3 and the discharge charge pump driver 4 operate such that the gate voltage of either one of the lower impedances of the protection elements 81 and 82 exceeds the threshold voltage of the transistor in the discharge transistor 11 and the charge transistor 12, and thus can supply a necessary charge current and discharge current.
In addition, according to embodiment 1, when both the gate voltage VG1 of the discharge transistor 12 and the gate voltage VG2 of the charge transistor 12 are at voltages exceeding the threshold voltage, the generation of the clock of the oscillator 54 is stopped, and therefore, the charge pump control circuit 5 with power saving can be realized.
< embodiment 2 >
The configuration other than the 1 st voltage conversion circuit 6 and the 2 nd voltage conversion circuit 7 of the battery device in embodiment 2 is the same as that of embodiment 1.
Fig. 5 is a circuit diagram showing a configuration example of the 1 st voltage conversion circuit 6A in embodiment 2. The 2 nd voltage conversion circuit 7A is also similar in structure to the 1 st voltage conversion circuit 6A shown in fig. 5.
The 1 st voltage conversion circuit 6A includes resistors 161 and 162, an amplifier 163, and a transistor P10. The transistor P10 is a P-channel MOS transistor.
One end of the resistor 161 is connected to the signal line of the gate voltage VG1, and the other end is connected to the source of the transistor P10 and the inverting input terminal (-) of the amplifier 163 via the connection point Q1.
One end of the resistor 162 is connected to the drain and the output terminal of the transistor P10, and the other end is connected to a power supply line of the power supply voltage VSS.
The amplifier 163 is supplied with a predetermined voltage (for example, a power supply voltage VDD of the battery 20 or a voltage of the positive terminal of the connection device 30) at its non-inverting input terminal (+) and an output terminal (-) are connected to the other end of the resistor 161 and the source of the transistor P10 and the gate of the transistor P10, respectively.
The source of the transistor P10 is connected to the other end of the resistor 162 and the inverting input terminal (-) of the amplifier 163, the gate is connected to the output terminal of the amplifier 163, and the drain is connected to one end of the resistor 162.
The amplifier 163 and the transistor P10 constitute a feedback circuit, and thus the voltage of the connection point Q1 is equal to the voltage of the power supply voltage VDD. Thus, a current I1 corresponding to the voltage difference between the gate voltage VG1 and the power supply voltage VDD flows through the resistor 161.
The current I1 flows through the resistor 162 via the transistor P10, and the 1 st detection voltage VDT1 is generated at one end of the resistor 162.
When the resistor 161 is set to the resistance Ra, the resistor 162 is set to the resistance Rb, the voltage applied to the non-inverting input terminal (+) of the amplifier 163 is set to the power supply voltage VDD, and the voltage applied to one end of the resistor 161 is set to the gate voltage VG1, the 1 st detection voltage VDT1 is expressed by the following equation (2).
VDT1＝(Rb/Ra)(VG1-VDD)…(2)
That is, the 1 st detection voltage VDT1 is outputted as the gate-source voltage VGS1 in the discharge transistor 11 at the ratio of the resistance ratio (Rb/Ra).
The 2 nd voltage conversion circuit 7A has the same circuit configuration as the 1 st voltage conversion circuit 6A, and generates the 2 nd detection voltage VDT2 in the same manner as the 1 st detection voltage VDT1.
In addition, in the case where the 1 st voltage conversion circuit 6A is configured as shown in fig. 5, the reference voltage Vref applied to the gate of the transistor P3 in the comparison circuit 52 is generated from the power supply voltage VDD, but unlike in the 1 st embodiment, the voltage difference (VG 1-VDD) is set to a constant voltage exceeding the threshold voltage of the discharge transistor 11. In addition, in the case where the 2 nd voltage conversion circuit 7A is configured as shown in fig. 5, the voltage difference (VG 2-VDD) is also set to a constant voltage exceeding the threshold voltage of the charge transistor 12.
As the voltage conversion circuit, the 1 st voltage conversion circuit 6B and the 2 nd voltage conversion circuit 7B having the circuit configuration shown in fig. 6 may be used instead of the 1 st voltage conversion circuit 6A and the 2 nd voltage conversion circuit 7A having the circuit configuration shown in fig. 5.
Fig. 6 is a circuit diagram showing a configuration example of the 1 st voltage conversion circuit 6B in embodiment 2. The 2 nd voltage conversion circuit 7B is also similar to the 1 st voltage conversion circuit 6B shown in fig. 6.
The 1 st voltage conversion circuit 6B includes a resistor 161, a resistor 162, transistors P11 and P12, and a constant current source 164. The transistors P11 and P12 are P-channel MOS transistors.
One end of the resistor 161 is connected to the signal line of the gate voltage VG1, and the other end is connected to the source of the transistor P12 via the connection point Q2.
One end of the resistor 162 is connected to the drain and the output terminal of the transistor P12, and the other end is connected to a power supply line of the power supply voltage VSS.
The source of the transistor P11 is supplied with a predetermined voltage (for example, the power supply voltage VDD of the battery 20 or the voltage of the positive terminal of the connection device 30), and the gate and the drain are connected to the gate of the transistor P12 and the input terminal of the constant current source 164.
An output terminal of the constant current source 164 is connected to a power supply line of the power supply voltage VSS.
Here, by making the size (W/L) of the transistor P11 and the transistor P12 equal and making the size (W/L) larger, the voltage at the connection point Q2 can be made substantially the same as the power supply voltage VDD.
Thus, a current I1 corresponding to the voltage difference between the gate voltage VG1 and the power supply voltage VDD flows through the resistor 161. Then, the current I1 flows through the resistor 162 via the transistor P12, and the 1 st detection voltage VDT1 is generated at one end.
When the resistor 161 is set to the resistance Ra, the resistor 162 is set to the resistance Rb, the voltage applied to the source of the transistor P11 is the power supply voltage VDD, and the voltage applied to one end of the resistor 161 is the gate voltage VG1, the 1 st detection voltage VDT1 is represented by the formula (2) as in the case of fig. 5.
In the case where the 1 st voltage conversion circuit 6B and the 2 nd voltage conversion circuit 7B are configured as shown in fig. 6, the reference voltage Vref applied to the gate of the transistor P3 in the comparison circuit 52 is generated from the power supply voltage VDD as in the case of fig. 5, but unlike in embodiment 1, the voltage difference (VG 1 to VDD) is set to a constant voltage exceeding the threshold voltage of the discharge transistor 11.
As described above, according to the present embodiment, the gate voltage VG1 of the discharge transistor 11 and the gate voltage VG2 of the charge transistor 12 can be controlled to a voltage that always exceeds the threshold voltages of the discharge transistor 11 and the charge transistor 12 regardless of the variation in the power supply voltage VDD.
Embodiment 3
Fig. 7 is a schematic block diagram showing a configuration example of a battery device using the charge pump control circuit according to embodiment 3.
The battery device 1C includes a battery control circuit 10C instead of the battery control circuit 10 of embodiment 1. The battery control circuit 10C includes a charge pump control circuit 5C instead of the charge pump control circuit 5 of embodiment 1. Since other structures are the same as those of the battery device 1 of fig. 1, the same reference numerals are given to the same constituent elements, and redundant description is appropriately omitted.
The charge pump control circuit 5C includes a switch circuit 51, a comparison circuit 52, a drive circuit 53, an oscillator 54C, and a frequency control circuit 55.
In the frequency control circuit 55, when both the charge enable signal en_chg and the discharge enable signal en_dsg or at least one of the charge enable signal en_chg and the discharge enable signal en_dsg has transitioned from the disabled state to the enabled state, the frequency control signal is set to a high frequency state (for example, an "H" level) for a predetermined period of time and outputted.
Then, after a predetermined time has elapsed, the frequency control circuit 55 changes the frequency control signal to a normal frequency state (for example, an "L" level).
When the driving signal is in the driving state, the oscillator 54C outputs a clock having a frequency corresponding to the frequency control signal from the frequency control circuit 55. Here, when the frequency control signal is in a high frequency state, the oscillator 54C generates a clock having a frequency higher (for example, 2 times or more) than that in the normal frequency state.
The frequency in the normal frequency state is set so that the charge pump driver 3 and the discharge charge pump driver 4 can supply gate currents capable of maintaining the gate voltages of the discharge transistor 11 and the charge transistor 12.
On the other hand, the frequency in the high frequency state is set so that the charge pump driver 3 and the discharge charge pump driver 4 can supply gate currents that can raise the gate voltages of the discharge transistor 11, the charge transistor 12 more rapidly (for example, 2 times faster) than in the case of the clock of the frequency in the normal frequency state.
Fig. 8 is a block diagram showing a configuration example of oscillator 54C and frequency control circuit 55 in embodiment 3.
The frequency control circuit 55 includes rising edge detection circuits 551, 552, or circuit 553, SR-flip-flop 554, and delay time generation circuit 555.
The rising edge detection circuit 551 detects a rising edge that changes from the "L" level (inhibit state) of the charge enable signal en_chg to the "H" level, generates a 1 st set signal of a predetermined time width, and outputs it to the or circuit 553.
The rising edge detection circuit 552 detects a rising edge that changes from the "L" level (inhibit state) of the discharge enable signal en_dsg to the "H" level, generates a 2 nd set signal having a predetermined time width, and outputs the 2 nd set signal to the or circuit 553.
When either one of the 1 st set signal and the 2 nd set signal is input, the or circuit 553 supplies a set signal to the set terminal S of the SR-flip-flop 554.
The SR-flip-flop 554 transitions the frequency control signal output from the output terminal Q from the "L" level (normal frequency state) to the "H" level (high frequency state), for example, in the case where the set signal is supplied to the set terminal S.
In the delay time generation circuit 555, a reset signal is supplied to the reset terminal R of the SR-flip-flop 554 after a predetermined delay time from the time when the frequency control signal supplied from the SR-flip-flop 554 changes from the "L" level to the "H" level.
The SR-flip-flop 554 transitions the frequency control signal output from the output terminal Q from the "H" level to the "L" level in the case where the reset terminal R is supplied with the reset signal.
The delay time generation circuit 555 stops the supply of the reset signal when the frequency control signal transitions from the "H" level to the "L" level.
As described above, according to embodiment 3, since the frequency control circuit 55 is provided, for example, the frequency of the clock at the time of start-up is increased, and therefore, the frequency of the clock in the normal frequency state can be reduced, and the power saving consumption mode can be set.
The delay time generation circuit 555 may be configured to output a reset signal having a predetermined pulse width to the reset terminal of the SR-flip-flop 554 at a timing when the frequency control signal supplied from the SR-flip-flop 554 changes from the "L" level to the "H" level.
In addition, the 1 st voltage conversion circuit 6A and the 2 nd voltage conversion circuit 7A or the 1 st voltage conversion circuit 6B and the 2 nd voltage conversion circuit 7B in embodiment 2 may be used instead of the 1 st voltage conversion circuit 6 and the 2 nd voltage conversion circuit 7.
Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the embodiments, and includes designs and the like that do not depart from the scope of the present invention.
Claims (4)
1. A charge pump control circuit, comprising:
an oscillator that supplies a clock for driving each of a charge pump driver that supplies a 1 st gate voltage to a discharge transistor that controls discharge from a battery and a charge pump driver that supplies a 2 nd gate voltage to a charge transistor that controls charging of the battery;
a drive control circuit that uses a lower one of the 1 st gate voltage and the 2 nd gate voltage as a control target voltage and controls generation of a clock by the oscillator in accordance with the control target voltage; and
and a switching circuit that outputs either one of a detection voltage corresponding to the 1 st gate voltage and a power supply voltage as a 1 st comparison voltage indicating the 1 st gate voltage of the discharge transistor, and switches the detection voltage corresponding to the 2 nd gate voltage and the power supply voltage as a 2 nd comparison voltage indicating the 2 nd gate voltage of the charge transistor, and outputs the switching voltage in response to a charge enable signal controlling the charge of the battery.
2. The charge pump control circuit of claim 1 wherein,
the drive control circuit causes the oscillator to generate the clock when either or both of the discharge enable signal and the charge enable signal indicate an enabled state and the control target voltage is lower than a predetermined set voltage.
3. The charge pump control circuit of claim 2 wherein,
the charge pump control circuit further includes a frequency control circuit that increases the frequency of the clock of the oscillator from a time point when at least one of the discharge enable signal and the charge enable signal is in an enabled state to a time point when a predetermined time elapses.
4. A battery control circuit, comprising:
a discharge transistor that controls discharge from the battery;
a charging transistor that controls charging of the battery;
a 1 st voltage conversion circuit that obtains a 1 st gate voltage of the discharge transistor as a 1 st detection voltage corresponding to the 1 st gate voltage;
a 2 nd voltage conversion circuit that obtains a 2 nd gate voltage of the charge transistor as a 2 nd detection voltage corresponding to the 2 nd gate voltage;
a discharge charge pump driver that supplies the 1 st gate voltage to the discharge transistor;
a charge pump driver that supplies the 2 nd gate voltage to the charge transistor;
an oscillator that supplies clocks for driving the discharge charge pump driver and the charge pump driver, respectively;
a drive control circuit that uses a voltage of the lower one of the 1 st detection voltage and the 2 nd detection voltage as a control target voltage, and controls generation of the clock by the oscillator in accordance with the control target voltage; and
and a switching circuit that outputs either one of a detection voltage corresponding to the 1 st gate voltage and a power supply voltage as a 1 st comparison voltage indicating the 1 st gate voltage of the discharge transistor, and switches the detection voltage corresponding to the 2 nd gate voltage and the power supply voltage as a 2 nd comparison voltage indicating the 2 nd gate voltage of the charge transistor, and outputs the switching voltage in response to a charge enable signal controlling the charge of the battery.
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| JP2019-110750 | 2019-06-14 | ||
| JP2019110750A JP7281805B2 (en) | 2019-06-14 | 2019-06-14 | Charge pump control circuit and battery control circuit |
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| CN112087131A CN112087131A (en) | 2020-12-15 |
| CN112087131B true CN112087131B (en) | 2023-12-05 |
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| CN112865254A (en) * | 2021-03-01 | 2021-05-28 | 珠海迈巨微电子有限责任公司 | Drive device and drive management device |
| CN113675925B (en) * | 2021-08-27 | 2025-01-28 | 珠海迈巨微电子有限责任公司 | Charging and discharging control devices, semiconductor chips, battery management systems and electrical equipment |
| CN113765371A (en) * | 2021-10-08 | 2021-12-07 | 上海南芯半导体科技有限公司 | Charge pump supporting ultra-low voltage charging |
| CN114050554B (en) * | 2022-01-11 | 2022-05-13 | 深圳市创芯微微电子有限公司 | A battery protection circuit and its power tube control method |
| US20240223076A1 (en) * | 2023-01-03 | 2024-07-04 | Texas Instruments Incorporated | Gate drive charge pump circuit for dynamic bias control |
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| TWI846878B (en) | 2024-07-01 |
| CN112087131A (en) | 2020-12-15 |
| TW202110029A (en) | 2021-03-01 |
| US11557963B2 (en) | 2023-01-17 |
| US20200395846A1 (en) | 2020-12-17 |
| JP2020205655A (en) | 2020-12-24 |
| JP7281805B2 (en) | 2023-05-26 |
| KR20200143288A (en) | 2020-12-23 |
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