CN112086450B - Semiconductor Devices - Google Patents

Abstract

Disclosed is a semiconductor device including: a logic cell on the substrate, the logic cell including a first active region and a second active region spaced apart in a first direction; first and second active patterns on the first and second active regions and extending in a second direction; first and second source/drain patterns on the first and second active patterns; a gate electrode extending in a first direction to span the first and second active patterns and arranged at a first pitch in a second direction; a first wiring in the first interlayer dielectric layer on the gate electrode and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode; and a second wiring in the second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.

Description

Semiconductor Devices

Technical Field

The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor.

Background Art

Semiconductor devices are beneficial in the electronics industry due to their small size, versatility and/or low manufacturing cost. Semiconductor devices may include semiconductor memory devices that store logic data, semiconductor logic devices that process operations of logic data, and hybrid semiconductor devices having both storage elements and logic elements. With the advanced development of the electronics industry, semiconductor devices are increasingly required to have high integration. For example, semiconductor devices are increasingly required to have high reliability, high speed and/or versatility. Semiconductor devices have gradually become complex and integrated to meet these required characteristics.

Summary of the invention

Some example embodiments of the inventive concepts provide a semiconductor device including a field effect transistor having enhanced electrical characteristics.

According to some example embodiments of the inventive concept, a semiconductor device may include: a logic unit on a substrate, the logic unit including a first active region and a second active region spaced apart from each other in a first direction; a first active pattern and a second active pattern on the first active region and the second active region, respectively, the first active pattern and the second active pattern extending in a second direction intersecting the first direction; a first source/drain pattern and a second source/drain pattern on an upper portion of the first active pattern and an upper portion of the second active pattern, respectively; a plurality of gate electrodes, spanning the first active pattern and the second active pattern and extending in the first direction, the gate electrodes being arranged at a first pitch in the second direction; a plurality of first wirings, each of the first wirings being electrically connected to the first source/drain pattern, the second source/drain pattern or the gate electrode in a first interlayer dielectric layer on the gate electrode, the first wirings extending parallel to each other in the second direction; and a plurality of second wirings, in a second interlayer dielectric layer on the first interlayer dielectric layer, the second wirings extending parallel to each other in the first direction. The first wirings may include first to third pin wirings. The second wirings may include first to third wiring wirings. The first to third pin wirings may be electrically connected to the first to third wiring wirings, respectively. The length of each of the first to third pin wirings in the second direction may be less than twice the first pitch. A first overlapping region may be defined in which adjacent pin wirings of the first to third pin wirings overlap each other in the first direction. The length of the first overlapping region in the second direction may be less than the first pitch.

According to some example embodiments of the present inventive concept, a semiconductor device may include: a logic unit on a substrate, the logic unit including a first active region and a second active region spaced apart from each other in a first direction; a first active pattern and a second active pattern on the first active region and the second active region, respectively, the first active pattern and the second active pattern extending in a second direction intersecting the first direction; a device isolation layer covering a lower sidewall of the first active pattern and a lower sidewall of the second active pattern, an upper portion of each of the first active pattern and the second active pattern protruding vertically upward from the device isolation layer; and a first active pattern and a second active pattern on the first active region and the second active region, respectively. a first source/drain pattern and a second source/drain pattern on the upper part of the first active pattern and the upper part of the second active pattern; a plurality of gate electrodes, spanning the first active pattern and the second active pattern and extending in the first direction, the gate electrodes being arranged at a first pitch in the second direction; a plurality of first wirings, in the first interlayer dielectric layer on the gate electrode, each of the first wirings is electrically connected to the first source/drain pattern, the second source/drain pattern or the gate electrode, the first wirings extending parallel to each other in the second direction; and a plurality of second wirings, in the second interlayer dielectric layer on the first interlayer dielectric layer, the second wirings extending parallel to each other in the first direction. The first wiring may include first to third pin wirings. The second wiring may include first to third wiring wirings. The first to third pin wirings may be electrically connected to the first to third wiring wirings, respectively. The length of each of the first to third pin wirings in the second direction may be less than twice the first pitch. A first overlapping region may be defined, in which the first to third pin wirings overlap each other in the first direction. The length of the first overlapping region in the second direction may be less than the first pitch.

According to some example embodiments of the inventive concept, a semiconductor device may include: a logic unit on a substrate, the logic unit including a first active region and a second active region spaced apart from each other in a first direction; a first active pattern and a second active pattern on the first active region and the second active region, respectively, the first active pattern and the second active pattern extending in a second direction intersecting the first direction, the first active pattern including a plurality of first channel patterns stacked vertically, the second active pattern including a plurality of second channel patterns stacked vertically; a first source/drain pattern and a second source/drain pattern, the first source/drain pattern The first active pattern is on one side of the first channel pattern, and the second source/drain pattern is on one side of the second channel pattern; a plurality of gate electrodes, spanning the first active pattern and the second active pattern and extending in the first direction, the gate electrodes are arranged at a first pitch in the second direction; a plurality of first wirings, in the first interlayer dielectric layer on the gate electrode, each of the first wirings is electrically connected to the first source/drain pattern, the second source/drain pattern or the gate electrode, and the first wirings extend parallel to each other in the second direction; and a plurality of second wirings, in the second interlayer dielectric layer on the first interlayer dielectric layer, the second wirings extend parallel to each other in the first direction. The first gate electrode in the gate electrode may be on the top surface, the bottom surface and the opposite sidewalls of each of the first channel patterns. The second gate electrode in the gate electrode may be on the top surface, the bottom surface and the opposite sidewalls of each of the second channel patterns. The first wiring may include first to third pin wirings. The second wiring may include first to third wiring wirings. The first to third pin wirings may be electrically connected to the first to third wiring wirings, respectively. Each of the first to third pin wirings may have a length in the second direction that is less than twice the first pitch. A first overlapping region may be defined in which the first to third pin wirings overlap each other in the first direction. The length of the first overlapping region in the second direction may be less than the first pitch.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram showing a computer system for semiconductor design according to some example embodiments of the inventive concept.

FIG. 2 illustrates a flowchart showing a method of designing and manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

3 to 7 show the designed layout of the standard cell, illustrating the layout design step S20 of FIG. 2 .

8A to 8E illustrate layouts showing the pin patterns of the standard cells shown in FIGS. 3 to 7 , respectively.

9 and 10 are plan views showing layouts illustrating the standard cell placement and routing step S30 of FIG. 2 .

FIG. 11 illustrates a plan view showing a semiconductor device according to some example embodiments of the inventive concepts.

12A , 12B, 12C, 12D, and 12E illustrate cross-sectional views taken along lines AA′, BB′, CC′, DD′, and EE′ of FIG. 11 , respectively.

13A , 13B, 13C, 13D and 13E illustrate cross-sectional views taken along lines AA′, BB′, CC′, DD′ and EE′ of FIG. 11 , respectively, showing semiconductor devices according to some example embodiments of the inventive concept.

DETAILED DESCRIPTION

FIG1 shows a block diagram of a computer system for semiconductor design according to some example embodiments of the inventive concept. Referring to FIG1 , the computer system may include a central processing unit (CPU) 10, a working memory 30, an input/output (I/O) device 50, and an auxiliary storage device 70. The computer system may be provided as a dedicated device for designing a layout according to the inventive concept. The computer system may be configured to drive various programs for design and verification simulation.

The CPU 10 may allow the computer system to run software (e.g., applications, operating systems, and device drivers). The CPU 10 may process an operating system loaded in a working memory 30. The CPU 10 may run various applications driven by the operating system. For example, the CPU 10 may process a layout design tool 32, a placement and routing tool 34, and/or an OPC tool 36 loaded in the working memory 30.

An operating system or an application program may be loaded in the working memory 30. When the computer system is started, based on the boot sequence, an operating system image (not shown) stored in the auxiliary storage device 70 may be loaded into the working memory 30. The overall input/output operation of the computer system may be supported by the operating system. Likewise, the working memory 30 may be loaded with an application program selected by a user or provided as a basic service.

The layout design tool 32 for layout design may be loaded from the auxiliary storage device 70 to the working memory 30. The working memory 30 may be loaded with the placement and routing tool 34 from the auxiliary storage device 70, which places the designed standard cells and routes the placed standard cells. The working memory 30 may be loaded with the OPC tool 36 from the auxiliary storage device 70, which performs optical proximity correction (OPC) on the designed layout data.

The layout design tool 32 may include a bias function by which a specific layout pattern is changed in shape and position defined by the design rule. In addition, the layout design tool 32 may perform a design rule check (DRC) under a changed bias data condition. The working memory 30 may be: a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM); or a non-volatile memory such as a phase change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (ReRAM), a ferroelectric random access memory (FRAM), or a NOR flash memory.

The I/O device 50 may control user input/output operations of the user interface. For example, the I/O device 50 may include a keyboard or monitor to allow a designer to input relevant information. The user may use the I/O device 50 to receive information about semiconductor regions or data paths whose operating characteristics need to be adjusted. The I/O device 50 may display the progress status or processing results of the OPC tool 36.

The auxiliary storage device 70 can be used as a storage medium for a computer system. The auxiliary storage device 70 can store application programs, operating system images, and various data. The auxiliary storage device 70 can be provided in the form of one of a memory card (e.g., MMC, eMMC, SD, and micro SD (Micro SD)) and a hard disk drive (HDD). The auxiliary storage device 70 may include a NAND flash memory with a large storage capacity. Alternatively, the auxiliary storage device 70 may include a NOR flash memory or a next generation volatile memory such as PRAM, MRAM, ReRAM, and FRAM.

The system interconnector 90 may be provided to be used as a system bus for providing a network in a computer system. The CPU 10, the working memory 30, the I/O device 50, and the auxiliary storage device 70 may be electrically connected through the system interconnector 90, and may exchange data with each other. The system interconnector 90 is not limited to the above description. For example, the system interconnector 90 may also include additional elements for improving data communication efficiency.

The CPU 10 (and other features, such as the working memory 30 loaded with the layout design tool 32, the placement and routing tool 34, and the OPC tool 36, the I/O device 50, and the auxiliary storage device 70) may include processing circuits, such as: hardware including logic circuits; hardware/software combinations, such as processors running software; or combinations thereof. For example, the processing circuits may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), and the like.

FIG. 2 illustrates a flowchart showing a method of designing and manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Referring to FIG. 2 , a high-level design (S10) of a semiconductor integrated circuit can be performed using the computer system discussed with reference to FIG. 1 . High-level design can mean describing an integrated circuit corresponding to a design target using a high-level language in a hardware description language. For example, a high-level language such as C language can be used for high-level design. Register transfer level (RTL) coding or simulation can be used to express a circuit designed by high-level design. In addition, the code created by RTL coding can be converted into a netlist, and the netlist can be synthesized to describe the entire semiconductor device. The synthesized principle circuit can be verified by a simulation tool, and an adjustment process can be performed based on the verified results.

Layout design may be performed to implement a logically completed semiconductor integrated circuit on a silicon substrate (S20). For example, layout design may be performed based on a schematic circuit synthesized in a high-level design or a netlist corresponding to the schematic circuit.

The cell library for layout design can include information about the operation, speed and power consumption of standard cells. A cell library for representing the layout of a specific gate-level circuit as a layout can be defined in a layout design tool. The layout can be prepared to define the shape or size of the pattern of transistors and metal wiring that will actually be formed on a silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, it may be necessary to properly arrange or describe layout patterns such as PMOS, NMOS, N-well (N-WELL), gate electrodes and metal wiring thereon. To this end, a search can be first performed to select a suitable inverter among the inverters predefined in the cell library.

Various standard cells stored in the cell library can be arranged and wired (S30). For example, the standard cells can be arranged two-dimensionally. High-level wiring (wiring pattern) can be provided on the arranged standard cells. The standard cells can be carefully connected to each other through the wiring step. The arrangement and wiring of the standard cells can be automatically performed by the arrangement and wiring tool 34.

After the routing step, a verification step can be performed on the layout to check whether any part of the schematic circuit violates the given design rules. The verification step can include: design rule checking (DRC), which is used to verify whether the layout meets the given design rules; electrical rule checking (ERC), which is used to verify whether there are electrical disconnect issues in the layout; and layout and schematic comparison (LVS), which is used to verify whether the layout is consistent with the gate-level netlist.

An optical proximity correction (OPC) step (S40) may be performed. A photolithography process may be employed to implement a layout pattern obtained by a layout design on a silicon substrate. Optical proximity correction may be a technique for correcting unintentional optical effects occurring in a photolithography process. For example, optical proximity correction may correct unwanted phenomena such as refraction or process side effects caused by the characteristics of light in an exposure process using the layout pattern. When the optical proximity correction step is performed, the designed layout pattern may be slightly changed (or offset) in shape and position.

A photomask may be generated based on the layout changed by the optical proximity correction (S50). The photomask may generally be manufactured by describing a layout pattern using a chrome layer coated on a glass substrate.

The generated photomask may be used to manufacture a semiconductor device (S60). Various exposure and etching processes may be repeatedly performed when manufacturing a semiconductor device using the photomask. Through these processes discussed above, a pattern defined in the layout design may be sequentially formed on a silicon substrate.

3 to 7 show the layout of the designed standard cell, showing the layout design step S20 of FIG. 2. FIG. 8A to FIG. 8E show the layout of the pin patterns of the standard cells shown in FIG. 3 to FIG. 7, respectively. FIG. 3 to FIG. 7 exemplarily show the layout of the standard cells STD-STDd for a single logic circuit. For example, the standard cell STD shown in FIG. 3, the standard cell STDa shown in FIG. 4, the standard cell STDb shown in FIG. 5, the standard cell STDc shown in FIG. 6, and the standard cell STDd shown in FIG. 7 may all include the same logic circuit. The standard cells STD-STDd of FIG. 3 to FIG. 7 may differ in the position and shape of the pin patterns M1a_P.

The designed standard cell STD will be described below with reference to FIG3 . The standard cell STD may include a gate pattern GEa, a first wiring pattern M1a, a second wiring pattern M2a, and a via pattern V2a. In addition, the standard cell STD may also include other layout patterns (e.g., active regions, active contact patterns, etc.). For the sake of simplicity of the accompanying drawings, other layout patterns (e.g., active regions, active contact patterns, etc.) are omitted in the standard cell STD shown in FIG3 .

The gate pattern GEa may extend in a first direction D1 and may be arranged along a second direction D2 intersecting (e.g., perpendicular to) the first direction D1. The gate pattern GEa may be arranged at a first pitch P1. The term "pitch" may be a distance between the center of a first pattern and the center of a second pattern adjacent to the first pattern. The gate pattern GEa may define a gate electrode.

The first wiring pattern M1a may be positioned at a level higher than or above the level of the gate pattern GEa. The first wiring pattern M1a may define a first metal layer (first wiring). For example, the first wiring pattern M1a may include a first power pattern M1a_R1, a second power pattern M1a_R2, a first internal wiring pattern M1a_I, and a first pin pattern M1a_P1, a second pin pattern M1a_P2, and a third pin pattern M1a_P3. The first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 may be collectively referred to as a pin pattern M1a_P.

The first power pattern M1a_R1, the second power pattern M1a_R2, the first internal wiring pattern M1a_I, and the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 may be patterns disposed on the same layer. The first power pattern M1a_R1, the second power pattern M1a_R2, the first internal wiring pattern M1a_I, and the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 may extend parallel to each other along the second direction D2.

The first power pattern M1a_R1 and the second power pattern M1a_R2 may extend to cross the standard cell STD. The first internal wiring pattern M1a_I and the first, second, and third pin patterns M1a_P1, M1a_P2, and M1a_P3 may be disposed between the first power pattern M1a_R1 and the second power pattern M1a_R2. The first, second, and third pin patterns M1a_P1, M1a_P2, and M1a_P3 may be disposed between the first internal wiring pattern M1a_I.

The first internal wiring pattern M1a_I and the first, second, and third pin patterns M1a_P1, M1a_P2, and M1a_P3 may be arranged along the first direction D1. The first internal wiring pattern M1a_I and the first, second, and third pin patterns M1a_P1, M1a_P2, and M1a_P3 may be arranged at a second pitch P2. The second pitch P2 may be smaller than the first pitch P1.

The first to fifth lower wiring tracks MPTa1 to MPTa5 may be imaginary lines for arranging the first wiring pattern M1a in the standard cell STD. The first to fifth lower wiring tracks MPTa1 to MPTa5 may extend in the second direction D2. The first to fifth lower wiring tracks MPTa1 to MPTa5 may be arranged along the first direction D1.

A single first wiring pattern M1a may be provided on each of the first lower wiring track MPTa1 to the fifth lower wiring track MPTa5. For example, the first internal wiring pattern M1a_I may be provided on the first lower wiring track MPTa1 and the fifth lower wiring track MPTa5, the first pin pattern M1a_P1 may be provided on the second lower wiring track MPTa2, the second pin pattern M1a_P2 may be provided on the third lower wiring track MPTa3, and the third pin pattern M1a_P3 may be provided on the fourth lower wiring track MPTa4.

The second wiring pattern M2a may be positioned at a higher level than the level of the first wiring pattern M1a. The second wiring pattern M2a may define a second metal layer (second wiring). For the layout of the standard cell STD before wiring, the second wiring pattern M2a may include a second internal wiring pattern M2a_I. The second internal wiring pattern M2a_I may extend along the first direction D1. The second internal wiring pattern M2a_I may be parallel to the gate pattern GEa.

The first wiring track MPT1 to the fifth wiring track MPT5 may be an imaginary line for arranging the second wiring pattern M2a in the standard cell STD. The first wiring track MPT1 to the fifth wiring track MPT5 may be collectively referred to as a wiring track MPT. The first wiring track MPT1 to the fifth wiring track MPT5 may extend in the first direction D1. For example, the second internal wiring pattern M2a_I may be disposed on the first wiring track MPT1. The center of the second internal wiring pattern M2a_I may be aligned with the first wiring track MPT1.

The first to fifth wiring traces MPT1 to MPT5 may be arranged at a third pitch P3 along the second direction D2. The third pitch P3 may be smaller than the first pitch P1. The third pitch P3 may be larger than the second pitch P2.

The via pattern V2a may be provided on a region where the first wiring pattern M1a overlaps with the second wiring pattern M2a. For example, the via pattern V2a may be provided between the first internal wiring pattern M1a_I and the second internal wiring pattern M2a_I.

The via pattern V2a may define a via that vertically connects a first wiring (eg, first wiring pattern M1a) to a second wiring (eg, second wiring pattern M2a). The second metal layer may be composed of the via pattern V2a together with the second wiring pattern M2a.

The first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 may define pin wiring in the first metal layer. For example, the pin wiring may be wiring through which a signal is input to the standard cell STD. For example, the pin wiring may be wiring through which a signal is output from the standard cell STD.

The hit point HP may be defined in each of the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3. The hit point HP may be defined at a location where the pin pattern M1a_P and the wiring trace MPT intersect each other. For example, the hit point HP may be defined at the intersection between the first pin pattern M1a_P1 and the second wiring trace MPT2. The hit point HP may be defined at the intersection between the first pin pattern M1a_P1 and the third wiring trace MPT3.

The hit point HP may be a location through which a signal is input to or output from the standard cell STD. As discussed below, in the wiring step S30, a via pattern V2a and a high-level wiring pattern may be disposed on the hit point HP.

An average hit probability value may be calculated for each of the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3. The average hit probability value may be defined as the sum of probabilities that the via pattern V2a is set on each hit point HP of the pin pattern M1a_P. The average hit probability value of each pin pattern may be represented by the following equation 1.

[Equation 1]

For example, two hit points HP (hit point stack _n of equation 1 above) may be defined on the second wiring track MPT2. Only a single via pattern V2a (hit point _n of equation 1 above) may be arranged on the second wiring track MPT2. Therefore, the hit point HP on the second wiring track MPT2 may have a placement probability value of 0.5 for the via pattern V2a.

Three hit points HP may be defined on the third wiring trace MPT3. Only a single via pattern V2a may be provided on the third wiring trace MPT3. Therefore, the hit point HP on the third wiring trace MPT3 may have an arrangement probability value of the via pattern V2a of 0.33.

One hit point HP may be defined on the fourth wiring trace MPT4. Only a single via pattern V2a may be disposed on the fourth wiring trace MPT4. Therefore, the hit point HP on the fourth wiring trace MPT4 may have a placement probability value of the via pattern V2a of 1.00.

The first pin pattern M1a_P1 may have an average hit probability value of 0.83, or the sum of 0.50 and 0.33 (see Equation 1). The second pin pattern M1a_P2 may have an average hit probability value of 0.83, or the sum of 0.50 and 0.33. The third pin pattern M1a_P3 may have an average hit probability value of 1.33, or the sum of 0.33 and 1.00. For the standard cell STD of FIG. 3 , the average hit probability value of each of the first pin pattern M1a_P1 and the second pin pattern M1a_P2 may be less than 1.00.

It may be preferable that the average hit probability value of each of the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 is equal to or greater than 1.00. Specifically, the range of the average hit probability value of each pin pattern according to the present invention may be represented by Equation 2 below.

[Equation 2]

The average hit probability value for each pin pattern means the minimum number of hit points required.

The average hit probability value of the first pin pattern M1a_P1 may be 0.83 which is less than 1.00. The average hit probability value of the second pin pattern M1a_P2 may be 0.83 which is less than 1.00. That is, the average hit probability value of the first pin pattern M1a_P1 and the average hit probability value of the second pin pattern M1a_P2 do not satisfy Equation 2 of the present invention. When the average hit probability value of the pin pattern M1a_P is less than 1.00, the wiring efficiency may be reduced and the capacitance between the wirings may be increased.

For example, referring to FIG. 8A , an overlap region OR may be defined in which the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 overlap each other in the first direction D1. The overlap region OR may have a first length L1 in the second direction D2. The first length L1 may be relatively large. The first length L1 may be greater than the third pitch P3. Because the first length L1 of the overlap region OR is relatively large, a relatively high capacitance may be provided between pin wirings to be formed by the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3.

The designed standard cell STDa will be described below with reference to FIG. 4 . In the following example implementation, it will be omitted to avoid repetition of the standard cell STD discussed above with reference to FIG. 3 , and the differences will be described in detail. The hit points HP may be limited to the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3. The number of hit points HP on the standard cell STDa shown in FIG. 4 may be greater than the number of hit points HP on the standard cell STD shown in FIG. 3 . For example, the number of positions where the via pattern V2a may be set on the standard cell STDa of FIG. 4 may be greater than the number of positions where the via pattern V2a may be set on the standard cell STD of FIG. 3 . The wiring freedom of the standard cell STDa shown in FIG. 4 may be greater than the wiring freedom of the standard cell STD shown in FIG. 3 .

The first pin pattern M1a_P1 may have an average hit probability value of 0.99, or the sum of 0.33, 0.33 and 033. The second pin pattern M1a_P2 may have an average hit probability value of 0.99, or the sum of 0.33, 0.33 and 033. The third pin pattern M1a_P3 may have an average hit probability value of 0.99, or the sum of 0.33, 0.33 and 033. For the standard cell STDa of FIG. 4, the average hit probability value of each of the first pin pattern M1a_P1, the second pin pattern M1a_P2 and the third pin pattern M1a_P3 may be less than 1.00. That is, the first pin pattern M1a_P1, the second pin pattern M1a_P2 and the third pin pattern M1a_P3 all do not satisfy equation 2 of the present invention.

In some example embodiments, referring to FIG. 8B , an overlap region OR may be defined in which the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 overlap each other in the first direction D1. The overlap region OR may have a second length L2 in the second direction D2. The second length L2 may be greater than the first length L1 of FIG. 8A . Because the second length L2 of the overlap region OR is relatively large, a relatively high capacitance may be provided between the pin wirings to be formed by the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3. In this case, the standard cell STDa of FIG. 4 may reliably have a high degree of freedom in wiring, but may have a problem of high capacitance between the pin wirings.

The designed standard cell STDb will be described below with reference to FIG. 5 . In the following example implementation, it will be omitted to avoid repetition of the standard cell STD discussed above with reference to FIG. 3 , and the differences will be described in detail. The hit point HP may be defined on the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3. The first pin pattern M1a_P1 may have an average hit probability value of 1.00, or the sum of 0.50 and 0.50. The second pin pattern M1a_P2 may have an average hit probability value of 1.50, or the sum of 1.00 and 0.50. The third pin pattern M1a_P3 may have an average hit probability value of 1.50, or the sum of 0.50 and 1.00. For the standard cell STDb of FIG. 5 , the average hit probability value of each of the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 may be equal to or greater than 1.00. That is, the first foot pattern M1a_P1 , the second foot pattern M1a_P2 , and the third foot pattern M1a_P3 all satisfy Equation 2 of the present invention.

For example, referring to FIG. 8C , a first overlap region OR1 may be defined in which the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 overlap each other in the first direction D1. The first overlap region OR1 may have a third length L3 in the second direction D2. The third length L3 may be relatively small. The third length L3 may be smaller than the third pitch P3. Thus, the third length L3 may be relatively small.

A second overlapping region OR2 may be defined in which a pair of adjacent foot patterns M1a_P overlap each other in the first direction D1. For example, a second overlapping region OR2 may be defined in which a first foot pattern M1a_P1 and a second foot pattern M1a_P2 overlap each other in the first direction D1.

The second overlap region OR2 may have a fourth length L4 in the second direction D2. The fourth length L4 may be relatively small. The fourth length L4 may be smaller than the third pitch P3. Thus, the fourth length L4 may be relatively small.

Each of the first leg pattern M1a_P1, the second leg pattern M1a_P2, and the third leg pattern M1a_P3 may have a length in the second direction D2 that is less than twice the first pitch P1. For example, the third leg pattern M1a_P3 may have a fifth length L5 in the second direction D2. The fifth length L5 may be less than twice the first pitch P1. In this sense, each of the first leg pattern M1a_P1, the second leg pattern M1a_P2, and the third leg pattern M1a_P3 may have a relatively small length.

For the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 of FIG5, the hit points HP can be evenly distributed in the standard cell STDb, which can lead to a high degree of freedom in wiring. In addition, because each of the first overlap region OR1 and the second overlap region OR2 between the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 is given a relatively small length, a relatively low capacitance can be provided between the pin wirings to be formed by the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3.

The designed standard cell STDc will be described below with reference to FIG. 6. In the following example implementation, it will be omitted to avoid repetition of the standard cell STD discussed above with reference to FIG. 3, and the differences will be described in detail. The hit point HP can be defined on the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3. The first pin pattern M1a_P1 can have an average hit probability value of 1.50, or the sum of 0.50 and 1.00. The second pin pattern M1a_P2 can have an average hit probability value of 1.00, or the sum of 0.50 and 0.50. The third pin pattern M1a_P3 can have an average hit probability value of 1.50, or the sum of 1.00 and 0.50. For the standard cell STDc of FIG. 6, the average hit probability value of each of the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 can be equal to or greater than 1.00. That is, the first foot pattern M1a_P1 , the second foot pattern M1a_P2 , and the third foot pattern M1a_P3 all satisfy Equation 2 of the present invention.

For example, referring to FIG8D, there may be no first overlapping region OR1 in which the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 overlap each other in the first direction D1. A second overlapping region OR2 may be defined in which a pair of adjacent pin patterns M1a_P overlap each other in the first direction D1. The second overlapping region OR2 may have a length less than the third pitch P3 in the second direction D2. For example, the length of the second overlapping region OR2 may be relatively small. Like the standard cell STDb of FIG5, the standard cell STDc of FIG6 may reliably have a high degree of freedom in wiring while reducing the capacitance between the pin wirings.

The designed standard cell STDd will be described below with reference to FIG. 7 . In the following example implementation, it will be omitted to avoid repetition of the standard cell STD discussed above with reference to FIG. 3 , and the differences will be described in detail. The hit point HP may be defined on the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3. The first pin pattern M1a_P1 may have an average hit probability value of 1.50, or the sum of 1.00 and 0.50. The second pin pattern M1a_P2 may have an average hit probability value of 1.00, or the sum of 0.50 and 0.50. The third pin pattern M1a_P3 may have an average hit probability value of 1.50, or the sum of 0.50 and 1.00. For the standard cell STDd of FIG. 7 , the average hit probability value of each of the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 may be equal to or greater than 1.00.

For example, referring to FIG8E, there may not be a first overlapping region OR1 in which the first pin pattern M1a_P1, the second pin pattern M1a_P2, and the third pin pattern M1a_P3 overlap each other in the first direction D1. A second overlapping region OR2 may be defined in which a pair of adjacent pin patterns M1a_P overlap each other in the first direction D1. The second overlapping region OR2 may have a length less than the third pitch P3 in the second direction D2. For example, the length of the second overlapping region OR2 may be relatively small. Like the standard cell STDb of FIG5, the standard cell STDd of FIG7 may reliably have a high degree of freedom in wiring while reducing the capacitance between the pin wirings.

9 and 10 are plan views showing layouts illustrating the standard cell placement and routing step S30 of FIG. 2 .

9 , the first, second, and third standard cells STD1 , STD2 , and STD3 may be arranged in the second direction D2 . For example, each of the first, second, and third standard cells STD1 , STD2 , and STD3 may be the designed standard cell STDb of FIG. 5 .

The partition pattern DBa may be interposed between adjacent standard cells among the first to third standard cells STD1 , STD2 , and STD3 . For example, the partition pattern DBa may replace the gate pattern GEa on the opposite side of the first standard cell STD1 .

10 , a wiring step may be performed on the first to third standard cells STD1 , STD2 and STD3 . The wiring of the first to third standard cells STD1 , STD2 and STD3 may include arranging a wiring pattern M2a_O . The arrangement of the wiring pattern M2a_O may connect the standard cells according to the designed circuit.

The first cell boundary CB1 may be defined on each of the first standard cell STD1, the second standard cell STD2, and the third standard cell STD3, and the first cell boundary CB1 extends in the second direction D2. For each of the first standard cell STD1, the second standard cell STD2, and the third standard cell STD3, the second cell boundary CB2 may be defined on a position opposite to the position on which the first cell boundary CB1 is defined. The first power pattern M1a_R1 may be disposed on the first cell boundary CB1. The second power pattern M1a_R2 may be disposed on the second cell boundary CB2. In each of the first to third standard cells STD1, STD2, and STD3, each of the wiring patterns M2a_O may extend beyond at least one of the first cell boundary CB1 and the second cell boundary CB2. The wiring pattern M2a_O may be connected to the pin pattern M1a_P.

The wiring pattern M2a_O may be disposed on the second to fifth wiring traces MPT2 to MPT5. The wiring pattern M2a_O and the second internal wiring pattern M2a_I may constitute a second wiring pattern M2a. The second wiring pattern M2a may define a second metal layer (second wiring).

The via pattern V2a may be disposed on a hit point HP between the wiring pattern M2a_O and the foot pattern M1a_P. The via pattern V2a on the hit point HP may define a connection between the wiring pattern M2a_O and the foot pattern M1a_P.

After the arrangement and routing of the standard cells are completed according to Figures 9 and 10, optical proximity correction can be performed on the designed layout, and a photomask can be manufactured. The manufactured photomask can be used in a semiconductor process, so a semiconductor device can be manufactured (see Figure 1).

FIG11 shows a plan view showing a semiconductor device according to some example embodiments of the present inventive concept. FIG12A, FIG12B, FIG12C, FIG12D and FIG12E show cross-sectional views taken along lines A-A', B-B', C-C', D-D' and E-E' of FIG11, respectively. FIG11 and FIG12A to FIG12E exemplarily show a semiconductor device actually implemented on a substrate when the designed second standard cell STD2 of FIG10 is used.

11 and 12A to 12E, a logic cell LC may be provided on a substrate 100. The logic cell LC may have logic transistors constituting a logic circuit provided thereon.

The substrate 100 may include a first active region PR and a second active region NR. In some example embodiments of the present inventive concept, the first active region PR may be a PMOSFET region, and the second active region NR may be an NMOSFET region. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, or silicon germanium. For example, the substrate 100 may be a silicon substrate.

The first active region PR and the second active region NR may be defined by a second trench TR2 formed at an upper portion of the substrate 100. The second trench TR2 may be positioned between the first active region PR and the second active region NR. The first active region PR and the second active region NR may be spaced apart from each other in the first direction D1 via the second trench TR2. Each of the first active region PR and the second active region NR may extend in a second direction D2 intersecting the first direction D1.

The first active pattern AP1 and the second active pattern AP2 may be provided on the first active region PR and the second active region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend parallel to each other in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertically protruding portions of the substrate 100. The first trench TR1 may be defined between adjacent first active patterns AP1 and between adjacent second active patterns AP2. The first trench TR1 may be shallower than the second trench TR2.

The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a silicon oxide layer. The first active pattern AP1 and the second active pattern AP2 may have an upper portion vertically protruding upward from the device isolation layer ST (see FIG. 12E). Each of the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may have a fin shape. The device isolation layer ST may not cover the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The device isolation layer ST may cover the lower sidewall of the first active pattern AP1 and the lower sidewall of the second active pattern AP2.

A first source/drain pattern SD1 may be provided at an upper portion of the first active pattern AP1. The first source/drain pattern SD1 may be an impurity region having a first conductivity type (e.g., p-type). A first channel pattern CH1 may be interposed between a pair of adjacent first source/drain patterns SD1. A second source/drain pattern SD2 may be provided at an upper portion of the second active pattern AP2. The second source/drain pattern SD2 may be an impurity region having a second conductivity type (e.g., n-type). A second channel pattern CH2 may be interposed between a pair of adjacent second source/drain patterns SD2.

The first source/drain pattern SD1 and the second source/drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth process. For example, the first source/drain pattern SD1 and the second source/drain pattern SD2 may have top surfaces coplanar with top surfaces of the first channel pattern CH1 and the second channel pattern CH2. In some example embodiments, the first source/drain pattern SD1 and the second source/drain pattern SD2 may have top surfaces higher than top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

The first source/drain pattern SD1 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Therefore, the first source/drain pattern SD1 may provide compressive stress to the first channel pattern CH1. For example, the second source/drain pattern SD2 may include the same semiconductor element (e.g., Si) as that of the substrate 100.

The gate electrode GE may be provided to extend in the first direction D1 while crossing the first active pattern AP1 and the second active pattern AP2. The gate electrodes GE may be arranged at a first pitch P1 along the second direction D2. The gate electrodes GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE may surround a top surface and opposite sidewalls of each of the first channel pattern CH1 and the second channel pattern CH2.

12E in detail, the gate electrode GE may be provided on the first top surface TS1 of the first channel pattern CH1, and may also be provided on at least one first side wall SW1 of the first channel pattern CH1. The gate electrode GE may be provided on the second top surface TS2 of the second channel pattern CH2, and may also be provided on at least one second side wall SW2 of the second channel pattern CH2. In this sense, the transistor according to the example embodiment may be a three-dimensional field effect transistor (e.g., FinFET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

Referring back to FIG. 11 and FIG. 12A to FIG. 12E, a pair of gate spacers GS may be disposed on opposite sidewalls of each gate electrode GE. The gate spacer GS may extend along the gate electrode GE in the first direction D1. The gate spacer GS may have a top surface higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer dielectric layer 110 to be discussed below. The gate spacer GS may include one or more of SiCN, SiCON, and SiN. Alternatively, the gate spacer GS may include a multilayer including two or more of SiCN, SiCON, and SiN.

A gate capping pattern GP may be provided on each of the gate electrodes GE. The gate capping pattern GP may extend in the first direction D1 along the gate electrode GE. The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to be discussed below. For example, the gate capping pattern GP may include one or more of SiON, SiCN, SiCON, and SiN.

The gate dielectric pattern GI may be interposed between the gate electrode GE and the first active pattern AP1 and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI may extend along the bottom surface of the gate electrode GE, and the bottom surface of the gate electrode GE is overlaid on the gate dielectric pattern GI. For example, the gate dielectric pattern GI may cover the first top surface TS1 and the first sidewall SW1 of the first channel pattern CH1. The gate dielectric pattern GI may cover the second top surface TS2 and the second sidewall SW2 of the second channel pattern CH2. The gate dielectric pattern GI may cover the top surface of the device isolation layer ST under the gate electrode GE (see FIG. 12E ).

In some example embodiments of the present inventive concept, the gate dielectric pattern GI may include a high-k dielectric material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on the gate dielectric pattern GI and adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. The thickness and composition of the first metal pattern may be adjusted to achieve a desired threshold voltage.

The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). The first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

The second metal pattern may include a metal having a lower resistance than that of the first metal pattern. For example, the second metal pattern may include one or more of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

A first interlayer dielectric layer 110 may be provided on the substrate 100. The first interlayer dielectric layer 110 may cover the gate spacer GS and the first source/drain pattern SD1 and the second source/drain pattern SD2. The first interlayer dielectric layer 110 may have a top surface substantially coplanar with a top surface of the gate cap pattern GP and a top surface of the gate spacer GS. The first interlayer dielectric layer 110 may be provided thereon with a second interlayer dielectric layer 120 covering the gate cap pattern GP. A third interlayer dielectric layer 130 may be provided on the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be provided on the third interlayer dielectric layer 130. For example, the first to fourth interlayer dielectric layers 110 to 140 may include silicon oxide layers.

The logic cell LC may be provided with a pair of partition structures DB facing each other in the second direction D2 on opposite sides thereof. The partition structure DB may extend parallel to the gate electrode GE in the first direction D1. The partition structure DB and its adjacent gate electrode GE may be arranged at a first pitch P1.

The separation structure DB may penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 and may extend into the first active pattern AP1 and the second active pattern AP2. The separation structure DB may penetrate the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The separation structure DB may separate the first active region PR and the second active region NR of the logic cell LC from the active region of the adjacent logic cell.

Active contacts AC may be provided to penetrate the first and second interlayer dielectric layers 110 and 120 and have electrical connection with the first and second source/drain patterns SD1 and SD2. Each of the active contacts AC may be provided between a pair of adjacent gate electrodes GE.

The active contact AC may be a self-aligned contact. For example, the gate cap pattern GP and the gate spacer GS may be used to form the active contact AC in a self-aligned manner. For example, the active contact AC may cover at least a portion of the sidewall of the gate spacer GS. Although not shown, the active contact AC may partially cover the top surface of the gate cap pattern GP.

The silicide pattern SC may be interposed between the active contact AC and the first source/drain pattern SD1 and between the active contact AC and the second source/drain pattern SD2. The active contact AC may be electrically connected to the first source/drain pattern SD1 and the second source/drain pattern SD2 through the silicide pattern SC. The silicide pattern SC may include metal silicide, such as one or more of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

The active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include one or more of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewall and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include one or more of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include one or more of a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer.

A first metal layer may be provided in the third interlayer dielectric layer 130. The first metal layer may include a first wiring M1, a first lower via V1_a, and a second lower via V1_b. The first lower via V1_a and the second lower via V1_b may be provided under the first wiring M1.

The first wiring M1 may include a first power wiring M1_R1 and a second power wiring M1_R2 extending in the second direction D2 and crossing the logic cell LC. The power supply voltage VDD may be applied to the first power wiring M1_R1, and the ground voltage VSS may be applied to the second power wiring M1_R2. A first cell boundary CB1 may be defined on the logic cell LC, the first cell boundary CB1 extending in the second direction D2. On the logic cell LC, the second cell boundary CB2 may be defined at a position opposite to a position on which the first cell boundary CB1 is defined. The first power wiring M1_R1 may be disposed on the first cell boundary CB1. The first power wiring M1_R1 may extend in the second direction D2 along the first cell boundary CB1. The second power wiring M1_R2 may be disposed on the second cell boundary CB2. The second power wiring M1_R2 may extend in the second direction D2 along the second cell boundary CB2.

The first wiring M1 may further include a first internal wiring M1_I between the first power wiring M1_R1 and the second power wiring M1_R2 and first, second, and third pin wirings M1_P1, M1_P2, and M1_P3. The first internal wiring M1_I and the first, second, and third pin wirings M1_P1, M1_P2, and M1_P3 may each have a linear shape or a bar shape extending in the second direction D2.

The first internal wiring M1_I and the first pin wiring M1_P1, the second pin wiring M1_P2, and the third pin wiring M1_P3 may be arranged along the first direction D1 with a second pitch P2. The second pitch P2 may be smaller than the first pitch P1. The first pin wiring M1_P1, the second pin wiring M1_P2, and the third pin wiring M1_P3 may be adjacent to each other. The first pin wiring M1_P1, the second pin wiring M1_P2, and the third pin wiring M1_P3 may be arranged in sequence along the first direction D1. The first pin wiring M1_P1, the second pin wiring M1_P2, and the third pin wiring M1_P3 may be collectively referred to as the pin wiring M1_P.

8C, the first overlap region OR1 in which the first pin wiring M1_P1, the second pin wiring M1_P2, and the third pin wiring M1_P3 overlap each other in the first direction D1 may be given a third length L3. The third length L3 may be smaller than the first pitch P1. The third length L3 may be smaller than the third pitch P3.

The second overlap region OR2 where the adjacent first and second pin wirings M1_P1 and M1_P2 overlap each other in the first direction D1 may be given a fourth length L4. The fourth length L4 may be smaller than the first pitch P1. The fourth length L4 may be smaller than the third pitch P3.

Each of the first pin wiring M1_P1, the second pin wiring M1_P2, and the third pin wiring M1_P3 may have a length less than twice the first pitch P1 in the second direction D2. For example, the third pin wiring M1_P3 may have a fifth length L5 in the second direction D2. The fifth length L5 may be less than twice the first pitch P1.

The first lower via V1_a may be correspondingly interposed between the first wiring M1 and the active contact AC and may electrically connect the first wiring M1 and the active contact AC. The second lower via V1_b may be correspondingly interposed between the first wiring M1 and the gate electrode GE and may connect the first wiring M1 and the gate electrode GE.

For example, the first power wiring M1_R1 and the second power wiring M1_R2 may be electrically connected to the corresponding active contact AC through the first lower via V1_a. The first internal wiring M1_I may be electrically connected to the corresponding active contact AC through the first lower via V1_a. The first pin wiring M1_P1, the second pin wiring M1_P2, and the third pin wiring M1_P3 may be electrically connected to the corresponding gate electrode GE through the second lower via V1_b.

For example, the corresponding first wiring in the first wiring M1 and the first lower via V1_a or the second lower via V1_b thereunder may be integrally connected to each other to form a single conductive structure. For example, the corresponding first wiring in the first wiring M1 and the first lower via V1_a or the second lower via V1_b thereunder may be formed together. A dual damascene process may be performed so that the corresponding first wiring in the first wiring M1 and the first lower via V1_a or the second lower via V1_b thereunder may be formed as a single conductive structure.

The second metal layer may be provided in the fourth interlayer dielectric layer 140. The second metal layer may include a second wiring M2 and a second via V2. The second via V2 may be provided under the second wiring M2. The second via V2 may be inserted between the second wiring M2 and the first wiring M1 and may electrically connect the second wiring M2 and the first wiring M1. The corresponding second wirings in the second wiring M2 and the second vias V2 thereunder may be connected to each other. For example, the corresponding second wirings in the second wiring M2 may be formed simultaneously with the second vias V2 thereunder. A dual damascene process may be performed to simultaneously form the corresponding second wirings in the second wiring M2 and the second vias V2 thereunder.

The second wirings M2 may each have a linear shape or a strip shape extending in the first direction D1. For example, all the second wirings M2 may extend parallel to each other in the first direction D1. When viewed in a plan view, the second wirings M2 may be parallel to the gate electrode GE. The second wirings M2 may be arranged along the second direction D2 at a third pitch P3. The third pitch P3 may be smaller than the first pitch P1. The third pitch P3 may be larger than the second pitch P2.

The second wiring M2 may include a second internal wiring M2_I and a first wiring wiring M2_O1, a second wiring wiring M2_O2, and a third wiring wiring M2_O3. The second internal wiring M2_I may extend from the first active region PR to the second active region NR. The second internal wiring M2_I may not extend beyond the first cell boundary CB1. The second internal wiring M2_I may not extend beyond the second cell boundary CB2. For example, the second internal wiring M2_I may have one end positioned on the first active region PR and the other end positioned on the second active region NR.

The second internal wiring M2_I on the first active region PR may be electrically connected to the first source/drain pattern SD1 through the second via V2, the first internal wiring M1_I, the first lower via V1_a, and the active contact AC. The second internal wiring M2_I on the second active region NR may be electrically connected to the second source/drain pattern SD2 through the second via V2, the first internal wiring M1_I, the first lower via V1_a, and the active contact AC.

In this case, the first internal wiring M1_I and the second internal wiring M2_I in the logic cell LC may electrically connect the PMOS transistor (PMOSFET) of the first active region PR to the NMOS transistor (NMOSFET) of the second active region NR. The first internal wiring M1_I and the second internal wiring M2_I in the logic cell LC may electrically connect the source/drain of the PMOSFET to the source/drain of the NMOSFET. The first internal wiring M1_I and the second internal wiring M2_I may be wirings constituting a logic circuit of the logic cell LC.

Each of the first wiring wiring M2_O1, the second wiring wiring M2_O2, and the third wiring wiring M2_O3 may extend beyond (e.g., over) at least one of the first cell boundary CB1 and the second cell boundary CB2. The first wiring wiring M2_O1 may extend to a first logic cell adjacent to the logic cell LC in a first direction D1. The second wiring wiring M2_O2 may extend to a second logic cell adjacent to the logic cell LC in a direction opposite to the first direction D1. The third wiring wiring M2_O3 may extend from the first logic cell to the second logic cell while crossing the logic cell LC. For example, the first wiring wiring M2_O1, the second wiring wiring M2_O2, and the third wiring wiring M2_O3 may connect the logic circuit of the logic cell LC to the logic circuit of another logic cell. The first wiring wiring M2_O1, the second wiring wiring M2_O2, and the third wiring wiring M2_O3 may be collectively referred to as wiring wiring M2_O.

The first wiring wiring M2_O1, the second wiring wiring M2_O2, and the third wiring wiring M2_O3 can be electrically connected to the first pin wiring M1_P1, the second pin wiring M1_P2, and the third pin wiring M1_P3 through the second path V2, respectively. The logic cell LC can be configured so that the pin wiring M1_P receives a signal through the wiring wiring M2_O. The logic cell LC can also be configured so that the pin wiring M1_P outputs a signal through the wiring wiring M2_O. For example, referring to FIG. 12A, the logic cell LC can be configured so that the gate electrode GE receives a signal through the wiring wiring M2_O, the second path V2, the pin wiring M1_P, and the second lower path V1_b.

The first wiring M1, the first lower via V1_a, the second lower via V1_b, the second wiring M2, and the second via V2 may include the same conductive material. For example, the first wiring M1, the first lower via V1_a, the second lower via V1_b, the second wiring M2, and the second via V2 may include at least one metallic material selected from aluminum, copper, tungsten, molybdenum, and cobalt. Although not shown, an additional metal layer may be stacked on the fourth interlayer dielectric layer 140. Each of the stacked metal layers may include a wiring wiring.

13A, 13B, 13C, 13D, and 13E illustrate cross-sectional views taken along lines A-A', B-B', C-C', D-D', and E-E' of FIG. 11, respectively, showing semiconductor devices according to some example embodiments of the inventive concept. In the following example embodiments, detailed descriptions of technical features that are repeated with respect to the technical features discussed above with reference to FIGS. 11 and 12A to 12E will be omitted, and differences from the technical features discussed above with reference to FIGS. 11 and 12A to 12E will be discussed in detail.

11 and 13A to 13E, a substrate 100 including a first active region PR and a second active region NR may be provided. A device isolation layer ST may be provided on the substrate 100. The device isolation layer ST may define a first active pattern AP1 and a second active pattern AP2 at an upper portion of the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be defined on the first active region PR and the second active region NR, respectively.

The first active pattern AP1 may include vertically stacked first channel patterns CH1. The stacked first channel patterns CH1 may be spaced apart from each other in the third direction D3. The stacked first channel patterns CH1 may vertically overlap each other. The second active pattern AP2 may include vertically stacked second channel patterns CH2. The stacked second channel patterns CH2 may be spaced apart from each other in the third direction D3. The stacked second channel patterns CH2 may vertically overlap each other. The first channel pattern CH1 and the second channel pattern CH2 may include one or more of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

The first source/drain pattern SD1 may be provided at an upper portion of the first active pattern AP1. The stacked first channel pattern CH1 may be interposed between a pair of adjacent first source/drain patterns SD1. The stacked first channel pattern CH1 may connect the pair of adjacent first source/drain patterns SD1 to each other.

The second source/drain pattern SD2 may be provided at an upper portion of the second active pattern AP2. The stacked second channel pattern CH2 may be interposed between a pair of adjacent second source/drain patterns SD2. The stacked second channel pattern CH2 may connect the pair of adjacent second source/drain patterns SD2 to each other.

The gate electrode GE may be provided to extend in the first direction D1 while crossing the first channel pattern CH1 and the second channel pattern CH2. The gate electrode GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS may be provided on opposite sidewalls of the gate electrode GE. A gate cap pattern GP may be provided on the gate electrode GE.

The gate electrode GE may surround each of the first channel pattern CH1 and the second channel pattern CH2 (see FIG. 13E ). The gate electrode GE may be provided on the first top surface TS1 of the first channel pattern CH1, at least one first side wall SW1 of the first channel pattern CH1, and the first bottom surface BS1 of the first channel pattern CH1. The gate electrode GE may be provided on the second top surface TS2 of the second channel pattern CH2, at least one second side wall SW2 of the second channel pattern CH2, and the second bottom surface BS2 of the second channel pattern CH2. For example, the gate electrode GE may surround the top surface, the bottom surface, and the opposite side walls of each of the first channel pattern CH1 and the second channel pattern CH2. In this sense, the transistor according to the example embodiment may be a three-dimensional field effect transistor (e.g., FinFET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

A gate dielectric pattern GI may be provided between the gate electrode GE and each of the first and second channel patterns CH1 and CH2. The gate dielectric pattern GI may surround each of the first and second channel patterns CH1 and CH2.

On the second active region NR, the dielectric pattern IP may be interposed between the gate dielectric pattern GI and the second source/drain pattern SD2. The gate dielectric pattern GI and the dielectric pattern IP may separate the gate electrode GE from the second source/drain pattern SD2. In contrast, the dielectric pattern IP may not be provided on the first active region PR.

First and second interlayer dielectric layers 110 and 120 may be provided on the entire surface of substrate 100. Active contacts AC may be provided to penetrate the first and second interlayer dielectric layers 110 and 120 and have connections with first and second source/drain patterns SD1 and SD2, respectively.

A third interlayer dielectric layer 130 may be provided on the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be provided on the third interlayer dielectric layer 130. A first metal layer may be provided in the third interlayer dielectric layer 130. The first metal layer may include a first wiring M1, a first lower via V1_a, and a second lower via V1_b. A second metal layer may be provided in the fourth interlayer dielectric layer 140. The second metal layer may include a second wiring M2 and a second via V2.

The description of the first metal layer and the second metal layer may be substantially the same as that discussed above with reference to FIGS. 11 and 12A to 12E .

According to the present invention, the semiconductor device can improve the wiring freedom of its logic unit. In addition, although the wiring freedom is improved, the capacitance between the pin wirings can be reduced to improve the electrical characteristics.

Although some exemplary embodiments of the present invention have been discussed with reference to the accompanying drawings, it will be appreciated that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention. Therefore, it will be appreciated that the above embodiments are illustrative in all aspects and not restrictive.

This application claims the benefit of Korean Patent Application No. 10-2019-0071019 filed on June 14, 2019, and Korean Patent Application No. 10-2019-0149828 filed on November 20, 2019, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety.

Claims (20)

1. A semiconductor device, comprising:

A logic cell on a substrate, the logic cell comprising a first active region and a second active region spaced apart in a first direction;

A first active pattern on the first active region and a second active pattern on the second active region, the first active pattern and the second active pattern extending in a second direction crossing the first direction;

a first source/drain pattern on an upper portion of the first active pattern and a second source/drain pattern on an upper portion of the second active pattern;

a plurality of gate electrodes crossing the first active pattern and the second active pattern and extending in the first direction, the gate electrodes being arranged at a first pitch in the second direction;

a plurality of first wirings in the first interlayer dielectric layer on the gate electrode, each of the first wirings being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, the first wirings extending parallel to each other in the second direction; and

A plurality of second wirings in a second interlayer dielectric layer on the first interlayer dielectric layer, the second wirings extending parallel to each other in the first direction,

Wherein the method comprises the steps of

The first wiring includes first to third pin wirings,

The second wiring includes first to third wiring lines,

The first to third lead wirings are electrically connected to the first to third wiring wirings respectively,

A length of each of the first to third pin wirings in the second direction is less than twice the first pitch,

A first overlapping region in which adjacent ones of the first to third lead wirings overlap each other in the first direction is defined, and

The length of the first overlap region in the second direction is less than the first pitch.

2. The semiconductor device according to claim 1, wherein

The first wirings are arranged at a second pitch in the first direction,

The second wirings are arranged at a third pitch in the second direction,

The third pitch is smaller than the first pitch, and

The third pitch is greater than the second pitch.

3. The semiconductor device according to claim 2, wherein the length of the first overlap region in the second direction is smaller than the third pitch.

4. The semiconductor device according to claim 2, wherein a second overlap region in which the first to third pin wirings overlap each other in the first direction is defined,

Wherein a length of the second overlap region in the second direction is smaller than the third pitch.

5. The semiconductor device of claim 1, wherein the first through third lower wiring traces are on the first metal layer,

Wherein the first to third lead wirings are on the first to third lower wiring traces, respectively.

6. The semiconductor device of claim 1, wherein the logic cell has a first cell boundary and a second cell boundary opposite the first cell boundary,

Wherein the first cell boundary and the second cell boundary extend in the second direction, an

Wherein each of the first to third wiring lines crosses at least one of the first cell boundary and the second cell boundary, each of the first to third wiring lines extending outside the logic cell.

7. The semiconductor device according to claim 6, wherein the first wiring further comprises a first power supply wiring on the first cell boundary and a second power supply wiring on the second cell boundary.

8. The semiconductor device according to claim 1, wherein

The first wiring further includes a first internal wiring,

The second wiring further includes a second internal wiring,

One end of the second internal wiring is on the first active region, the other end of the second internal wiring is on the second active region, and

The first internal wiring is electrically connected to the second internal wiring.

9. The semiconductor device of claim 1, further comprising a device isolation layer covering lower sidewalls of the first active pattern and lower sidewalls of the second active pattern,

Wherein the upper portion of each of the first active pattern and the second active pattern protrudes vertically upward from the device isolation layer.

10. The semiconductor device according to claim 1, wherein

The first active pattern includes a plurality of first channel patterns vertically stacked,

The second active pattern includes a plurality of second channel patterns vertically stacked,

A first one of the gate electrodes on the top surface, the bottom surface, and the opposite side walls of each of the first channel patterns, and

A second one of the gate electrodes is on a top surface, a bottom surface, and opposite sidewalls of each of the second channel patterns.

11. A semiconductor device, comprising:

A logic cell on a substrate, the logic cell comprising a first active region and a second active region spaced apart in a first direction;

A first active pattern on the first active region and a second active pattern on the second active region, the first active pattern and the second active pattern extending in a second direction crossing the first direction;

a device isolation layer covering lower sidewalls of the first and second active patterns, an upper portion of each of the first and second active patterns protruding vertically upward from the device isolation layer;

a first source/drain pattern at the upper portion of the first active pattern and a second source/drain pattern at the upper portion of the second active pattern;

a plurality of gate electrodes crossing the first active pattern and the second active pattern and extending in the first direction, the gate electrodes being arranged at a first pitch in the second direction;

a plurality of first wirings in the first interlayer dielectric layer on the gate electrode, each of the first wirings being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, the first wirings extending parallel to each other in the second direction; and

A plurality of second wirings in a second interlayer dielectric layer on the first interlayer dielectric layer, the second wirings extending parallel to each other in the first direction,

Wherein the method comprises the steps of

The first wiring includes first to third pin wirings,

The second wiring includes first to third wiring lines,

The first to third lead wirings are electrically connected to the first to third wiring wirings respectively,

A length of each of the first to third pin wirings in the second direction is less than twice the first pitch,

A first overlapping region in which the first to third pin wirings overlap each other in the first direction is defined, and

The length of the first overlap region in the second direction is less than the first pitch.

12. The semiconductor device according to claim 11, wherein

The first wirings are arranged at a second pitch in the first direction,

The second wirings are arranged at a third pitch in the second direction,

The third pitch is smaller than the first pitch, and

The third pitch is greater than the second pitch.

13. The semiconductor device according to claim 12, wherein the length of the first overlap region in the second direction is smaller than the third pitch.

14. The semiconductor device according to claim 11, wherein a second overlap region in which adjacent ones of the first to third lead wirings overlap each other in the first direction is defined,

Wherein a length of the second overlap region in the second direction is smaller than the first pitch.

15. The semiconductor device of claim 11, wherein the first through third lower wiring traces are on the first metal layer,

Wherein the first to third lead wirings are on the first to third lower wiring traces, respectively.

16. A semiconductor device, comprising:

A logic cell on a substrate, the logic cell comprising a first active region and a second active region spaced apart in a first direction;

A first active pattern on the first active region and a second active pattern on the second active region, the first active pattern and the second active pattern extending in a second direction crossing the first direction, the first active pattern including a plurality of first channel patterns vertically stacked, the second active pattern including a plurality of second channel patterns vertically stacked;

A first source/drain pattern on one side of the first channel pattern and a second source/drain pattern on one side of the second channel pattern;

a plurality of gate electrodes crossing the first active pattern and the second active pattern and extending in the first direction, the gate electrodes being arranged at a first pitch in the second direction;

a plurality of first wirings in the first interlayer dielectric layer on the gate electrode, each of the first wirings being electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, the first wirings extending parallel to each other in the second direction; and

A plurality of second wirings in a second interlayer dielectric layer on the first interlayer dielectric layer, the second wirings extending parallel to each other in the first direction,

Wherein the method comprises the steps of

A first one of the gate electrodes is on a top surface, a bottom surface and opposite sidewalls of each of the first channel patterns,

A second one of the gate electrodes is on a top surface, a bottom surface and opposite sidewalls of each of the second channel patterns,

The first wiring includes first to third pin wirings,

The second wiring includes first to third wiring lines,

The first to third lead wirings are electrically connected to the first to third wiring wirings respectively,

A length of each of the first to third pin wirings in the second direction is less than twice the first pitch,

A first overlapping region in which the first to third pin wirings overlap each other in the first direction is defined, and

The length of the first overlap region in the second direction is less than the first pitch.

17. The semiconductor device of claim 16, wherein

The first wirings are arranged at a second pitch in the first direction,

The second wirings are arranged at a third pitch in the second direction,

The third pitch is smaller than the first pitch, and

The third pitch is greater than the second pitch.

18. The semiconductor device of claim 17, wherein the length of the first overlap region in the second direction is less than the third pitch.

19. The semiconductor device according to claim 16, wherein a second overlap region in which adjacent ones of the first to third lead wirings overlap each other in the first direction is defined,

Wherein a length of the second overlap region in the second direction is smaller than the first pitch.

20. The semiconductor device of claim 16, wherein the first through third lower wiring traces are on the first metal layer,

Wherein the first to third lead wirings are on the first to third lower wiring traces, respectively.