CN112086115B - Memory system - Google Patents

Abstract

The invention discloses a memory system. The memory system comprises a non-volatile memory block, a random bit block and a sense amplifier. The non-volatile memory block comprises a plurality of non-volatile memory units. Each nonvolatile memory unit comprises a first storage transistor. The random bit block includes a plurality of random bit cells. Each random bit cell includes a second storage transistor and a third storage transistor. The sense amplifier senses a first read current of the nonvolatile memory cell during a read operation of the nonvolatile memory cell and senses a second read current of the random bit cell during a read operation of the random bit cell. The first storage transistor, the second storage transistor and the third storage transistor are storage transistors of the same type.

Description

Memory System

Technical Field

The present invention relates to a memory system, and in particular to a memory system with random bit blocks.

Background Art

As the functions of electronic devices become increasingly diverse, they are often equipped with chips manufactured by different companies. For example, the controller and the power management IC (PMIC) may be designed and manufactured by two different companies. However, in order to ensure that the electronic device can operate normally, the power management IC still needs to match the controller.

For example, in a wireless charging device, the power management chip must store the firmware program and related parameters to protect the normal operation of the circuit. In this case, if the firmware program is modified by hackers, the power management chip may not be able to provide overheating protection, causing safety concerns for the electronic device. Therefore, how to prevent important information stored in the power management chip or any other chip from being tampered with by hackers has become a problem to be solved.

Summary of the invention

An embodiment of the present invention provides a memory system. The memory system includes a non-volatile memory block, a random bit block, and at least one sense amplifier.

The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bit data. Each non-volatile memory cell includes a first storage transistor. The random bit block includes a plurality of random bit cells for providing a plurality of random bits. Each random bit cell includes a second storage transistor and a third storage transistor.

At least one sense amplifier is coupled to the non-volatile memory block and the random bit block. In a read operation of the non-volatile memory cell, the sense amplifier senses a first read current of the non-volatile memory cell among the plurality of non-volatile memory cells. In a read operation of the random bit cell, the sense amplifier senses at least a second read current of the random bit cell among the plurality of random bit cells.

The first storage transistor, the second storage transistor and the third storage transistor are storage transistors of the same type.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a memory system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a non-volatile memory cell according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a random bit unit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a non-volatile memory cell according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a random bit unit according to another embodiment of the present invention.

The reference numerals are described as follows:

100:Memory system

110: Non-volatile memory block

112, 212: non-volatile memory unit

120: Random bit block

122, 222: Random bit unit

130: Sense amplifier

140: Bandgap Regulator

150: High voltage generator

160, 170: control circuit

STA, STB1, STB2, STA’, STB1’, STB2’: storage transistors

V _BDG : Bandgap reference voltage

SLTA, SLTB: Select transistor

SLA, SLB: Source Line

BLA, BLB1, BLB2: bit lines

WLA, WLB: character line

ELA, ELB: Clearance Line

EGA, EGB1, EGB2: Clear components

CLA, CLB: control line

DETAILED DESCRIPTION

1 is a schematic diagram of a memory system 100 according to an embodiment of the present invention. The memory system 100 includes a non-volatile memory block 110 and a random bit block 120 .

The non-volatile memory block 110 includes a plurality of non-volatile memory cells 112 to store a plurality of bits of data, and the random bit block 120 may include a plurality of random bit cells 122 to provide a plurality of random bits. In other words, the non-volatile memory block 110 may be used to store data, and the random bit block 120 may provide random bits to generate security keys and protect the data stored in the non-volatile memory block 110.

For example, the memory system 100 can be applied to a power management chip, and the non-volatile memory block 110 can be used to store the firmware program of the power management chip. In this case, the power management chip can use the random bits provided by the random bit block 120 to generate a security key. The security key can be used to encrypt and/or decrypt transmission data to ensure that only authorized persons can access the data stored in the non-volatile memory block 110.

In some embodiments, each non-volatile memory cell 112 may include a storage transistor STA, and each random bit unit 122 may include storage transistors STB1 and STB2. In addition, the storage transistors STA, STB1, and STB2 may be storage transistors of the same type. That is, the storage transistors STA, STB1, and STB2 may perform write and read operations based on the same principle. Therefore, the non-volatile memory block 110 and the random bit block 120 may be manufactured in the same process and may share circuits in the memory system 100.

For example, in FIG. 1 , the memory system 100 may further include a sense amplifier 130. The sense amplifier 130 may be coupled to the non-volatile memory block 110 and the random bit block 120. In some embodiments, the sense amplifier 130 may sense a read current generated by the non-volatile memory cell 112 during a read operation of the non-volatile memory cell 112, and may sense a read current generated by the random bit cell 122 during a read operation of the random bit cell 122. That is, the sense amplifier 130 may be used to perform read operations of the non-volatile memory cell 112 and the random bit cell 122. In some embodiments, a plurality of non-volatile memory cells 112 may be coupled to different bit lines, and a plurality of random bit cells 122 may also be coupled to different bit lines. In this case, the memory system 100 may also include a plurality of sense amplifiers 130 to sense currents on different bit lines in parallel.

FIG. 2 is a schematic diagram of a non-volatile memory cell 112 according to an embodiment of the present invention. The non-volatile memory cell 112 may include a selection transistor SLTA, a storage transistor STA, and an erasing element EGA. The selection transistor SLTA has a first end, a second end, and a control end. The first end of the selection transistor SLTA may be coupled to the source line SLA, and the control end of the selection transistor SLTA may be coupled to the word line WLA. The storage transistor STA has a first end, a second end, and a floating gate end. The first end of the storage transistor STA may be coupled to the second end of the selection transistor SLTA, and the second end of the storage transistor STA may be coupled to the bit line BLA. The erasing element EGA may have a first end and a second end. The first end of the erasing element EGA may be coupled to the floating gate end of the storage transistor STA, and the second end of the erasing element EGA may be coupled to the erasing line ELA.

In some embodiments, the selection transistor SLTA and the storage transistor STA may be P-type transistors and may be disposed in the same N-type well NWA. In addition, in some embodiments, the clearing element EGA may be a capacitor element and may couple the floating gate of the storage transistor STA to the clearing line ELA.

Table 1 shows the voltages received by the non-volatile memory cell 112 on the source line SLA, the word line WLA, the bit line BLA and the clear line ELA during the write operation, the erase operation and the read operation.

Table 1

According to Table 1, during a write operation, the source line SLA and the N-type well NWA may be at a write voltage VPP, the word line WLA may be at an operating voltage VOP1, the bit line BLA may be at a reference voltage V0, and the clear line ELA may be raised from the reference voltage V0 to the operating voltage VOP1. In some embodiments, the write voltage VPP may be greater than the operating voltage VOP1, and the operating voltage VOP1 may be greater than the reference voltage V0. For example, the write voltage VPP may be, for example but not limited to, 8V, the operating voltage VOP1 may be, for example but not limited to, 4V, and the reference voltage V0 may be, for example but not limited to, 0V.

In this case, during the write operation, the selection transistor SLTA can be turned on, so that the first end of the storage transistor STA can receive the write voltage VPP, and the second end of the storage transistor STA can receive the reference voltage V0 via the bit line BLA. Therefore, a strong electric field is formed on the storage transistor STA to induce hot electron injection. In this way, the injected electrons will be captured by the floating gate of the storage transistor STA, so that the non-volatile memory cell 112 becomes a write state.

In addition, according to Table 1, during the read operation, the source line SLA and the N-type well NWA can be at the operating voltage VOP3, the bit line BLA can be precharged to the read voltage VR, and the clear line ELA and the word line WLA can be at the reference voltage V0. In some embodiments, the operating voltage VOP3 can be greater than the read voltage VR, and the read voltage VR can be greater than the reference voltage V0. For example, the operating voltage VOP3 can be, for example but not limited to, 2.5V, and the read voltage VR can be, for example but not limited to, 0.4V.

In this case, the selection transistor SLTA will be turned on. In addition, if the non-volatile memory cell 112 has been written, the storage transistor STA will induce a read current, and the read current will flow from the source line SLA to the bit line BLA. However, if the non-volatile memory cell 112 has not been written, the storage transistor STA will not induce a read current, or will only induce an insignificant current. Therefore, by using the sense amplifier 130 to sense the current on the bit line BLA, it is possible to determine whether the state of the non-volatile memory cell 112 is written or not written, and then read the value of the data stored in the non-volatile memory cell 112.

Furthermore, in some embodiments, the non-volatile memory cell 112 may be a memory cell that can be programmed multiple times (MTP). That is, the non-volatile memory cell 112 that has been written can also be cleared and returned to an unwritten state by a clear operation. According to Table 1, during the clear operation, the source line SLA, the N-well NWA, the bit line BLA, and the word line WLA can be at a reference voltage V0, and the clear line ELA can be at a clear voltage VEE. In some embodiments, the clear voltage VEE may be greater than the write voltage VPP. For example, the clear voltage VEE may be, for example but not limited to, 13V to 14V. In this case, the electrons captured by the storage transistor STA will be released through the clearing element EGA, so that the non-volatile memory cell 112 is cleared and returned to an unwritten state.

In FIG2 , the storage transistor STA of the non-volatile memory cell 112 can be implemented using a floating gate transistor. In this case, the storage transistors STB1 and STB2 of the random bit unit 122 can also be implemented using floating gate transistors. FIG3 is a schematic diagram of a random bit unit 122 according to an embodiment of the present invention. The random bit unit 122 may include a selection transistor SLTB, clearing elements EGB1 and EGB2, and storage transistors STB1 and STB2.

The selection transistor SLTB has a first end, a second end, and a control end. The first end of the selection transistor SLTB can be coupled to the source line SLB, and the control end of the selection transistor SLTB can be coupled to the word line WLB. The storage transistor STB1 can have a first end, a second end, and a floating gate end. The first end of the storage transistor STB1 can be coupled to the second end of the selection transistor SLTB, and the second end of the storage transistor STB1 can be coupled to the bit line BLB1. The storage transistor STB2 can have a first end, a second end, and a floating gate end. The first end of the storage transistor STB2 can be coupled to the second end of the selection transistor SLTB, and the second end of the storage transistor STB2 can be coupled to the bit line BLB2.

The clearing element EGB1 has a first end and a second end, the first end of the clearing element EGB1 is coupled to the floating gate end of the storage transistor STB1, and the second end of the clearing element EGB1 is coupled to the clearing line ELB. The clearing element EGB2 has a first end and a second end, the first end of the clearing element EGB2 is coupled to the floating gate end of the storage transistor STB2, and the second end of the clearing element EGB2 is coupled to the clearing line ELB.

3, the selection transistor SLTB and the storage transistors STB1 and STB2 may be P-type transistors and may be disposed in the same N-type well NWB. Table 2 shows the voltages received by the random bit unit 122 from the source line SLB, the word line WLB, the bit lines BLB1 and BLB2, the clear line ELB and the N-type well NWB during the register operation, the clear operation and the read operation.

Table 2

According to Table 2, during the registration operation of the random bit cell 122, the source line SLB, the clear line ELB and the N-well NWB may be at the write voltage VPP, the word line WLB may be at the operation voltage VOP2, and the bit lines BLB1 and BLB2 may be at the reference voltage V0. In some embodiments, the write voltage VPP may be greater than the operation voltage VOP2, and the operation voltage VOP2 may be greater than the reference voltage V0. For example, if the write voltage VPP is 8V and the reference voltage V0 is 0V, the operation voltage VOP2 may be, for example but not limited to, 7V.

In this case, the selection transistor SLTB can be turned on. However, if the storage transistors STB1 and STB2 are not written, the storage transistors STB1 and STB2 will have a relatively large resistance value. Therefore, the voltage at the second end of the selection transistor STLB will be raised to a high voltage close to the write voltage VPP. In this case, since the storage transistors STB1 and STB2 will have some differences in the process, one of the storage transistors STB1 and STB2 will be more likely to cause channel hot electron injection and be written first. Once one of the storage transistors STB1 and STB2 is written, that is, when the injected electrons are stored in the floating gate of one of the storage transistors STB1 and STB2, the resistance value of the storage transistor being written will decrease rapidly, and it will have a similar resistance value to the selection transistor SLTB being turned on. In this way, the voltage at the second end of the selection transistor SLTB will be reduced, thereby preventing the storage transistor that has not been written from being written.

Therefore, after the registration operation, only one of the storage transistors STB1 and STB2 will be written. In addition, since it is impossible to predict which storage transistor of the storage transistors STB1 and STB2 will be written first, the write states of the storage transistors STB1 and STB2 can be used to represent the value of the random bit. For example, if the storage transistor STB1 is written and the storage transistor STB2 is not written, it can represent that the value of the random bit is 1, and if the storage transistor STB1 is not written and the storage transistor STB2 is written, it can represent that the value of the random bit is 0.

Furthermore, during a read operation of the random bit cell 112 , the source line SLB and the N-well NWB may be at an operating voltage VOP3 , the bit lines BLB1 and BLB2 may be precharged to a read voltage VR , and the clear line ELB and the word line WLB may be at a reference voltage V0 .

In this case, the selection transistor SLTB can be turned on. In addition, if the storage transistor STB1 has been written and the storage transistor STB2 has not been written, the storage transistor STB1 will generate a read current from the source line SLB1 to the bit line BLB1, and no read current will be generated on the bit line BLB2 or only an insignificant current will be generated. Conversely, if the storage transistor STB2 has been written and the storage transistor STB1 has not been written, the storage transistor STB2 will generate a read current from the source line SLB1 to the bit line BLB2, and no read current will be generated on the bit line BLB1 or only an insignificant current will be generated.

Therefore, by using the sense amplifier 130 to sense the current on the bit lines BLB1 and BLB2 , the write state of the random bit unit 122 can be determined, and the value of the random bit can be read out.

In some embodiments, the sense amplifier 130 can compare the current on the bit line BLB1 and the current on the bit line BLB2 to determine the value of the random bit. In other words, the sense amplifier 130 can be designed to sense the current in a differential manner. Similarly, in this case, in the read operation of the non-volatile memory cell 112, the sense amplifier 130 can also compare the read current on the bit line BLA and the reference current generated by the reference memory cell to determine the value of the bit data. Therefore, the sense amplifier 130 can be used to perform the read operation of the random bit cell 122 and the non-volatile memory cell 112.

However, in some other embodiments, during the read operation of the random bit unit 122, the sense amplifier 130 may also compare the read current on the bit line BLB1 or BLB2 with a predetermined reference current to determine the value of the random bit. In other words, the sense amplifier 130 may be designed as a single-ended input. Since the write states of the storage transistors STB1 and STB2 should be complementary, during the read operation, the sense amplifier 130 may only sense the current of the bit line BLB1 or the current of the bit line BLB2. In this case, during the read operation of the non-volatile memory cell 112, the sense amplifier 130 may also compare the read current on the bit line BLA with a predetermined reference current to determine the value of the bit data. Therefore, the sense amplifier 130 can still be used to perform the read operation of the random bit unit 122 and the non-volatile memory cell 112.

Furthermore, in some embodiments, the random bit unit 122 can also be restored to an unregistered state through a clear operation. According to Table 2, in the clear operation of the random bit unit 122, the source line SLB2, the bit lines BLB1 and BLB2, the word line WLB and the N-type well NWB can be at the reference voltage V0, and the clear line ELB can be at the clear voltage VEE. In this case, the electrons stored in the floating gates of the storage transistors STB1 and STB2 can be released through the clearing elements EGB1 and EGB2, so that the storage transistors STB1 and STB2 can be restored to an unwritten state.

In some embodiments, since the voltage required for the operation of the non-volatile memory block 110 is very close to the voltage required for the operation of the random bit block 120 , the non-volatile memory block 110 and the random bit block 120 may also share the same voltage generator.

For example, in FIG. 1 , the memory system 100 may further include a band-gap regulator 140 , a high voltage generator 150 , and control circuits 160 and 170 .

The bandgap regulator 140 may provide a bandgap reference voltage V _BDG . The high voltage generator 150 may be coupled to the bandgap regulator 140 and may generate a plurality of voltages according to the bandgap reference voltage V _BDG . In this case, the control circuit 160 may be coupled to the high voltage generator 150 and the non-volatile memory block 110 and may transmit the voltage required for the operation of the non-volatile memory unit 112 from the voltage generated by the high voltage generator 150 to the non-volatile memory block 110 . In addition, the control circuit 170 may be coupled to the high voltage generator 150 and the random bit block 120 and may transmit the voltage required for the operation of the random bit unit 122 from the voltage generated by the high voltage generator 150 to the random bit block 120 .

That is, by selecting the voltages required by the non-volatile memory block 110 and the random bit block 120 through the control circuits 160 and 170, the non-volatile memory block 110 and the random bit block 120 can share the voltage generated by the high voltage generator 150. In this way, the area required by the memory system 100 can be reduced.

Since the memory system 100 may include a non-volatile memory block 110 to store data and may include a random bit block 120 to provide random bits, the random bits provided by the random bit block 120 may be used to generate a security key to protect data stored in the non-volatile memory block 110, such as a firmware program, thereby improving the security of the memory system 100. In addition, since the non-volatile memory block 110 and the random bit block 120 may be implemented with the same type of transistors, the non-volatile memory block 110 and the random bit block 120 may be manufactured in the same process and may share a sense amplifier 130 and a high voltage generator 150, thereby reducing the area and cost of the memory system 100.

Although in FIGS. 2 and 3 , the storage transistor STA in the non-volatile memory unit 112 and the storage transistors STB1 and STB2 in the random bit unit 122 may be floating gate transistors (i.e., transistors having a floating gate structure), in some other embodiments, the storage transistors STA, STB1, and STB2 may also use other types of transistors having a charge trapping structure.

4 is a schematic diagram of a non-volatile memory cell 212 according to an embodiment of the present invention. In some embodiments, the non-volatile memory cell 212 may replace the non-volatile memory cell 112 in the non-volatile memory block 110 .

The non-volatile memory cell 212 may include a selection transistor SLTA and a storage transistor STA’. The selection transistor SLTA has a first terminal, a second terminal, and a control terminal. The first terminal of the selection transistor SLTA may be coupled to the source line SLA, and the control terminal of the selection transistor SLTA may be coupled to the word line WLA. The storage transistor STA’ has a first terminal, a second terminal, and a stack gate terminal. The first terminal of the storage transistor STA’ may be coupled to the second terminal of the selection transistor SLTA, the second terminal of the storage transistor STA’ may be coupled to the bit line BLA, and the stack gate terminal of the storage transistor STA’ may be coupled to the control line CLA. In some embodiments, the storage transistor STA’ may be a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, that is, the stack gate of the storage transistor STA’ may be composed of multiple silicon layers, multiple silicon oxide layers, and silicon nitride layers.

In some embodiments, like the non-volatile memory cell 112, the non-volatile memory cell 212 can also be written by inducing hot electron injection, and the stacked gate of the storage transistor STA' can capture the injected electrons.

Similarly, the random bit unit can also be implemented by stacked gate transistors. FIG5 is a schematic diagram of a random bit unit 222 according to an embodiment of the present invention. In some embodiments, the random bit unit 222 can be used to replace the random bit unit 122 in the random bit block 120.

The random bit unit 222 may include a selection transistor SLTB, storage transistors STB1’ and STB2’. The selection transistor SLTB has a first end, a second end and a control end, the first end of the selection transistor SLTB may be coupled to the source line SLB, and the control end of the selection transistor SLTB may be coupled to the word line WLB. The storage transistor STB1’ may have a first end, a second end and a stack gate end. The first end of the storage transistor STB1’ may be coupled to the second end of the selection transistor SLTB, and the second end of the storage transistor STB1’ may be coupled to the bit line BLB1, and the stack gate end of the storage transistor STB1’ may be coupled to the control line CLB. The first end of the storage transistor STB2’ may be coupled to the second end of the selection transistor SLTB, and the second end of the storage transistor STB2’ may be coupled to the bit line BLB2, and the stack gate end of the storage transistor STB2’ may be coupled to the control line CLB.

In some embodiments, the random bit unit 222 can perform the registration operation with the similar principle as the random bit unit 122. That is, by applying an appropriate electric field to the storage transistors STB1’ and STB2’, one of the storage transistors STB1’ and STB2’ can be caused to first induce hot electron injection while preventing the other from being written. Therefore, after the registration operation is completed, the storage transistors STB1’ and STB2’ will have different write states according to their native characteristics. Since the write states caused by the storage transistors STB1’ and STB2’ in the registration operation are unpredictable, the write states of the storage transistors STB1’ and STB2’ can be used to represent the value of the random bit.

Since the non-volatile memory cell 212 and the random bit cell 222 can be implemented with the same type of storage transistors, the non-volatile memory cell 212 and the random bit cell 222 can be manufactured in the same process and can share the same sense amplifier and high voltage generator, thereby reducing the area and cost of the memory system 100.

In summary, the memory system provided by the embodiment of the present invention may include a non-volatile memory block to store data and may include a random bit block to provide random bits. Therefore, the random bits provided by the random bit block can be used to generate a security key to protect the data stored in the non-volatile memory block, such as a firmware program, so that the security of the memory system can be improved. In addition, since the non-volatile memory block and the random bit block can be implemented using the same type of storage transistors, the non-volatile memory block and the random bit block can be manufactured using the same process and can share the same sense amplifier and high-voltage generator, thereby reducing the area and cost of the memory system.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (15)

1. A memory system, comprising: The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bits of data, each of the non-volatile memory cells including a first storage transistor; The random bit block includes a plurality of random bit units for providing a plurality of random bits, each of which includes: A second selection transistor having a first terminal coupled to the second source line, a second terminal, and a control terminal coupled to the second word line; A second storage transistor having a first terminal coupled to the second terminal of the second selection transistor, a second terminal coupled to a second bit line, and a floating gate terminal; a third storage transistor having a first terminal coupled to the second terminal of the second selection transistor, a second terminal coupled to a third bit line, and a floating gate terminal; a second clear element having a first terminal coupled to the floating gate terminal of the second storage transistor and a second terminal coupled to a second clear line; and a third clear element having a first terminal coupled to the floating gate terminal of the third storage transistor and a second terminal coupled to the second clear line; and a sense amplifier coupled to the non-volatile memory block and the random bit block and configured to sense a first read current of the non-volatile memory cell among the plurality of non-volatile memory cells in a read operation of the non-volatile memory cell and to sense at least a second read current of the random bit cell among the plurality of random bit cells in a read operation of the random bit cell; The first storage transistor, the second storage transistor and the third storage transistor are storage transistors of the same type. 2. The memory system as claimed in claim 1, wherein: Each non-volatile memory cell further includes a first selection transistor and a first clear element; The first selection transistor has a first terminal coupled to the first source line, a second terminal, and a control terminal coupled to the first word line; The first storage transistor has a first terminal coupled to the second terminal of the first selection transistor, a second terminal coupled to the first bit line, and a floating gate terminal; and The first clear element has a first end coupled to the floating gate terminal of the first storage transistor, and a second end coupled to a first clear line. 3. The memory system of claim 2, wherein the first selection transistor and the first storage transistor are P-type transistors disposed in a first N-type well, and in a write operation of each non-volatile memory cell: The first source line and the first N-type well are at a write voltage; The first word line is at a first operating voltage; The first bit line is at a reference voltage; and The first clear line is raised from the reference voltage to the first operating voltage; and The write voltage is greater than the first operating voltage, and the first operating voltage is greater than the reference voltage. 4. The memory system of claim 3, wherein the second selection transistor, the second storage transistor and the third storage transistor are P-type transistors disposed in a second N-type well, and in a registration operation of each random bit cell: The second source line, the second clear line and the second N-type well are at the write voltage; the second word line is at a second operating voltage; The second bit line and the third bit line are at the reference voltage; and The write voltage is greater than the second operating voltage, and the second operating voltage is greater than the reference voltage. 5. The memory system of claim 2, wherein in a read operation of each non-volatile memory cell: The first source line is at a third operating voltage; The first bit line is precharged to a read voltage; and The first clear line and the first word line are at a reference voltage; and The third operating voltage is greater than the read voltage, and the read voltage is greater than the reference voltage. 6. The memory system of claim 5, wherein in a read operation of each random bit cell: The second source line is at the third operating voltage; The second bit line and the third bit line are precharged to the read voltage; and The second clear line and the second word line are at the reference voltage. 7. The memory system of claim 2, wherein in an erase operation of each non-volatile memory cell: The first source line, the first bit line and the first word line are at a reference voltage; The first clear line is at a clear voltage; and The clear voltage is greater than the reference voltage. 8. The memory system of claim 7, wherein in the clearing operation of each random bit cell: The second source line, the second bit line, the third bit line and the second word line are at a third operating voltage; and The second clear line is at the reference voltage. 9. The memory system as claimed in claim 2, wherein: In a read operation of each non-volatile memory cell, the sense amplifier compares the first read current of the first bit line with a reference current generated by a reference memory cell to determine a read bit data; and In a read operation of each random bit cell, the sense amplifier compares the second read current of the second bit line with a third read current of the third bit line to determine a random bit. 10. The memory system as claimed in claim 2, wherein: In a read operation of each non-volatile memory cell, the sense amplifier compares the first read current of the first bit line with a first predetermined reference current to determine read bit data; and In a read operation of each random bit cell, the sense amplifier compares the second read current of the second bit line with a second predetermined reference current to determine a random bit. 11. The memory system of claim 1, further comprising: A bandgap regulator for providing a bandgap reference voltage; a high voltage generator, coupled to the bandgap regulator, and configured to generate a plurality of voltages according to the bandgap reference voltage; A first control circuit coupled to the high voltage generator and the non-volatile memory block, for outputting voltages required by the non-volatile memory units from among the plurality of voltages to the non-volatile memory units; and The second control circuit is coupled to the high voltage generator and the random bit block, and is used for outputting the voltages required by the random bit units among the multiple voltages to the random bit units. 12. The memory system of claim 1, wherein: The plurality of non-volatile memory cells further include a first select transistor; The first selection transistor has a first terminal coupled to the first source line, a second terminal, and a control terminal coupled to the first word line; and The first storage transistor has a first terminal coupled to the second terminal of the first selection transistor, a second terminal coupled to a first bit line, and a stack gate terminal coupled to a first control line. 13. A memory system, comprising: The non-volatile memory block includes a plurality of non-volatile memory cells for storing a plurality of bit data, each of which includes a first storage transistor; the random bit block includes a plurality of random bit cells for providing a plurality of random bits, each of which includes: A second selection transistor having a first terminal coupled to the second source line, a second terminal, and a control terminal coupled to the second word line; A second storage transistor having a first terminal coupled to the second terminal of the second selection transistor, a second terminal coupled to a second bit line, and a stack gate terminal coupled to a second control line; and a third storage transistor having a first terminal coupled to the second terminal of the second selection transistor, a second terminal coupled to a third bit line, and a stack gate terminal coupled to the second control line; and a sense amplifier coupled to the non-volatile memory block and the random bit block and configured to sense a first read current of the non-volatile memory cell among the plurality of non-volatile memory cells in a read operation of the non-volatile memory cell and to sense at least a second read current of the random bit cell among the plurality of random bit cells in a read operation of the random bit cell; The first storage transistor, the second storage transistor and the third storage transistor are storage transistors of the same type. 14. The memory system of claim 13, wherein the first storage transistor, the second storage transistor, and the third storage transistor have a charge trapping structure. 15. The memory system of claim 13, wherein the first storage transistor, the second storage transistor, and the third storage transistor have a floating gate structure.

Images