CN112071899A - Semiconductor structure and method of making the same - Google Patents

Abstract

A semiconductor structure and its preparation method, its structure includes the substrate of the first doping type, cross-over area, first injection region and second injection region are the second doping type, define the ditch groove area on the cross-over area, the ditch groove area divides the substrate into multiple chip areas; the first injection region and the second injection region are both communicated with the penetration region. The first injection region and the substrate form a PN junction, the second injection region and the substrate also form a PN junction, and the first injection region and the second injection region are communicated through the through region, so various devices of the PN junction can be formed in the substrate, the device can select to lead out electrodes at different positions according to the requirement of circuit design, and the device can be processed into devices with different functions.

Description

Semiconductor structure and method of making the same

technical field

The present invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.

Background technique

Using different doping processes, through diffusion, the P-type semiconductor and N-type semiconductor are fabricated on the same semiconductor (usually silicon or germanium) substrate, and a space charge region is formed at their interface, which is called a PN junction ( PNjunction). The PN junction has unidirectional conductivity, which is a feature used by many devices in electronic technology. The material basis of commonly used devices such as semiconductor diodes and bipolar transistors is the PN junction. With the development of integrated circuits (ICs), the semiconductor industry has experienced rapid growth due to continued improvements in the integration density of individual semiconductor devices (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the continuous reduction in minimum feature size, which allows more components to be integrated into a given area.

With the development of smart home appliances of various sizes, the usage scenarios of semiconductor devices are becoming more and more frequent, and it is even necessary to integrate multiple semiconductor devices in one integrated circuit board. Different customers will have different circuit designs. Therefore, it is necessary to have different Functional semiconductor devices are integrated in the application circuit board in different packaging methods, and semiconductor devices with different functions and packaging methods require different processing or manufacturing methods, resulting in high production costs.

Therefore, it is necessary to provide a semiconductor structure that can be used in different usage scenarios and a manufacturing method thereof, so that it can be processed into devices with different functions according to the needs of circuit design, thereby improving efficiency and reducing production costs.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor structure and a manufacturing method thereof, which can be rapidly processed into devices with different functions according to requirements, thereby improving production efficiency and reducing production costs.

According to a first aspect, an embodiment provides a method for fabricating a semiconductor structure, including:

providing a substrate of a first doping type, the substrate having a first surface and a second surface opposite the first surface;

A punch-through process is used to punch through the substrate to form a punch-through region, the punch-through region is of the second doping type, a trench region is defined on the punch-through region, and the trench region divides the substrate into Multiple chip areas;

Using a diffusion process, a first implantation region is formed on the first surface of the substrate, and a second implantation region is formed on the second surface; the first implantation region is located inside the substrate deep along part of the first surface, so The first implanted region is of the same doping type as the through region, and communicated with the through region; the second implanted region is located inside the substrate deep along the second surface, and the second implanted region is connected to the through region. The doping type of the through region is the same, and is communicated with the through region.

In some embodiments, the method further includes: using a diffusion process to form a third implantation region, the third implantation region is located inside the substrate deep along a part of the first surface, and is not communicated with the first implantation region, and the third implantation region is The implanted regions are of the same doping type as the punch-through regions.

In some embodiments, it also includes:

Passivation is performed on the surface of the substrate by using a passivation process;

Adopt photolithography process, use photoresist as a mask, and etch to expose the lead-out electrode window;

A metal layer is deposited on the conductive window to form an electrode.

In some embodiments, a photolithography process is used, a photoresist is used as a mask, and etching is performed to expose the lead-out electrode window, including:

Etching to expose the surface of the second implantation region and the surface of the first surface except the remaining part of the first implantation region, as a lead-out electrode window;

In some embodiments, a photolithography process is used, a photoresist is used as a mask, and etching is performed to expose the lead-out electrode window, including:

Etching is performed to expose the surface of the first implantation region and the surface of the first surface except for the remaining part of the first implantation region as a lead-out electrode window.

In some embodiments, a photolithography process is used, a photoresist is used as a mask, and etching is performed to expose the lead-out electrode window, including:

Etching is performed to expose the surface of the first implantation region, the surface of the third implantation region, and the surface of the remaining part of the first surface except the first implantation region and the third implantation region, as a lead-out electrode window.

In some embodiments, a photolithography process is used, a photoresist is used as a mask, and etching is performed to expose the lead-out electrode window, including:

Etching is performed to expose the surface of the second implantation region, the surface of the third implantation region, and the surface of the rest of the first surface except the first implantation region and the third implantation region, as a lead-out electrode window.

In some embodiments, a photolithography process is used, a photoresist is used as a mask, and etching is performed to expose the lead-out electrode window, including:

Etching to expose the surface of the first implanted region and the surface of the third implanted region as a lead-out electrode window.

In some embodiments, a photolithography process is used, a photoresist is used as a mask, and etching is performed to expose the lead-out electrode window, including:

Etching to expose the surface of the second implanted region and the surface of the third implanted region as a lead-out electrode window.

In some embodiments, after depositing a metal layer on the conductive window and forming an electrode, the method further includes:

Dicing is performed in defined trench areas to separate individual chip areas.

According to a second aspect, an embodiment provides a semiconductor structure including:

a substrate of a first doping type, the substrate having a first surface and a second surface opposite the first surface;

a through region disposed inside the substrate, the through region is of the second doping type, a trench region is defined on the through region, and the trench region divides the substrate into a plurality of chip regions;

a first implantation region, located inside the substrate deep along a part of the first surface, the first implantation region is of the same doping type as the through region, and communicated with the through region;

and a second implantation region, located inside the substrate deep along the second surface, the second implantation region is of the same doping type as the through region, and communicated with the through region.

In some embodiments, it further includes: a third implantation region, located inside the substrate deep along a part of the first surface, not communicating with the first implantation region, and the doping type of the third implantation region and the punch-through region same.

According to the method for fabricating the semiconductor structure of the above-mentioned embodiment, since there are a first implantation region and a second implantation region in the direction of the first surface and the second surface of the substrate, wherein the first implantation region and the substrate have The bottom can form a PN junction, the second implantation region and the substrate can also form a PN junction, and since the first implantation region and the second implantation region are connected through a through region, the substrate can Various devices forming PN junction, the device can choose to lead out electrodes at different positions according to the needs of circuit design, so as to process into devices with different functions, improve the flexibility of application, because the pre-process is fixed, it is unnecessary to design more masks. Stencils or other etching steps, therefore, can improve production efficiency and reduce manufacturing costs.

Description of drawings

FIG. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

2-4 are schematic structural diagrams of semiconductor devices provided by different embodiments of the present invention;

5 is a schematic diagram of a semiconductor structure provided by another embodiment of the present invention;

6-10 are schematic structural diagrams of semiconductor devices provided by different embodiments of the present invention;

FIG. 11 and FIG. 12 are flowcharts of methods for fabricating semiconductor devices according to different embodiments of the present invention.

Detailed ways

The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments have used associated similar element numbers. In the following embodiments, many details are described so that the present application can be better understood. However, those skilled in the art will readily recognize that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, and methods. In some cases, some operations related to the present application are not shown or described in the specification, in order to avoid the core part of the present application from being overwhelmed by excessive description, and for those skilled in the art, these are described in detail. The relevant operations are not necessary, and they can fully understand the relevant operations according to the descriptions in the specification and general technical knowledge in the field.

Additionally, the features, acts, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can also be exchanged or adjusted in order in a manner obvious to those skilled in the art. Therefore, the various sequences in the specification and drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a necessary order unless otherwise stated, a certain order must be followed.

The serial numbers themselves, such as "first", "second", etc., for the components herein are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "connection" mentioned in this application, unless otherwise specified, include both direct and indirect connections (connections).

It can be seen from the analysis that different semiconductor devices need to be designed according to the needs of different integrated circuits when they are packaged, and different packaging structures will affect the chip design structure of the semiconductor device. Therefore, in the manufacturing process of the semiconductor device It is necessary to redesign the manufacturing process according to the semiconductor devices required by each customer. In particular, in the manufacturing process, it involves the design of various lithography masks, which greatly increases the production cost, and, The repeatability of the process is low, the design and production require time and manpower, and the production efficiency is greatly reduced.

Semiconductor devices with different functions need to be integrated in the application circuit board in different packaging methods, and semiconductor devices with different functions and different packaging methods require different processing or manufacturing methods, resulting in higher manufacturing costs.

In an embodiment of the present invention, a semiconductor structure and a method for fabricating the same are provided. The semiconductor structure fabricated by the method includes a substrate of a first doping type, a through region, a first implantation region, and a second implantation region. The through region Region, the first implantation region and the second implantation region are of the second doping type, a trench region is defined on the through region, and the trench region divides the substrate into a plurality of chip regions; the first implantation region is located along a portion of the first surface deep inside the substrate and communicated with the through region; and a second implantation region located deep inside the substrate along the second surface and communicated with the through region. The first implanted region and the substrate form a PN junction, and the second implanted region and the substrate also form a PN junction. Since the first implanted region and the second implanted region are connected through the punch-through region, the PN junction can be formed in the substrate. Various devices, the device can choose to lead out electrodes at different positions according to the needs of circuit design, so as to be processed into devices with different functions, which has strong application flexibility. Because the pre-process is fixed, it is unnecessary to design more masks. or other etching steps, therefore, the production efficiency can be improved, and the manufacturing cost can also be reduced.

Example 1

Referring to FIG. 1 , a semiconductor structure is provided in this embodiment, including: a substrate of a first doping type, a through region, a first implantation region, and a second implantation region.

The substrate 100 of the first doping type has a first surface 101 and a second surface 102 opposite the first surface 101 .

In this embodiment, the substrate 100 is a silicon substrate, and impurities are doped in the silicon substrate to form the substrate 100 of the first doping type.

The first doping type may be N-type semiconductor doping or P-type semiconductor doping. When the N-type semiconductor is doped, the substrate 100 may be doped with a small amount of impurity phosphorus element (or antimony element); when the P-type semiconductor is doped, the substrate 100 may be doped with A small amount of impurity boron element (or indium element).

In this embodiment, the substrate 100 is N-type doped.

In some embodiments, the substrate 100 is P-type doped.

The through region 110 disposed inside the substrate is of the second doping type, a trench region (not shown) is defined on the through region 110 , and the trench region divides the substrate 100 into a plurality of chip area.

The second doping type may be N-type semiconductor doping or P-type semiconductor doping. When the N-type semiconductor is doped, the substrate 100 may be doped with a small amount of impurity phosphorus element (or antimony element); when the P-type semiconductor is doped, the substrate 100 may be doped with A small amount of impurity boron element (or indium element).

It should be noted that when the first doping type is N-type semiconductor doping, the second doping type needs to be P-type semiconductor doping; when the first doping type is P-type semiconductor doping, the The second doping type needs to be an N-type semiconductor doping.

In this embodiment, the through region 110 is P-type doped through along the thickness of the substrate 100 .

In some embodiments, the through region 110 is an N-type doped through through the thickness of the substrate 100 .

As shown in FIG. 1 , the first implanted region 201 is located inside the substrate along a portion of the first surface 101 . The first implanted region 201 has the same doping type as the through region 110 and is of the same doping type as the through region 110 . connected.

The second implanted region 202 is located deep inside the substrate along the second surface 102 , the second implanted region 202 is of the same doping type as the through region 110 , and communicated with the through region 110 .

Since the first implanted region 201 in this embodiment is P-type, it forms a PN junction with the N-type substrate 100 , and the second implanted region 202 also forms a PN junction with the substrate 100 . The region 202 is connected through the through region 110, thus forming a PN junction, the device can choose to lead out electrodes at different positions according to the needs of the circuit design, so as to be processed into devices with different functions, which has strong application flexibility. The process is fixed, and there is no need to design a mask or other etching steps. Therefore, the production efficiency can be improved and the manufacturing cost can be reduced.

Referring to FIG. 2 , the PN junction semiconductor structure of this embodiment may have three positions of external electrodes, namely a first electrode position 301 , a second electrode position 302 and a third electrode position 303 , wherein the first electrode position 301 is located at The remaining part of the surface of the first surface except the first implantation region 201; the second electrode position 302 is located on the surface of the second implantation region 202, and the third electrode position 303 is located on the surface of the first implantation region.

In some embodiments, referring to FIG. 3 , the surface of the second implanted region 202 has a metal layer, and the rest of the first surface 101 has a metal layer.

In some embodiments, referring to FIG. 4 , the surface of the first implanted region 201 has a metal layer, and the rest of the first surface has a metal layer.

In this embodiment, a flow chart of a method for fabricating a semiconductor structure is also provided. Please refer to FIG. 11 in conjunction with the fabrication method. The fabrication method includes:

Step 1, providing a substrate of a first doping type, the substrate having a first surface and a second surface opposite to the first surface.

In this embodiment, the substrate 100 is a silicon substrate, and impurities are doped in the silicon substrate to form the substrate 100 of the first doping type.

The first doping type may be N-type semiconductor doping or P-type semiconductor doping. When the N-type semiconductor is doped, the substrate 100 may be doped with a small amount of impurity phosphorus element (or antimony element); when the P-type semiconductor is doped, the substrate 100 may be doped with A small amount of impurity boron element (or indium element).

In this embodiment, the substrate 100 is N-type doped.

In some embodiments, the substrate 100 is P-type doped.

Step 2, using a punch-through process to punch through the substrate to form a punch-through region, the punch-through region is of the second doping type, and a trench region is defined on the punch-through region, and the trench region connects the lining The bottom is divided into a plurality of chip regions.

The second doping type may be N-type semiconductor doping or P-type semiconductor doping. When the N-type semiconductor is doped, the substrate 100 may be doped with a small amount of impurity phosphorus element (or antimony element); when the P-type semiconductor is doped, the substrate 100 may be doped with A small amount of impurity boron element (or indium element).

It should be noted that when the first doping type is N-type semiconductor doping, the second doping type needs to be P-type semiconductor doping; when the first doping type is P-type semiconductor doping, the The second doping type needs to be an N-type semiconductor doping.

For example, a P-type punch-through region is formed on an N-type silicon wafer by a punch-through process, and the punch-through region may also function as a punch-through isolation layer.

In this embodiment, the through region 110 is P-type doped through along the thickness of the substrate 100 .

In some embodiments, the through region 110 is an N-type doped through through the thickness of the substrate 100 .

Step 3: Using a diffusion process, a first implantation region is formed on the first surface of the substrate, and a second implantation region is formed on the second surface; the first implantation region is located in the substrate deep along a portion of the first surface Inside, the first implanted region is of the same doping type as the through region, and communicated with the through region; the second implanted region is located inside the substrate deep along the second surface, and the second implanted region The region is of the same doping type as the punch-through region and communicates with the punch-through region.

In this embodiment, the material of the mask layer in the diffusion process is silicon dioxide.

A P-type layer or an N-type layer is formed on both sides of the substrate by a planar diffusion method to form a PN junction.

It should be noted that the size and number of the formed PN junctions can be adjusted as required.

In this embodiment, the junction depth of the PN junction formed by the diffusion process may be 30-60um; the longer the diffusion time, the deeper the junction; the longer the diffusion time, the higher the voltage. Different voltage products require different diffusion times, which can be made according to the needs of specific products.

Step 4, using a passivation process to passivate the surface of the substrate.

In this embodiment, thermal oxidation can be used for passivation, for example, oxygen+dry oxygen or hydrogen-oxygen synthesis, or Sipos (Semi-Insulating Polycrystalline Silicon, semi-insulating polycrystalline silicon) deposition or silicon nitride deposition, or Sipos+ Silicon nitride, or Sipos+ thermal oxidation, or adding LTO (LowTemperature Oxidation, low temperature silicon dioxide film) on the basis of the above passivation layer.

In this embodiment, when an oxide layer is selected for the passivation layer, its thickness can be 12 kÅ to 14 kÅ, which can be adjusted according to process requirements.

When Sipos is used for the passivation layer, its thickness can be 3 kÅ-23kÅ, which can be adjusted according to the needs of the process.

When LTO is used for the passivation layer, its thickness can be 4 kÅ-8kÅ, which can be adjusted according to the needs of the process.

When the passivation layer is Si3N4 (silicon nitride), its thickness can be 700-1200 Å, which can be adjusted according to the needs of the process.

Step 5, using a photolithography process, using a photoresist as a mask, and performing etching to expose the lead-out electrode window.

After the above process, when the lead-out electrode window is etched to expose the lead-out electrode window, there can be various etching methods, so that the lead-out electrode window can be used at different positions to form devices with different functions.

Step 6, depositing a metal layer on the conductive window to form an electrode.

For example, there may be three positions of external electrodes, namely a first electrode position 301, a second electrode position 302 and a third electrode position 303, wherein the first electrode position 301 is located on the first surface except the first implanted region The remaining part of the surface of 201; the second electrode position 302 is located on the surface of the second injection region 202, and the third electrode position 303 is located on the surface of the first injection region.

In some embodiments, the metal layer is located at the first electrode location 301 and the third electrode location 303 .

In some embodiments, the metal layer is located at the second electrode position 302 and the first electrode position 301, which may be suitable for packaging when the circuit terminals are at both ends of the device.

In this embodiment, after depositing a metal layer on the conductive window and forming an electrode, the method further includes:

Dicing is performed in defined trench areas to separate individual chip areas.

In some embodiments, after cutting and separating each of the chip regions, the side surfaces of the chip regions may also be passivated to ensure the effectiveness of device functions.

Embodiment 2

The difference between this embodiment and the first embodiment is that the structure further includes a third implantation region, and the third implantation region is located inside the substrate deep along a part of the first surface, and is not in communication with the first implantation region. The rest of the parts are the same as those in the embodiment. To avoid redundancy in the article, only the difference parts are described in detail in this embodiment.

Referring to FIG. 5 , in this embodiment, the structure further includes a third implantation region 203 , which is located inside the substrate 100 along a portion of the first surface 101 and is not in communication with the first implantation region 201 . The third implanted region 203 has the same doping type as the through region 110 .

Since the third implantation region 203 in this embodiment is P-type and forms a PN junction with the N-type substrate 100 , a PN junction is formed, and the structure has two PN junctions, which is a PNP structure or an NPN structure, depending on the circuit According to the needs of the design, the electrodes can be selected at different positions, which can be processed into devices with different functions, such as triodes or bidirectional TVS, or can be used as diodes or unidirectional TVS, which has strong application flexibility, because the pre-process is fixed. , it is not necessary to design more masks or other etching steps, therefore, the production efficiency can be improved, and the manufacturing cost can also be reduced.

Please refer to FIG. 6 , the PN junction semiconductor structure of this embodiment may have four positions of external electrodes, namely the first electrode position 401 , the second electrode position 402 , the third electrode position 403 and the fourth electrode position 404 , wherein , the first electrode position 401 is located on the surface of the first injection region 201 , the second electrode position 402 is located on the remaining surface of the first surface except the first injection region and the third injection region, and the third electrode position 403 is located in the third On the surface of the implanted region 203 , the fourth electrode position 404 is located on the surface of the second implanted region 202 .

Please refer to FIG. 7 , in some embodiments, the surface of the first implantation region 201 has a metal layer, the surface of the third implantation region 203 has a metal layer, and the first implantation region 201 and the first implantation region 201 are removed from the first surface 101 . The rest of the surface of the third implanted region 203 has a metal layer, that is, the metal layer is located at the first electrode position 401 and the second electrode position 402 .

Through this electrode access method, a unidirectional TVS can be formed, or it can be a rectifier diode or other PN junction device, and the external electrodes of the device are on the same side, which can be applied to the package directly mounted on the PCB board. form.

Please refer to FIG. 8 , in some embodiments, the surface of the second implantation region 202 has a metal layer, the surface of the third implantation region 203 has a metal layer, and the first implantation region 201 and the first implantation region 201 are removed from the first surface 101 . The rest of the surface of the third injection region 203 has a metal layer, that is, the metal layer is located at the fourth electrode position 404 , the third electrode position 403 and the second electrode position 402 .

Through this electrode access method, a device with a PNP structure can be formed, and the PNP device can be a triode device. When the device is packaged, it is suitable for packaging when the circuit terminals are at both ends of the device.

Please refer to FIG. 9 , in some embodiments, the surface of the first implantation region 201 has a metal layer, and the surface of the third implantation region 203 has a metal layer, that is, the metal layer is located at the first electrode position 401 and the third Electrode location 403 .

Through this electrode wiring method, the formed device can be a bidirectional TVS device, and the external electrodes of the device are on the same surface, which can be suitable for a package type directly mounted on a PCB board.

Referring to FIG. 10 , in some embodiments, the surface of the second implantation region 202 has a metal layer, and the surface of the third implantation region 203 has a metal layer, that is, the metal layer is located at the fourth electrode position 404 and the third electrode Location 403.

Through this electrode wiring method, the formed device can be a bidirectional TVS device, which can be the same as the device in the embodiment corresponding to FIG. 9. However, the external electrodes of the device in this embodiment are at both ends, Can be used for packaging where circuit terminations are at both ends of the device.

Referring to FIG. 12 , a method for fabricating a semiconductor structure is also provided in this embodiment. The difference between the fabrication method and the fabrication method in Embodiment 1 is that the structure further includes a diffusion process to form a third implantation region. The three implanted regions are located inside the substrate deep along a portion of the first surface, and are not in communication with the first implanted regions. The rest of the parts are the same as those in the first embodiment. In order to avoid redundant articles, only the different parts are described in detail in this embodiment.

Step 1, providing a substrate of a first doping type, the substrate having a first surface and a second surface opposite to the first surface.

Step 2, using a punch-through process to punch through the substrate to form a punch-through region, the punch-through region is of the second doping type, and a trench region is defined on the punch-through region, and the trench region connects the lining The bottom is divided into a plurality of chip regions.

Step 3: Using a diffusion process, a first implantation region is formed on the first surface of the substrate, and a second implantation region is formed on the second surface; the first implantation region is located in the substrate deep along a portion of the first surface Inside, the first implanted region is of the same doping type as the through region, and communicated with the through region; the second implanted region is located inside the substrate deep along the second surface, and the second implanted region The region is of the same doping type as the punch-through region and communicates with the punch-through region.

In this embodiment, between step 3 and step 4, it also includes:

In step 31, a diffusion process is used to form a third implantation region, the third implantation region is located inside the substrate deep along part of the first surface, and is not connected to the first implantation region, and the third implantation region is connected to the first implantation region. The doping types of the punch-through regions are the same.

Step 4, using a passivation process to passivate the surface of the substrate.

Step 5, using a photolithography process, using a photoresist as a mask, and performing etching to expose the lead-out electrode window.

Referring to FIG. 6, in this embodiment, a photolithography process is used, a photoresist is used as a mask, and etching is performed to expose the lead-out electrode window. An electrode position 401, a second electrode position 402, a third electrode position 403, and a fourth electrode position 404, wherein the first electrode position 401 is located on the surface of the first implantation region 201, and the second electrode position 402 is located in the first surface The third electrode position 403 is located on the surface of the third injection region 203 , and the fourth electrode position 404 is located on the surface of the second injection region 202 , except for the rest of the surfaces of the first and third injection regions.

Step 6, depositing a metal layer on the conductive window to form an electrode.

In some embodiments, the surface of the first implantation region, the surface of the third implantation region, and the first surface can be exposed by etching, using a photolithography process, using a photoresist as a mask, and performing etching. The surface of the rest of the first implanted region and the third implanted region is used as a lead-out electrode window.

In some embodiments, the surface of the second implantation region, the surface of the third implantation region, and the first surface can be exposed by etching, using a photolithography process, using a photoresist as a mask, and performing etching. The surface of the rest of the first implanted region and the third implanted region is used as a lead-out electrode window.

In some embodiments, the surface of the first implantation region and the surface of the third implantation region can be exposed as lead-out electrode windows by etching, using a photolithography process, using a photoresist as a mask, and performing etching.

In some embodiments, the surface of the second implantation region and the surface of the third implantation region can be exposed as lead-out electrode windows by etching, using a photolithography process, using a photoresist as a mask, and performing etching.

In this embodiment, after depositing a metal layer on the conductive window and forming an electrode, the method further includes:

Cutting is performed in the defined trench area to separate each chip area, and the side surfaces of the chip area are passivated to ensure the effectiveness of the device function.

The semiconductor structure and its fabrication method provided in this embodiment can be selected to lead out electrodes at different positions according to the needs of circuit design, so as to be processed into devices with different functions, and the flexibility of application is improved. Multiple design masks or other etching steps, therefore, can improve production efficiency and reduce manufacturing costs.

The above specific examples are used to illustrate the present invention, which are only used to help understand the present invention, and are not intended to limit the present invention. For those skilled in the art to which the present invention pertains, according to the idea of the present invention, several simple deductions, modifications or substitutions can also be made.

Claims (10)

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate of a first doping type, the substrate having a first surface and a second surface opposite to the first surface;

adopting a punch-through process to punch through the substrate to form a punch-through area, wherein the punch-through area is of a second doping type, a groove area is defined on the punch-through area, and the groove area divides the substrate into a plurality of chip areas;

forming a first injection region on the first surface of the substrate and a second injection region on the second surface of the substrate by adopting a diffusion process; the first injection region is positioned in the substrate which is deep along part of the first surface, and the first injection region and the through region have the same doping type and are communicated with each other; the second injection region is positioned in the substrate which is deep along the second surface, and the second injection region and the through region have the same doping type and are communicated with each other.

2. The method of manufacturing of claim 1, further comprising: and forming a third injection region by adopting a diffusion process, wherein the third injection region is positioned in the substrate which is deep along part of the first surface and is not communicated with the first injection region, and the third injection region and the through region have the same doping type.

3. The method of manufacturing of claim 2, further comprising:

passivating the surface of the substrate by adopting a passivation process;

adopting a photoetching process, using a light resistance as a mask, and etching to expose a lead-out electrode window;

and depositing a metal layer on the lead-out electrode window to form an electrode.

4. The method of claim 3, wherein the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and performing etching comprises:

etching to expose the surface of the second injection region and the surface of the rest part of the first surface except the first injection region as a lead-out electrode window;

or,

etching to expose the surface of the first implantation region and the surface of the rest part of the first surface except the first implantation region as a lead-out electrode window.

5. The method of claim 3, wherein the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and performing etching comprises:

etching to expose the surface of the first implantation region, the surface of the third implantation region and the surface of the rest part of the first surface except the first implantation region and the third implantation region to be used as a lead-out electrode window.

6. The method of claim 3, wherein the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and performing etching comprises:

etching to expose the surface of the second injection region, the surface of the third injection region and the surface of the rest part of the first surface except the first injection region and the third injection region to be used as a lead-out electrode window.

7. The method of claim 3, wherein the exposing the lead-out electrode window by using a photolithography process and using a photoresist as a mask and performing etching comprises:

etching to expose the surface of the first injection region and the surface of the third injection region as a lead-out electrode window;

or,

etching to expose the second and third implantation region surfaces as a lead-out electrode window.

8. The method of claim 3, wherein depositing a metal layer over the exit electrode window, after forming the electrode, further comprises:

and cutting in the defined groove region to separate the chip regions.

9. A semiconductor structure, comprising:

a substrate of a first doping type, the substrate having a first surface and a second surface opposite the first surface;

the through area is arranged in the substrate, the through area is of a second doping type, a groove area is defined on the through area, and the groove area divides the substrate into a plurality of chip areas;

the first injection region is positioned in the substrate which is deep along part of the first surface, and the first injection region and the through region have the same doping type and are communicated with each other;

and a second implantation region located inside the substrate deep along the second surface, the second implantation region having the same doping type as the through region and being in communication with the through region.

10. The semiconductor structure of claim 9, further comprising:

and the third injection region is positioned in the substrate which is deep along part of the first surface and is not communicated with the first injection region, and the doping type of the third injection region is the same as that of the through region.

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