CN112071896A - A lateral 4H-SiC MOSFET power device - Google Patents

Abstract

The invention discloses a lateral 4H-SiC MOSFET power device. From bottom to top, it includes: P+ substrate, P-epitaxial layer, P buried layer, N-drift region, Pwell region, Ptop region, P+ contact region, N+ source region, N+ drain region, silicon dioxide dielectric layer, source electrode , drain and gate; wherein the Ptop region is divided into two sub-regions, the first Ptop region and the second Ptop region. The lateral 4H-SiC MOSFET power device proposed by the present invention introduces the idea of step doping, which can effectively improve the electric field distribution of the device, thereby increasing the breakdown voltage of the device; at the same time, the P buried layer can assist in depleting the N-drift region, making the The doping concentration of the N-drift region can be higher, which reduces the characteristic on-resistance of the device and improves the overall electrical performance of the device.

Description

A lateral 4H-SiC MOSFET power device

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a lateral 4H-SiC MOSFET power device.

Background technique

Compared with traditional Si materials, SiC materials have many superior material properties, such as wide band gap, high breakdown field strength, high thermal conductivity, etc., which make SiC materials well used in high temperature, high pressure and power devices. Among the various isomers of SiC, 4H-SiC is the most promising material for power application scenarios due to its high and isotropic bulk mobility. Compared with the vertical structure, SiC lateral double-diffused MOSFET (LDMOS) is more suitable for high-voltage power integrated circuits. Researchers have proposed a variety of 4H-SiC LDMOS structures.

In order to obtain better device performance, reduced surface electric field technology (RESURF) is widely used to design SiC LDMOS. RESURF technology can make the surface electric field distribution more uniform, thereby improving the breakdown voltage of the device. And it can promote the depletion of the drift region, thereby increasing the doping concentration of the drift region to reduce the on-resistance. The conventional dual RESURF LDMOS structure with uniformly doped Ptop region improves the breakdown voltage and reduces the on-resistance to a certain extent, but the electric field distribution in the horizontal direction of its surface has two very high electric field peaks at both ends, In the middle of the drift region, there is an obvious electric field sag. Such a transverse electric field distribution is not ideal, and its longitudinal electric field distribution also needs to be optimized.

SUMMARY OF THE INVENTION

In order to solve the problems in the background art, the present invention provides a novel high-voltage lateral 4H-SiC LDMOS power device, the Ptop region is uniformly divided into a first Ptop region with a doping concentration of 3×10 ¹⁷ cm ^-3 and a doping A second Ptop region with a concentration of 2 × 10 ¹⁷ cm ^-3 and a buried P layer with a doping concentration of 2 × 10 ¹⁷ cm ^-3 are added to the surface of the P-epitaxial layer.

The technical scheme adopted in the present invention is as follows:

Power devices are mainly composed of P+ substrate, P- epitaxial layer, P buried layer, N-drift region, Pwell region, Ptop region, P+ contact region, N+ source region, N+ drain region, silicon dioxide dielectric layer, source, drain. The electrode and the gate are sequentially composed from bottom to top; the source electrode, the drain electrode and the gate electrode are located in the silicon dioxide dielectric layer, the source electrode and the drain electrode are arranged in parallel on the lower part of both sides of the silicon dioxide dielectric layer, and the gate electrode is arranged close to the source electrode and formed on the upper part of the silicon dioxide dielectric layer;

The Pwell region, the Ptop region and the N+ drain region are located in the N-drift region. The Pwell region and the N+ drain region are respectively formed on both sides of the upper part of the N-drift region. The P+ contact region and the N+ source region are located in the Pwell region. The P+ contact region is formed in the On the upper part of one side of the Pwell region, the N+ source region is set close to the P+ contact region; the Ptop region is formed in the upper middle of the N-drift region, and the Ptop region is divided into two sub-regions: the first Ptop region and the second Ptop region;

The P buried layer is located in the P- epitaxial layer, and the P buried layer is formed on the upper part of one side of the P- epitaxial layer.

The upper end surface of the Ptop region contacts the lower end surface of the silicon dioxide dielectric layer 10 , and the upper end surface of the P buried layer 3 contacts the lower end surface of the N-drift region 4 .

The depth of the first Ptop region is 0.4um, the length is 4.2um, and the doping concentration is 3×10 ¹⁷ cm ⁻³ ; the depth of the second Ptop region is 0.4um, the length is 4.2um, and the doping concentration is 2×10 ¹⁷ cm ⁻³ . ³ .

The distance between the Pwell region and the first Ptop region is 1.5 μm, and the distance between the second Ptop region and the N+ drain region is 2.5 μm.

The P buried layer, the Pwell region and the source electrode are located on the same side.

The depth of the P buried layer is 0.4 μm, the length is 7 μm, and the doping concentration is 2×10 ¹⁷ cm ⁻³ .

The thickness of the N-drift region is 4 μm, and the doping concentration is 5×10 ¹⁶ cm ⁻³ .

The thickness of the Pwell region is 1 μm, and the doping concentration is 2×10 ¹⁷ cm ⁻³ .

The thickness of the P-epitaxial layer is 10 μm, and the doping concentration is 5×10 ¹⁵ cm ⁻³ .

The channel length of the power device is 0.5 μm, and the gate oxide thickness of the power device is 50 nm.

The channel length is the distance between the side of the N+ source region close to the Ptop region and the side of the Pwell region close to the Ptop region; the gate oxide thickness is the distance between the bottom edge of the gate and the top edge of the Pwell region.

The beneficial effects of the present invention are:

The invention utilizes the idea of step doping (variable doping) to make the lateral and vertical electric field distribution of the 4H-SiC LDMOS more uniform, thereby increasing the breakdown voltage of the device to 1900V. At the same time, the P buried layer can help deplete the N-drift region, so that the doping concentration of the N-drift region can be higher, and the characteristic on-resistance of the device is reduced to 4.04mΩ·cm ² , thereby improving the overall electrical performance of the device.

Description of drawings

Figure 1 is a device structure diagram of a traditional dual RESURF 4H-SiC LDMOS;

2 is a device structure diagram of a 4H-SiC LDMOS provided by an embodiment of the present invention;

Fig. 3 is the electric field distribution diagram of the conventional dual RESURF 4H-SiC LDMOS;

4 is an electric field distribution diagram of a 4H-SiC LDMOS provided by an embodiment of the present invention;

Fig. 5 is the transfer characteristic curve under the 0.1V drain-source voltage of the traditional dual RESURF 4H-SiC LDMOS and the 4H-SiC LDMOS provided by the embodiment of the present invention;

Fig. 6 is the breakdown characteristic curve of the traditional double RESURF 4H-SiC LDMOS and the 4H-SiC LDMOS provided by the embodiment of the present invention;

In the figure: 1 is P+ substrate, 2 is P- epitaxial layer, 3 is P buried layer, 4 is N-drift region, 5 is Pwell region, 6 is Ptop region, 7 is P+ contact region, 8 is N+ source region , 9 is the N+ drain region, 10 is the silicon dioxide dielectric layer, 11 is the source electrode, 12 is the drain electrode, 13 is the gate electrode, 6-1 is the first Ptop region, and 6-2 is the second Ptop region.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings and embodiments.

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Various details in this specification can also be modified or changed in various ways without departing from the spirit of the present invention based on different viewpoints and applications.

Specific examples:

An embodiment of the present invention provides a 4H-SiC LDMOS power device with a withstand voltage of 1900V. Specifically, as shown in FIG. 2, the 4H-SiC LDMOS power device includes from bottom to top: P+ substrate 1, P- epitaxial layer 2, P Buried layer 3, N-drift region 4, Pwell region 5, Ptop region 6, P+ contact region 7, N+ source region 8, N+ drain region 9, silicon dioxide dielectric layer 10, source electrode 11, drain electrode 12 and gate 13; wherein the Ptop area is divided into two sub-areas, a first Ptop area 6-1 and a second Ptop area 6-2.

The upper end surface of the Ptop region is in contact with the lower end surface of the silicon dioxide dielectric layer 10 , and the upper end surface of the P buried layer 3 is in contact with the lower end surface of the N-drift region 4 .

The depth of the first Ptop region 6-1 is 0.4 μm, the length is 4.2 μm, and the doping concentration is 3×10 ¹⁷ cm ⁻³ ; the depth of the second Ptop region 6-2 is 0.4 μm, the length is 4.2 μm, and the concentration is 2×10 ¹⁷ cm ^-3 .

The depth of the P buried layer 3 is 0.4 μm, the length is 7 μm, and the doping concentration is 2×10 ¹⁷ cm ⁻³ .

The thickness of the N-drift region 4 is 4 μm, and the doping concentration is 5×10 ¹⁶ cm ⁻³ .

The thickness of the Pwell region 5 is 1 μm, and the doping concentration is 2×10 ¹⁷ cm ⁻³ .

The thickness of the P-epitaxial layer 2 is 10 μm, and the doping concentration is 5×10 ¹⁵ cm ⁻³ .

The channel length of the device, that is, the distance between the right edge of the N+ source region 8 and the right edge of the Pwell region 5 is 0.5 μm.

The gate oxide thickness of the device, ie the distance between the bottom edge of the gate 13 and the top edge of the Pwell region 5, is 50 nm.

The distance between the right edge of the Pwell region 5 and the left edge of the first Ptop region 6-1 is 1.5 μm, and the distance between the right edge of the second Ptop region 6-2 and the left edge of the N+ drain region 9 is 2.5 μm.

The working principle of the embodiment of the present invention is as follows:

As shown in FIG. 4 , in the 4H-SiC LDMOS power device provided by the embodiment of the present invention, when the device is in the blocking state, the first Ptop region 6-1 and the second Ptop region 6-2 with different doping concentrations are at the interface thereof. An additional electric field peak is introduced at the position, which can effectively adjust the lateral electric field distribution; while the P buried layer 3 on the surface of the P-epitaxial layer 2 introduces another electric field peak at its right edge, which can effectively adjust the vertical electric field distribution. Therefore, the breakdown voltage of the device can be improved. In addition, the higher doping concentration of the N-drift region reduces the forward on-resistance when the device is in the on-state, resulting in higher current capability than conventional dual RESURF 4H-SiC LDMOS.

Figure 3 is a simulation diagram of the electric field distribution during breakdown of the conventional dual RESURF 4H-SiC LDMOS. It can be seen that the electric field strength at both ends of the Ptop region 6 is very high, while the electric field strength in the middle is relatively weak, resulting in uneven lateral Electric field distribution. In addition, the electric field distribution in the longitudinal direction is also not ideal.

FIG. 4 is a simulation diagram of the electric field distribution during breakdown of the 4H-SiC LDMOS power device provided by the embodiment of the present invention. It can be seen that the electric field intensity on the left side of the first Ptop region and the right side of the second Ptop region has been effectively alleviated, and the two A new electric field spike appears at the interface of each region, which effectively modulates the electric field distribution transverse to the surface. At the same time, another new electric field peak appeared on the right edge of the P buried layer 3, which effectively adjusted the longitudinal electric field distribution. On the whole, the electric field distribution of the 4H-SiC LDMOS provided by the embodiment of the present invention is much more uniform than that of the conventional dual RESURF 4H-SiC LDMOS.

5 is a transfer characteristic curve of a 4H-SiC LDMOS (SDP LDMOS) and a conventional dual RESURF 4H-SiC LDMOS (DR LDMOS) provided by an embodiment of the present invention, where V _DS =0.1V. It can be seen that the current capability of the 4H-SiC LDMOS provided by the embodiment is obviously higher than that of the conventional dual RESURF 4H-SiC LDMOS, and the threshold voltage of the two is the same, about 6.8V. The characteristic on-resistances of the 4H-SiC LDMOS and the conventional dual RESURF 4H-SiC LDMOS provided in the examples are 4.04 mΩ·cm ² and 4.36 mΩ·cm ² , respectively.

6 is a breakdown characteristic curve of a 4H-SiC LDMOS (SDP LDMOS) and a conventional dual RESURF 4H-SiC LDMOS (DR LDMOS) provided by an embodiment of the present invention. Since the 4H-SiC LDMOS provided in the embodiment has a more uniform electric field distribution, its breakdown voltage reaches 1934V, while the breakdown voltage of the conventional dual RESURF 4H-SiC LDMOS is 1648V.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (10)

1. A transverse 4H-SiC MOSFET power device is characterized by mainly comprising a P + substrate (1), a P-epitaxial layer (2), a P buried layer (3), an N-drift region (4), a Pwell region (5), a Ptop region (6), a P + contact region (7), an N + source region (8), an N + drain region (9), a silicon dioxide dielectric layer (10), a source electrode (11), a drain electrode (12) and a grid electrode (13) from bottom to top in sequence; the source electrode (11), the drain electrode (12) and the grid electrode (13) are positioned in the silicon dioxide dielectric layer (10), the source electrode (11) and the drain electrode (12) are arranged at the lower parts of two sides of the silicon dioxide dielectric layer (10) in parallel, and the grid electrode (13) is arranged close to the source electrode (11) and is formed at the upper part of the silicon dioxide dielectric layer (10);

the Pwell region (5), the Ptop region (6) and the N + drain region (9) are located in the N-drift region (4), the Pwell region (5) and the N + drain region (9) are respectively formed on two sides of the upper portion of the N-drift region (4), the P + contact region (7) and the N + source region (8) are located in the Pwell region (5), the P + contact region (7) is formed on the upper portion of one side of the Pwell region (5), and the N + source region (8) is arranged close to the P + contact region (7); the Ptop area (6) is formed in the middle of the upper part of the N-drift area (4), and the Ptop area (6) is divided into a first Ptop area (6-1) and a second Ptop area (6-2) which are divided into a left sub-area and a right sub-area;

the P buried layer (3) is positioned in the P-epitaxial layer (2), and the P buried layer (3) is formed on the upper portion of one side of the P-epitaxial layer (2).

2. The lateral 4H-SiC MOSFET power device of claim 1, wherein the first Ptop region (6-1) has a depth of 0.4um, a length of 4.2um, and a doping concentration of 3 x 10¹⁷cm^-3(ii) a The second Ptop region (6-2) has a depth of 0.4um, a length of 4.2um, and a doping concentration of 2 × 10¹⁷cm^-3。

3. A lateral 4H-SiC MOSFET power device according to claim 1, characterized in that the distance between the Pwell region (5) and the first Ptop region (6-1) is 1.5 μm and the distance between the second Ptop region (6-2) and the N + drain region (9) is 2.5 μm.

4. A lateral 4H-SiC MOSFET power device according to claim 1, characterized in that the buried P layer (3), Pwell region (5) and source (11) are located on the same side.

5. A lateral 4H-SiC MOSFET power device according to claim 1, characterized in that the buried P layer (3) has a depth of 0.4 μm, a length of 7 μm and a doping concentration of 2 x 10¹⁷cm^-3。

6. A lateral 4H-SiC MOSFET power device according to claim 1, characterized in that the N-drift region (4) has a thickness of 4 μm and a doping concentration of 5 x 10¹⁶cm^-3。

7. A lateral 4H-SiC MOSFET power device according to claim 1, characterized in that the Pwell region (5) has a thickness of 1 μm and a doping concentration of 2 x 10¹⁷cm^-3。

8. A lateral 4H-SiC MOSFET power device according to claim 1, characterized in that the P-epitaxial layer (2) has a thickness of 10 μm and a doping concentration of 5 x 10¹⁵cm^-3。

9. The lateral 4H-SiC MOSFET power device of claim 1, wherein the channel length of the power device is 0.5 μm and the gate oxide thickness of the power device is 50 nm.

10. A lateral 4H-SiC MOSFET power device according to claim 9, characterized in that the channel length is the distance between the side of the N + source region (8) close to the Ptop region (6) and the side of the Pwell region (5) close to the Ptop region (6); the gate oxide thickness is the distance between the bottom edge of the gate (13) and the top edge of the Pwell region (5).

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