CN112071351A

CN112071351A - Flash memory programming operation method and operation circuit

Info

Publication number: CN112071351A
Application number: CN202010892461.XA
Authority: CN
Inventors: 黄明永
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2020-12-11
Anticipated expiration: 2040-08-31
Also published as: CN112071351B

Abstract

The application relates to the field of memories, in particular to a flash memory programming operation method and an operation circuit. Wherein. The method comprises the following steps: providing a pulse train signal to a bit line of a memory cell, the pulse train signal comprising: a high level period and a low level period which alternate in time domain; under the control of the programming permission signal, enabling the memory cell to perform programming operation according to programming input data during a high level period of the pulse sequence signal; during a low level period of the pulse sequence signal, making the memory cell perform a read detection operation; the read detection operation includes: reading data stored in the memory cell, and comparing whether the data read during a low level period is identical to the program input data; if the two are consistent, stopping programming operation; otherwise, the memory cell is caused to perform the program operation again according to the program input data during the next high level period, and to perform the read sensing operation during the subsequent low level period. Wherein the circuit is used for executing the method.

Description

Flash memory programming operation method and operation circuit

Technical Field

The application relates to the field of memories, in particular to a flash memory programming operation method and an operation circuit.

Background

A Flash memory (Flash), which is a non-volatile memory, can perform an Erase operation (Erase) and a Program operation (Program) on a block (sector), wherein when the Erase operation is performed on the block, all bits (bit) of the block are erased to a "1" state, when the Program operation is performed on the block, some bits (bit) of the block are changed from the "1" state to a "0" state, and before the Program operation is performed, the Erase operation is required, and all bits (bit) are erased to a "1" state.

In many cases, such as when flash memory is used in a financial card, the total time of an erase operation and a program operation performed on a block is required to be less than 1ms, and for this reason, a means for reducing the time of the program operation is generally adopted to reduce the total time of the erase operation and the program operation.

However, the related art generally reduces the total time of the erase operation and the program operation by increasing the number of bits of the one-time program operation, but this approach increases the power consumption of the flash memory during the program operation.

Disclosure of Invention

The application provides a flash memory programming operation method and an operation circuit, which can solve the problem of larger programming power consumption when the total time of erasing operation and programming operation is reduced in the related art.

As a first aspect of the present application, there is provided a flash memory program operation method including:

providing a pulse train signal to a bit line of a memory cell, the pulse train signal comprising: a high level period and a low level period which alternate in time domain;

under the control of a program permission signal, enabling the memory cell to perform a programming operation according to programming input data during a high level period of the pulse sequence signal;

during a low level period of the pulse sequence signal, enabling the memory cell to perform a read detection operation; the read detection operation includes: reading out data stored in the memory cell, comparing whether the data read out during the low level is identical to the program input data;

if the two are consistent, stopping programming operation; otherwise, the memory cell is caused to perform the programming operation again according to the programming input data during the next high level period, and to perform the read sensing operation during the subsequent low level period until the read data is the same as the programming input data, and the programming operation is stopped.

Optionally, the method further includes:

if the memory cell is not correctly read after sequentially passing through the high level period of the specific segment of the pulse sequence signal, the programming operation is stopped, and the programming input data is replaced.

The method of claim 1, wherein the pulse train signal is reset to a low level during a time period when the generation of the program permission signal is started.

Optionally, the charge pump module is used for generating a high-voltage signal capable of enabling the memory cell to perform a programming operation; the pulse control module is connected between the output end of the charge pump module and the bit line of the storage unit, and is used for periodically switching off the pulse control signal and converting the high-voltage signal into the pulse sequence signal.

Optionally, the duty cycle of the high-voltage signal is smaller than the duty cycle of the pulse control signal, and the duty cycle of the pulse control signal is equal to the duty cycle of the pulse sequence signal.

As a second aspect of the present application, there is provided a flash memory program operation circuit including:

the storage unit is provided with a lead-out bit line;

the output end of the pulse sequence generating unit is connected with the bit line and is used for generating a pulse sequence signal to the bit line;

and the programming signal generating circuit is connected with the pulse sequence generating unit and is used for enabling the memory unit to carry out programming operation according to programming input data in a high level period of the pulse sequence signal and carry out read detection operation in a low level period of the pulse sequence signal under the control of a programming permission signal.

Optionally, the pulse sequence generating unit includes a charge pump module and a pulse control module;

the charge pump module is used for generating a high-voltage signal which can enable the memory cell to carry out programming operation;

the pulse control module is connected between the charge pump module and the bit line and used for converting the high-voltage signal into the pulse sequence signal according to a pulse control signal.

Optionally, the program signal generating circuit is further configured to reset the pulse train signal to a low level at the start of generating the program permission signal.

The technical scheme at least comprises the following advantages: the flash memory programming operation method and the flash memory programming operation circuit provided by the embodiment of the application can ensure the reliability of programming operation and reduce the time occupied by the programming operation.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a timing diagram of a high level signal applied to a bit line of a memory cell for a predetermined time Tprog in the related art;

FIG. 2 is a schematic diagram of a flash memory programming circuit according to an embodiment of the present application;

fig. 3 is a waveform diagram of a PULSE train signal PULSE referred to in the present application;

FIG. 4 is a timing diagram of the program permission signal PROG, the PULSE control signal PROG _ INTERNAL, the high voltage signal SW provided by the charge pump module, and the PULSE sequence signal PULSE referred to in this application;

fig. 5 is a flowchart of a flash memory programming method according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

In the related art, it is general to perform a uniform program operation on the respective bits of the memory cell, that is, apply a high level signal for a predetermined time Tprog to the bit line of the memory cell, and the high level signal refers to fig. 1, so that the respective bits in the memory cell perform a program operation according to a binary value on the respective bits of the program input data. In principle, after a programming operation, the amount of electrons in the floating gate of the corresponding bit of the memory cell is changed to a target value, so that the binary number stored in each bit of the memory cell corresponds to each bit binary value of the programming input data. However, in the memory cells, due to the difference in performance among the bits, when the memory cells are subjected to the uniform programming operation, there may be a case where the time required for the floating gate charge amount of each bit to reach the target value is different, that is, the charge amount in some bits can reach the target value faster, and the charge amount in some bits can reach the target value slower. The bits that reach the target value more quickly are the bits that are easier to program, and the bits that reach the target value more slowly are the bits that are harder to program. Therefore, in order to ensure the reliability of the programming operation, the predetermined time Tprog for the high level signal of the programming operation is generally set to be long, generally 6us to 7.5us, but the time taken to perform the programming operation on the memory cell is long, which may pull down the read data rate of the memory, so that the performance of the memory is deteriorated.

In order to ensure the reliability of the programming operation while reducing the time taken by the programming operation, the present application provides a flash memory programming circuit and a flash memory programming method.

Fig. 2 shows a flash memory programming circuit provided in an embodiment of the present application, the flash memory programming circuit including:

a memory cell 100, wherein a bit line BL is drawn from the memory cell 100, and a PULSE train signal PULSE is applied to the bit line BL, so that the memory cell 100 performs a programming operation during a high level period of the PULSE train signal PULSE and performs a read detection operation during a low level period of the PULSE train signal PULSE.

A PULSE sequence generating unit 200, an output terminal of the PULSE sequence generating unit 200 being connected to the bit line BL of the memory cell 100 for generating the PULSE sequence signal PULSE applied to the bit line BL.

Fig. 3 shows a waveform diagram of the PULSE train signal PULSE, which is a rectangular PULSE signal having alternating high and low levels, including a high level period H and a low level period L in the time domain, and has a voltage amplitude a with reference to fig. 3. In the high level period H of the waveform of the PULSE train signal PULSE, the PULSE train generating unit 200 applies a high level to the bit line BL, and the memory cell 100 performs a program operation. In the low level period L of the waveform of the PULSE train signal PULSE, the PULSE train generating unit 200 applies a low level to the bit line BL, and the memory cell 100 performs a read sensing operation.

With continued reference to fig. 2, the flash memory programming circuit further includes a programming signal generating circuit 300, wherein the programming signal generating circuit 300 is connected to the PULSE sequence generating unit 200, and is configured to enable the memory cell 100 to perform a programming operation according to the programming input data Din during a high level period H of the PULSE sequence signal PULSE under the control of the programming permission signal PROG.

In this embodiment, the memory cell 100 can perform a programming operation according to the programming input data Din during a high level period H of the PULSE train signal PULSE, and the duration of the high level period of the PULSE train signal PULSE is usually short, about 1 us; after a short programming operation, the memory cell 100 immediately performs a read detection operation, i.e. reads the data stored in the memory cell 100 during a low level period L of the PULSE sequence signal PULSE, compares the read data with the programming input data Din, if the data are the same, stops the programming operation, and if the data are different, the memory cell performs the programming operation again according to the programming input data Din along with a next high level period H of the PULSE sequence signal PULSE, and performs the read detection operation during a subsequent low level period L until the read data are the same as the programming input data Din. For example, if the memory cell 100 is not correctly read even after sequentially undergoing the 10 high periods H and the 10 low periods L of the PULSE train signal PULSE, the programming operation is stopped and the programming input data Din is replaced.

With continued reference to fig. 1, the pulse sequence generation unit 200 includes a charge pump module 210 and a pulse control module 220.

The charge pump module 210 is used for generating a high voltage signal SW for enabling the memory cell 100 to perform a programming operation, and the programming signal generating circuit 300 is connected to an output terminal of the charge pump module 210.

For one embodiment, the charge pump module 210 includes a charge pump 211 and a comparator 212, a reference terminal Vref of the comparator 212 is connected to a power supply, a feedback terminal FD of the comparator 212 is connected to an output terminal OUT of the charge pump 211, and the output terminal OUT of the charge pump 211 is an output terminal of the charge pump module 210; the output terminal of the comparator 212 is connected to the enable terminal EN of the charge pump 211, and the clock terminal CLK of the charge pump 211 is connected to a clock signal.

The PULSE control module 220 is connected between the charge pump module 210 and the bit line BL of the memory cell 100, and configured to periodically turn off according to a PULSE control signal PROG _ INTERNAL, and convert a high-voltage signal generated by the charge pump module 210 and used for enabling the memory cell to perform a programming operation into the PULSE sequence signal PULSE, where a high-level voltage amplitude of the PULSE sequence signal PULSE is equal to a high voltage generated by the charge pump module 210. Illustratively, the high voltage signal SW generated by the charge pump module 210 is a rectangular wave having a duty cycle smaller than that of the PULSE control signal PROG _ interval, and the duty cycle of the PULSE control signal PROG _ interval is equal to that of the PULSE sequence signal PULSE.

For one embodiment, the pulse control module 220 includes a first MOS switch transistor N1, a source of the first MOS switch transistor N1 is connected to the output terminal of the charge pump 211, a drain of the first MOS switch transistor is connected to the bit line of the memory cell 100, and a gate of the first MOS switch transistor is connected to a pulse control signal PROG _ interval, which may be generated by a timer. The pulse control signal PROG _ interval is a rectangular wave with alternating high and low levels. When the PULSE control signal PROG _ interval is at a high level, the PULSE control module 220 is turned on, the high-voltage signal generated by the charge pump module 210 can be transmitted to the bit line BL of the memory cell, and when the PULSE control signal PROG _ interval is at a low level, the PULSE control module 220 is turned off, the voltage input to the bit line BL of the memory cell 100 is at a low level, so as to generate the PULSE sequence signal PULSE with the high-level period and the low-level period sequentially alternating in time domain.

Referring to fig. 1, the program signal generating circuit 300 includes: a D flip-flop 310 and a constant current source module 320.

The constant current source module 320 includes a second MOS switch tube N2 and a constant current source I1, a gate of the second MOS switch tube N2 is connected to the output end of the D flip-flop 310 through a phase inverter, a source of the second MOS switch tube N2 is connected to the constant current source I1, and a drain of the second MOS switch tube N2 is connected to the output end of the charge pump module 210.

The D flip-flop 310 includes a reset terminal RST, an input terminal D, and an output terminal Q; the reset terminal RST of the D flip-flop 310 is connected to the programming enable signal PROG through an inverter, and the output terminal Q of the D flip-flop 310 is connected to the gate of the second MOS switch transistor N2 through an inverter, and the input terminal D of the D flip-flop is used for inputting the programming input data Din.

Fig. 4 shows timing diagrams of the program permission signal PROG, the PULSE control signal PROG _ INTERNAL, the high voltage signal SW supplied from the charge pump module, and the PULSE sequence signal PULSE.

It can be seen from fig. 4 that the duty cycle of the high voltage signal SW is smaller than the duty cycle of the PULSE control signal PROG _ interval, which is equal to the duty cycle of the PULSE sequence signal PULSE.

Referring to fig. 4, the high level and the low level of the supplied pulse control signal PROG _ interval are periodically alternated. The program enable signal PROG starts to be generated at time t0, i.e., the program enable signal PROG is a rising edge at time t0, the program enable signal PROG is stopped at time tn, i.e., the program enable signal PROG is a falling edge at time tn, and the memory cell has performed at least one programming operation and at least one read sensing operation during the time t 0-tn. For example, in the time period t11-t12, the program permission signal PROG is high, and the memory cell sequentially performs a set of a program operation and a read sensing operation.

At time t0, the program enable signal PROG starts to be generated, i.e. the program enable signal PROG is at the rising edge, and since the program signal generating circuit 300 is connected to the output terminal of the charge pump module 210, at the instant when the second MOS switch N2 of the program signal generating circuit 300 is turned on, due to the constant current source I1, a pull-down current is generated so that the potential of the output terminal of the charge pump module 210 is lowered to the low level, i.e. the PULSE sequence signal PULSE and the high voltage signal SW provided by the charge pump module are reset to the low level. With the arrival of the next high level, i.e., in the time period t11-t1, the PULSE control signal PROG _ INTERNAL is at the high level, so that the high level of the high voltage signal SW generated by the charge pump module can be transmitted to the bit line BL, thereby forming the high level period H of the PULSE sequence signal PULSE.

In the time period t1-t12, the PULSE control signal PROG _ interval is at low level, so that the charge pump module and the bit line BL can be disconnected, thereby forming a low level period L of the PULSE sequence signal PULSE.

The time lengths of the t0-tn are varied, that is, when the memory cell has a bit which is hard to be programmed, the time lengths of the t0-tn are longer, that is, the times of the programming operation and the read detection operation are more; if the bits in the memory cells are bits that are easier to program, the time length of t0-tn required by the memory cells is shorter, so that the flash memory programming operation method and the flash memory programming operation circuit provided by the embodiments of the present application can reduce the time taken by the programming operation while ensuring the reliability of the programming operation.

On the basis of any one of fig. 1 to 4, referring to fig. 5, fig. 5 shows a flowchart of a flash memory programming method provided by an embodiment of the present application, where the flash memory programming operation method includes the following steps:

step S1: providing a pulse train signal to a bit line of a memory cell, the pulse train signal comprising: the high level period and the low level period alternate in time domain.

Step S2: under the control of the program permission signal, the memory cell is caused to perform a program operation according to program input data during a high level of the pulse sequence signal.

Step S3: during a low level period of the pulse sequence signal, enabling the memory cell to perform a read detection operation; the read detection operation includes: reading out data stored in the memory cell, and comparing whether the data read out during the low level is identical to the programming input data.

Step S4: if so, stopping the programming operation.

Step S5: otherwise, the memory cell is caused to perform the programming operation again according to the programming input data during the next high level period, and to perform the read sensing operation during the subsequent low level period until the read data is the same as the programming input data, and the programming operation is stopped.

The pulse train signal is reset to a low level period at the start of generation of the program permission signal.

As an example, with continued reference to fig. 2, the memory cell can perform a programming operation according to the programming input data Din during a high level period H of the PULSE train signal PULSE, and the high level period of the PULSE train signal PULSE is generally short in duration, about 1 us; after a short programming operation, the memory cell 100 immediately performs a read detection operation, i.e. reads the data stored in the memory cell 100 during a low level period L of the PULSE sequence signal PULSE, compares the read data with the programming input data Din, if the data are the same, stops the programming operation, and if the data are different, the memory cell performs the programming operation again according to the programming input data Din along with a next high level period H of the PULSE sequence signal PULSE, and performs the read detection operation during a subsequent low level period L until the read data are the same as the programming input data Din. For example, if the memory cell 100 is not correctly read even after sequentially undergoing the 10 high periods H and the 10 low periods L of the PULSE train signal PULSE, the programming operation is stopped and the programming input data Din is replaced.

The total time length of the total programming operation time and the total time length of the reading detection operation time for different memory cells are changed, namely when a bit which is difficult to perform the programming operation exists in the memory cell, the total time length is longer, namely the times of performing the programming operation and the reading detection operation are more; if the bits in the memory cells are bits that are easier to program, the total time required for the bits is shorter, so that the flash memory programming operation method and the flash memory programming operation circuit provided by the embodiment of the application can ensure the reliability of the programming operation and reduce the time taken by the programming operation.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims

1. A flash memory programming operation method, comprising:

2. The flash memory program operation method of claim 1, further comprising:

3. The method of claim 1, wherein the pulse train signal is reset to a low level during a time period when the generation of the program permission signal is started.

4. The flash memory program operation method of claim 1, wherein a charge pump module is used to generate a high voltage signal capable of causing the memory cell to perform a program operation; the pulse control module is connected between the output end of the charge pump module and the bit line of the storage unit, and is used for periodically switching off the pulse control signal and converting the high-voltage signal into the pulse sequence signal.

5. The flash memory program operation method of claim 1, wherein a duty ratio of the high voltage signal is smaller than a duty ratio of the pulse control signal, the duty ratio of the pulse control signal being equal to a duty ratio of the pulse train signal.

6. A flash memory program operation circuit, the flash memory program operation circuit comprising:

the storage unit is provided with a lead-out bit line;

7. The flash program operation circuit of claim 6, wherein the pulse sequence generating unit comprises a charge pump module and a pulse control module;

8. The flash program operation circuit of claim 6, wherein the program signal generation circuit is further configured to reset the pulse train signal to a low level during a time when generation of the program permission signal is started.