[go: up one dir, main page]

CN112071255A - a display panel - Google Patents

a display panel Download PDF

Info

Publication number
CN112071255A
CN112071255A CN202011000133.0A CN202011000133A CN112071255A CN 112071255 A CN112071255 A CN 112071255A CN 202011000133 A CN202011000133 A CN 202011000133A CN 112071255 A CN112071255 A CN 112071255A
Authority
CN
China
Prior art keywords
trace
wire
display area
wiring
traces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011000133.0A
Other languages
Chinese (zh)
Inventor
徐尚君
王鸣昕
黄洪涛
高威
王志军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing CEC Panda LCD Technology Co Ltd
Original Assignee
Nanjing CEC Panda LCD Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing CEC Panda LCD Technology Co Ltd filed Critical Nanjing CEC Panda LCD Technology Co Ltd
Priority to CN202011000133.0A priority Critical patent/CN112071255A/en
Publication of CN112071255A publication Critical patent/CN112071255A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明涉及一种显示面板,包括显示区的多组走线,其特征在于,每组所述走线包括第一走线、第二走线和第三走线,所述第一走线具有与所述第二走线和第三走线不同的信号类型,所述第二走线和第三走线与所述第一走线相邻设置,所述第二走线的长度和所述第二走线与所述第一走线之间距离的比值等于所述第三走线的长度和所述第三走线与所述第一走线之间距离的比值,所述第二走线和第三走线具有频率相同、高低电平相同以及相位差为180°的不同信号。本发明工艺简单,成本较低,能够很好的消除相邻走线之间侧向电容引起的耦合效应。

Figure 202011000133

The present invention relates to a display panel, comprising multiple groups of wirings in a display area, wherein each group of the wirings includes a first wiring, a second wiring and a third wiring, and the first wiring has Different signal types from the second and third traces, which are arranged adjacent to the first trace, the length of the second trace and the The ratio of the distance between the second trace and the first trace is equal to the ratio of the length of the third trace to the distance between the third trace and the first trace, and the second trace The line and the third trace have different signals with the same frequency, the same high and low levels, and a phase difference of 180°. The invention has simple process and low cost, and can well eliminate the coupling effect caused by the lateral capacitance between adjacent wirings.

Figure 202011000133

Description

一种显示面板a display panel

技术领域technical field

本发明涉及显示领域,尤其涉及一种显示面板。The present invention relates to the field of display, in particular to a display panel.

背景技术Background technique

随着显示面板集成度的提高,无可避免地出现两条不同信号走线并排紧密布线的设计。当这两条走线距离较近且长度很长(通常为整个面板长度)时,两者之间的侧向电容无法忽视(

Figure BDA0002693995960000011
其中,C为侧向电容,A为介电常数相关的常数,S为两条走线相对应的走线面积,d为两条走线之间的距离)。侧向电容的存在导致两条线的信号相互耦合,最终影响显示。As the integration of display panels increases, it is inevitable that two different signal traces are closely routed side by side. When the two traces are close together and have a long length (usually the entire panel length), the lateral capacitance between the two cannot be ignored (
Figure BDA0002693995960000011
Among them, C is the lateral capacitance, A is the constant related to the dielectric constant, S is the trace area corresponding to the two traces, and d is the distance between the two traces). The presence of lateral capacitance causes the signals of the two lines to couple to each other, which ultimately affects the display.

比如,文献CN110579920A公开了一种显示面板,包括纵横交错的栅极线和数据线、由栅极线和数据线交叉限定的子像素单元、位于栅极线和数据线交叉处的第一TFT开关、与数据线平行设置的信号线等,其实现了显示面板更窄的边框和更加灵活多变的显示区形状。然而,由于上述方案中信号线(时钟信号线CKn,n为≥1的整数)设置在显示区,并且与数据线平行设置,两者走线距离较近,且长度为整个面板长度,导致两者之间产生侧向电容,引发相互耦合效应,最终出现在红画面下宏观下竖条纹及微观下像素现象亮暗不均等显示问题。For example, the document CN110579920A discloses a display panel, including gate lines and data lines that are crisscrossed, sub-pixel units defined by the intersection of the gate lines and the data lines, and a first TFT switch located at the intersection of the gate lines and the data lines , a signal line arranged in parallel with the data line, etc., which realizes a narrower frame of the display panel and a more flexible display area shape. However, since the signal line (the clock signal line CKn, n is an integer ≥ 1) in the above solution is arranged in the display area and is arranged in parallel with the data line, the two lines are relatively close in distance and the length is the entire panel length, resulting in two Lateral capacitance is generated between them, which causes mutual coupling effect, and finally appears in the display problems such as vertical stripes under the macroscopic picture and uneven brightness and darkness of the pixels under the microscopic picture.

发明内容SUMMARY OF THE INVENTION

本发明提出一种显示面板,能够克服相邻信号走线之间侧向电容和耦合的影响。The present invention provides a display panel capable of overcoming the effects of lateral capacitance and coupling between adjacent signal lines.

具体地,本发明提出一种显示面板,包括显示区的多组走线,每组所述走线包括第一走线、第二走线和第三走线,所述第一走线具有与所述第二走线和第三走线不同的信号类型,所述第二走线和第三走线与所述第一走线相邻设置,所述第二走线的长度和所述第二走线与所述第一走线之间距离的比值等于所述第三走线的长度和所述第三走线与所述第一走线之间距离的比值,所述第二走线和第三走线具有频率相同、高低电平相同以及相位差为180°的不同信号。Specifically, the present invention provides a display panel, which includes multiple groups of wirings in a display area, each group of the wirings includes a first wiring, a second wiring and a third wiring, and the first wiring has a The second trace and the third trace have different signal types, the second trace and the third trace are arranged adjacent to the first trace, and the length of the second trace is the same as the length of the first trace. The ratio of the distance between the second trace and the first trace is equal to the ratio of the length of the third trace to the distance between the third trace and the first trace, and the second trace and the third trace have different signals with the same frequency, the same high and low levels, and a phase difference of 180°.

优选的,所述第二走线和第三走线与所述第一走线的距离相等,所述第二走线和第三走线的长度相等。Preferably, the distances between the second wiring and the third wiring are equal to the first wiring, and the lengths of the second wiring and the third wiring are the same.

优选的,所述第二走线和第三走线分别位于所述第一走线的同一侧。Preferably, the second wiring and the third wiring are respectively located on the same side of the first wiring.

优选的,所述第二走线和第三走线分别位于所述第一走线的两侧。Preferably, the second wiring and the third wiring are located on two sides of the first wiring, respectively.

优选的,所述显示区分为第一显示区和第二显示区,所述第二走线贯穿第一显示区,所述第三走线贯穿第二显示区。Preferably, the display area is divided into a first display area and a second display area, the second wiring runs through the first display area, and the third wiring runs through the second display area.

优选的,所述第二走线和第三走线均贯穿整个显示区。Preferably, both the second wiring and the third wiring run through the entire display area.

优选的,所述第二走线和第三走线分别与所述第一走线平行。Preferably, the second wiring and the third wiring are respectively parallel to the first wiring.

优选的,所述第一走线为数据线,所述第二走线和第三走线为信号线。Preferably, the first wire is a data wire, and the second wire and the third wire are signal wires.

优选的,所述第二走线和第三走线为时钟信号线。Preferably, the second wiring and the third wiring are clock signal lines.

有益效果:Beneficial effects:

本发明将相互靠近的两根走线中的其中一根设置为两根具有频率相同、高低电平相同、相位差180°的信号的不同走线,由于设置了180°的相位差,这两根不同走线分别对另一根走线的耦合效应相互抵消,消除了原本相互靠近的两根走线之间由于侧向电容引起的耦合效应,从而改善了画质。本发明工艺简单,成本较低,能够很好的消除相邻走线之间的耦合效应。In the present invention, one of the two wirings that are close to each other is set as two different wirings with signals with the same frequency, the same high and low levels, and a phase difference of 180°. The coupling effects of different traces to another trace cancel each other out, eliminating the coupling effect caused by side capacitance between the two traces originally close to each other, thereby improving the image quality. The invention has simple process and low cost, and can well eliminate the coupling effect between adjacent wirings.

附图说明Description of drawings

图1为本发明实施例一的示意图;1 is a schematic diagram of Embodiment 1 of the present invention;

图2为本发明实施例二的示意图;2 is a schematic diagram of Embodiment 2 of the present invention;

图3为本发明实施例三的示意图。FIG. 3 is a schematic diagram of Embodiment 3 of the present invention.

附图标记:Reference number:

AA显示区;1第一走线;2第二走线;3第三走线。AA display area; 1 the first line; 2 the second line; 3 the third line.

具体实施方式Detailed ways

为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对照附图说明本发明的具体实施方式。显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图,并获得其他的实施方式。In order to more clearly describe the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative efforts, and obtain other implementations.

为使图面简洁,各图中只示意性地表示出了与本发明相关的部分,它们并不代表其作为产品的实际结构。另外,以使图面简洁便于理解,在有些图中具有相同结构或功能的部件,仅示意性地绘示了其中的一个,或仅标出了其中的一个。在本文中,“一个”不仅表示“仅此一个”,也可以表示“多于一个”的情形。In order to keep the drawings concise, the drawings only schematically show the parts related to the present invention, and they do not represent its actual structure as a product. In addition, in order to make the drawings concise and easy to understand, in some drawings, only one of the components having the same structure or function is schematically shown, or only one of them is marked. As used herein, "one" not only means "only one", but also "more than one".

图1-图3示出了本发明具体实施例的示意图:一种显示面板,包括显示区AA的多组走线,每组所述走线包括第一走线1、第二走线2和第三走线3,所述第一走线1具有与所述第二走线2和第三走线3不同的信号类型,所述第二走线2和第三走线3与所述第一走线1相邻设置,所述第二走线2的长度和所述第二走线2与所述第一走线1之间距离的比值等于所述第三走线3的长度和所述第三走线3与所述第一走线1之间距离的比值。1-3 show schematic diagrams of specific embodiments of the present invention: a display panel, comprising multiple groups of wirings in the display area AA, each group of the wirings includes a first wiring 1, a second wiring 2 and The third trace 3, the first trace 1 has a different signal type from the second trace 2 and the third trace 3, the second trace 2 and the third trace 3 are the same as the second trace 2 and the third trace 3. A trace 1 is arranged adjacently, and the ratio of the length of the second trace 2 to the distance between the second trace 2 and the first trace 1 is equal to the length of the third trace 3 and the The ratio of the distance between the third trace 3 and the first trace 1.

所述第二走线2和第三走线3具有频率相同、高低电平相同以及相位差为180°的不同信号。The second trace 2 and the third trace 3 have different signals with the same frequency, the same high and low levels, and a phase difference of 180°.

根据侧向电容的计算公式

Figure BDA0002693995960000031
其中,C为侧向电容,A为介电常数相关的常数,d为两条走线之间的距离,S为两条走线相对应的走线面积,S=LW,其中,L为两条走线对应处的长度,W为两条走线对应处的走线厚度,具体的,本发明中,所述第二走线2和所述第一走线1之间的第一侧向电容为C1,所述第二走线2的长度为L1,所述第二走线2的厚度为W1,所述第二走线2与所述第一走线1之间的距离为d1,所述第三走线3和所述第一走线1之间的第二侧向电容为C2,所述第三走线3的长度为L2,所述第三走线3的厚度为W3,所述第三走线3与所述第一走线1之间的距离为d2,由于走线厚度相当,即W1和W2近似相等,因此,当L1/d1=L2/d2时,C1≈C2,由于所述第二走线2和第三走线3的信号之间相位差为180°,这两个不同信号将所述第一侧向电容C1和第二侧向电容C2产生的耦合效应相互抵消,最终实现正常的显示。According to the calculation formula of lateral capacitance
Figure BDA0002693995960000031
Among them, C is the lateral capacitance, A is the constant related to the dielectric constant, d is the distance between the two traces, S is the trace area corresponding to the two traces, S=LW, where L is the two traces is the length of the corresponding part of the two traces, and W is the trace thickness of the corresponding part of the two traces. Specifically, in the present invention, the first lateral direction between the second trace 2 and the first trace 1 The capacitance is C1, the length of the second trace 2 is L1, the thickness of the second trace 2 is W1, the distance between the second trace 2 and the first trace 1 is d1, The second lateral capacitance between the third trace 3 and the first trace 1 is C2, the length of the third trace 3 is L2, the thickness of the third trace 3 is W3, The distance between the third trace 3 and the first trace 1 is d2. Since the thickness of the traces is the same, that is, W1 and W2 are approximately equal, therefore, when L1/d1=L2/d2, C1≈C2 , since the phase difference between the signals of the second trace 2 and the third trace 3 is 180°, the two different signals will cause the coupling effect generated by the first lateral capacitor C1 and the second lateral capacitor C2 They cancel each other out and finally achieve a normal display.

优选的,所述第二走线2和第三走线3与所述第一走线1的距离相等。所述第二走线2和第三走线3的长度相等。Preferably, the distances between the second wiring 2 and the third wiring 3 and the first wiring 1 are equal. The lengths of the second wiring 2 and the third wiring 3 are equal.

所述第一走线1可以是数据线,相应的,所述第二走线2和第三走线3为信号线。The first wire 1 may be a data wire, and correspondingly, the second wire 2 and the third wire 3 are signal wires.

更进一步的,所述第二走线2和第三走线3可以为时钟信号线。Further, the second wire 2 and the third wire 3 may be clock signal wires.

更进一步的,所述第二走线2从侧面非显示区进行走线,从而连接到驱动IC中,所述第三走线3直接连接到驱动IC中。Further, the second wiring 2 is routed from the side non-display area, so as to be connected to the driver IC, and the third wiring 3 is directly connected to the driver IC.

图1具体示出了本发明的第一个实施例,其中,所述显示区AA包括第一显示区和第二显示区,所述第二走线2和第三走线3分别位于所述第一走线1的同一侧,所述第二走线2贯穿所述第一显示区,所述第三走线3贯穿所述第二显示区。FIG. 1 specifically shows the first embodiment of the present invention, wherein the display area AA includes a first display area and a second display area, and the second wiring 2 and the third wiring 3 are located in the On the same side of the first trace 1, the second trace 2 runs through the first display area, and the third trace 3 runs through the second display area.

图2具体示出了本发明的第二个实施例,其中,所述显示区AA包括第一显示区和第二显示区,所述第二走线2和第三走线3分别位于所述第一走线1的两侧,所述第二走线2贯穿所述第一显示区,所述第三走线3贯穿所述第二显示区。FIG. 2 specifically shows the second embodiment of the present invention, wherein the display area AA includes a first display area and a second display area, and the second wiring 2 and the third wiring 3 are located in the On both sides of the first trace 1, the second trace 2 runs through the first display area, and the third trace 3 runs through the second display area.

图3具体示出了本发明的第三个实施例,其中,所述第二走线2和第三走线3分别位于所述第一走线1的两侧,所述第二走线2和第三走线3均贯穿整个显示区AA。FIG. 3 specifically shows the third embodiment of the present invention, wherein the second wiring 2 and the third wiring 3 are located on both sides of the first wiring 1 respectively, and the second wiring 2 and the third wiring 3 run through the entire display area AA.

本发明将相互靠近的两根走线中的其中一根设置为两根具有频率相同、高低电平相同、相位差180°的信号的不同走线(所述第二走线和第三走线),由于设置了180°的相位差,这两根不同走线分别对另一根走线(所述第一走线)的耦合效应相互抵消,消除了原本相互靠近的两根走线之间由于侧向电容引起的耦合效应,从而改善了画质。本发明工艺简单,成本较低,能够很好的消除相邻走线之间的耦合效应。In the present invention, one of the two wirings that are close to each other is set as two different wirings (the second wiring and the third wiring) having signals with the same frequency, the same high and low levels, and a phase difference of 180°. ), due to the 180° phase difference, the coupling effects of the two different traces on the other trace (the first trace) cancel each other out, eliminating the gap between the two traces that were originally close to each other. The picture quality is improved due to the coupling effect caused by the lateral capacitance. The invention has simple process and low cost, and can well eliminate the coupling effect between adjacent wirings.

应当说明的是,上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。It should be noted that the above embodiments can be freely combined as required. The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.

Claims (10)

1. A display panel comprises a plurality of groups of wires in a display area, and is characterized in that each group of wires comprises a first wire, a second wire and a third wire, the first wire has a signal type different from that of the second wire and the third wire, the second wire and the third wire are arranged adjacent to the first wire, the ratio of the length of the second wire to the distance between the second wire and the first wire is equal to the ratio of the length of the third wire to the distance between the third wire and the first wire, and the second wire and the third wire have different signals with the same frequency, the same high and low levels and the phase difference of 180 degrees.
2. The display panel according to claim 1, wherein the second and third traces are equidistant from the first trace, and the second and third traces are equal in length.
3. The display panel according to claim 1 or 2, wherein the second trace and the third trace are respectively located on the same side of the first trace.
4. The display panel according to claim 3, wherein the display area is divided into a first display area and a second display area, the second wire penetrates through the first display area, and the third wire penetrates through the second display area.
5. The display panel according to claim 1 or 2, wherein the second trace and the third trace are respectively located at two sides of the first trace.
6. The display panel according to claim 5, wherein the display area is divided into a first display area and a second display area, the second wire penetrates through the first display area, and the third wire penetrates through the second display area.
7. The display panel according to claim 5, wherein the second traces and the third traces both extend through the entire display area.
8. The display panel according to claim 1, wherein the second and third traces are parallel to the first trace, respectively.
9. The display panel according to claim 1, wherein the first traces are data lines, and the second traces and the third traces are signal lines.
10. The display panel according to claim 9, wherein the second traces and the third traces are clock signal lines.
CN202011000133.0A 2020-09-22 2020-09-22 a display panel Pending CN112071255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011000133.0A CN112071255A (en) 2020-09-22 2020-09-22 a display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011000133.0A CN112071255A (en) 2020-09-22 2020-09-22 a display panel

Publications (1)

Publication Number Publication Date
CN112071255A true CN112071255A (en) 2020-12-11

Family

ID=73681502

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011000133.0A Pending CN112071255A (en) 2020-09-22 2020-09-22 a display panel

Country Status (1)

Country Link
CN (1) CN112071255A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0935491A (en) * 1995-07-18 1997-02-07 Sharp Corp Image display and wiring structure
JP2008026870A (en) * 2006-07-21 2008-02-07 Samsung Electronics Co Ltd Liquid crystal display
US20170084247A1 (en) * 2015-09-21 2017-03-23 Apple Inc. Gate line layout configuration
WO2018040477A1 (en) * 2016-08-31 2018-03-08 深圳市华星光电技术有限公司 Goa driving circuit
CN109599405A (en) * 2019-01-02 2019-04-09 京东方科技集团股份有限公司 Array substrate, display panel, display device and correlation technique

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0935491A (en) * 1995-07-18 1997-02-07 Sharp Corp Image display and wiring structure
JP2008026870A (en) * 2006-07-21 2008-02-07 Samsung Electronics Co Ltd Liquid crystal display
US20170084247A1 (en) * 2015-09-21 2017-03-23 Apple Inc. Gate line layout configuration
WO2018040477A1 (en) * 2016-08-31 2018-03-08 深圳市华星光电技术有限公司 Goa driving circuit
CN109599405A (en) * 2019-01-02 2019-04-09 京东方科技集团股份有限公司 Array substrate, display panel, display device and correlation technique

Similar Documents

Publication Publication Date Title
US10644038B2 (en) Array substrate, display panel, and display device thereof
US9570021B2 (en) Array substrate, flexible display device and electronic device
JP5917694B2 (en) Display device
KR100906103B1 (en) Array Board for Liquid Crystal Display
CN106226963B (en) Array substrate, display panel and display device
US8314766B2 (en) Liquid crystal display panel
CN106707646A (en) Array base plate and display panel
CN110531559B (en) Array substrate, display panel and display device
CN104969283A (en) Display apparatus
CN108573682B (en) Array substrate, display panel and display device
CN113764491B (en) Electroluminescent display panel and display device
US20220181357A1 (en) Array substrate, display panel and display device
CN110187576B (en) Display panel and display device
CN106597713A (en) Array substrate and display panel
CN102323681A (en) Lead structure and display panel with same
CN108831365A (en) Display panel and display device
WO2019205467A1 (en) Tft array substrate and display device
WO2020015070A1 (en) Array substrate
US11640189B2 (en) Source-side fan-out structure, array substrate and display device
US10747059B2 (en) Display apparatus having pattern of slits on top-common electrode
US11256146B2 (en) Electrode structure, array substrate and display device
US20160043055A1 (en) GOA Layout Method, Array Substrate and Display Device
US12045430B2 (en) Display panel and mobile terminal
US20210408214A1 (en) Display panel and display device
CN112071255A (en) a display panel

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20201211

WD01 Invention patent application deemed withdrawn after publication