CN112052115B - Data storage erasure method, device, equipment and computer readable storage medium - Google Patents

Abstract

The invention discloses a data storage erasure erasure method, which comprises the following steps: analyzing a received target data erasure task to obtain a target data block and a target matrix; obtaining a target resource block corresponding to the target data erasure task; The erasure operation is performed on the target data block and the target matrix by using the target resource block based on the time division multiplexing algorithm, and the erasure result is obtained. By applying the technical solutions provided by the embodiments of the present invention, the occupation of CPU computing resources is greatly reduced, and the resource utilization rate is improved. The invention also discloses a data storage and erasure correction device, equipment and storage medium, which have corresponding technical effects.

Description

Data storage erasure method, apparatus, device and computer readable storage medium

technical field

The present invention relates to the field of storage technologies, and in particular, to a data storage erasure correction method, apparatus, device, and computer-readable storage medium.

Background technique

In order to improve the data reliability of the distributed storage system and ensure that the data collection nodes can reconstruct the original files with a high probability, it is necessary to store a certain amount of redundancy on the basis of storing the original data, so that when some nodes appear In the case of failure, the system can still run normally, and the data collection node can still decode and recover the original file. At the same time, in order to maintain the reliability of the system, it is necessary to repair the failed nodes in time.

Erasure code (Erasure Code) belongs to a forward error correction technology in coding theory, which has achieved good results in preventing data loss, so it is introduced into the field of storage applications.

At present, some data storage erasure methods are to allocate a resource block for each output data buffer during the execution of the encoding task or the decoding task. One data erasure task may occupy multiple resource blocks, which will occupy CPU computing resources. more, the resource utilization rate is lower.

To sum up, how to effectively solve the problems that the current data storage erasure method occupies more CPU computing resources and lower resource utilization rate is a problem that those skilled in the art urgently need to solve.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a data storage erasure correction method, which greatly reduces the occupancy of CPU computing resources and improves resource utilization; another purpose of the present invention is to provide a data storage erasure correction device, Devices and computer-readable storage media.

In order to solve the above-mentioned technical problems, the present invention provides the following technical solutions:

A data storage erasure method, comprising:

Analyze the received target data erasure task to obtain the target data block and target matrix;

obtaining the target resource block corresponding to the target data erasure task;

Using the target resource block to perform an erasure operation on the target data block and the target matrix based on a time division multiplexing algorithm, an erasure result is obtained.

In a specific embodiment of the present invention, the received target data erasure task is analyzed to obtain a target data block and a target matrix, including:

Analyze the received target data erasure task to obtain the target erasure task type;

When the target erasure task type is encoding, obtain the target original data block and the target encoding matrix;

When the target erasure erasure task type is decoding, the target remaining data block, the target check data block, and the target decoding matrix are acquired.

In a specific embodiment of the present invention, when the number of the target data erasure tasks is multiple, acquiring the target resource blocks corresponding to the target data erasure tasks includes:

Get each resource block that is currently free;

Using the target resource block to perform an erasure correction operation on the target data block and the target matrix based on a time division multiplexing algorithm, including:

A parallel erasure correction operation is performed on each target data block and each target matrix by using each of the resource blocks based on the time division multiplexing algorithm.

In a specific embodiment of the present invention, after parsing the received target data erasure task to obtain the target data block and the target matrix, the method further includes:

obtaining the data size of the target data block;

Using each of the resource blocks to perform parallel erasure operations on each target data block and each target matrix based on the time division multiplexing algorithm, including:

Time-division multiplexing each of the resource blocks is allocated to each target data block and a matrix row of each target matrix according to the data size;

An erasure correction operation is performed on each of the target data blocks and each of the matrix rows by using each of the resource blocks.

A data storage erasure device, comprising:

The task parsing module is used to parse the received target data erasure task to obtain the target data block and the target matrix;

a resource block obtaining module, configured to obtain a target resource block corresponding to the target data erasure task;

The erasure result obtaining module is configured to use the target resource block to perform an erasure operation on the target data block and the target matrix based on a time division multiplexing algorithm to obtain an erasure result.

In a specific embodiment of the present invention, the task analysis module includes:

The task type obtaining sub-module is used to parse the received target data erasure task to obtain the target erasure task type;

The first input data acquisition submodule is used to acquire the target original data block and the target encoding matrix when the target erasure task type is encoding;

The second input data acquisition sub-module is configured to acquire the target residual data block, the target check data block, and the target decoding matrix when the target erasure erasure task type is decoding.

In a specific embodiment of the present invention, the resource block obtaining module is specifically a module for obtaining currently idle resource blocks when the number of the target data erasure tasks is multiple;

The erasure result obtaining module is specifically a module that uses each target resource block to perform a parallel erasure operation on each target data block and each target matrix based on the time division multiplexing algorithm.

In a specific embodiment of the present invention, it also includes:

a data size obtaining module, configured to obtain the data size of the target data block after parsing the received target data erasure task to obtain the target data block and the target matrix;

The erasure result obtaining module includes:

a resource block allocation submodule, configured to time-division multiplex each resource block and allocate it to each target data block and a matrix row of each target matrix according to the data size;

The erasure erasure operation sub-module is configured to perform erasure operation on each of the target data blocks and each of the matrix rows by using each of the resource blocks.

A data storage erasure device, comprising:

memory for storing computer programs;

The processor is configured to implement the steps of the aforementioned data storage erasure method when executing the computer program.

A computer-readable storage medium stores a computer program on the computer-readable storage medium, and when the computer program is executed by a processor, implements the steps of the foregoing method for data storage erasure correction.

By applying the method provided by the embodiment of the present invention, the received target data erasure task is analyzed to obtain the target data block and the target matrix; the target resource block corresponding to the target data erasure task is obtained; the target resource block is used based on time division multiplexing The algorithm performs the erasure operation on the target data block and the target matrix, and obtains the erasure result. After obtaining the target data block and target matrix required for erasure processing, the time division multiplexing algorithm is used to implement the erasure operation in a specific target resource block. Compared with the existing one, each output data buffer is allocated a resource. Block erasure mode, the present invention greatly reduces the occupancy of CPU computing resources and improves resource utilization.

Correspondingly, the embodiments of the present invention also provide a data storage and erasure correction device, device, and computer-readable storage medium corresponding to the above-mentioned data storage and erasure method, which have the above-mentioned technical effects, and are not repeated here.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

Fig. 1 is a kind of implementation flow chart of the data storage erasure correction method in the embodiment of the present invention;

Fig. 2 is another implementation flow chart of the data storage erasure correction method in the embodiment of the present invention;

3 is a structural block diagram of a single hardware processing unit;

4 is a schematic diagram of resource division of hardware processing erasure tasks in the prior art;

5 is a schematic diagram of resource division of hardware processing erasure tasks in an embodiment of the present invention;

Fig. 6 is another implementation flowchart of the data storage erasure correction method in the embodiment of the present invention;

7 is a structural block diagram of a data storage erasure correction device in an embodiment of the present invention;

FIG. 8 is a structural block diagram of a data storage erasure correction device in an embodiment of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Example 1:

Referring to FIG. 1, FIG. 1 is an implementation flowchart of a data storage erasure correction method in an embodiment of the present invention, and the method may include the following steps:

S101: Analyze the received target data erasure task to obtain a target data block and a target matrix.

When data is backed up or pre-stored backup data is lost, a target data erasure task is generated, and the target data erasure task includes target data blocks and target matrices required for erasure processing. Send the target data erasure task to the erasure processing center, and the erasure processing center receives the target data erasure task, analyzes the received target data erasure task, and obtains the target data block and the target matrix.

Specifically, when the target data erasure task is an encoding task, the target data block includes the original data block, and the target matrix is a matrix pre-written into the matrix queue. When the target data erasure task is a decoding task, the target data block includes the original data block and the check data block, and the target matrix is a matrix pre-written into the matrix queue.

S102: Obtain a target resource block corresponding to the target data erasure task.

The corresponding target resource blocks are allocated for the target data erasure task in advance. After the target data block and the target matrix are obtained by parsing, the target resource block corresponding to the target data erasure task is obtained.

S103: Use the target resource block to perform an erasure operation on the target data block and the target matrix based on a time division multiplexing algorithm, to obtain an erasure result.

After obtaining the target resource block corresponding to the target data erasure task, use the target resource block to perform erasure operations on the target data block and the target matrix based on the time division multiplexing algorithm, and obtain the erasure result.

If the RS (Reed-Solomon Code) code is used for erasure processing, the target data block and the first matrix row in the target matrix can be used to perform Galois field multiplication and Galois field multiplication in the first time period. Galois field addition operation; use the target resource block to sequentially perform Galois field multiplication and Galois field addition operations on the target data block and the second matrix row in the target matrix within the second time period; Each matrix row in the target matrix is completed by Galois field multiplication and Galois field addition. After obtaining the target data block and target matrix required for erasure processing, the time division multiplexing algorithm is used to implement the erasure operation in a specific target resource block. Compared with the existing one, each output data buffer is allocated a resource. Block erasure mode, the present invention greatly reduces the occupancy of CPU computing resources and improves resource utilization.

By applying the method provided by the embodiment of the present invention, the received target data erasure task is analyzed to obtain a target data block and a target matrix; the target resource block corresponding to the target data erasure task is obtained; the target resource block is used based on time division multiplexing The algorithm performs erasure operation on the target data block and each matrix row in the target matrix, and obtains the erasure result. After obtaining the target data block and target matrix required for erasure processing, the time division multiplexing algorithm is used to implement erasure operation in a specific target resource block. Compared with the existing hardware, a hardware is allocated for each output data buffer. In the erasure correction method of the processing unit, the present invention greatly reduces the occupation of CPU computing resources and improves the resource utilization rate.

It should be noted that, based on the foregoing first embodiment, the embodiment of the present invention also provides a corresponding improvement solution. In subsequent embodiments, the same steps or corresponding steps in the above-mentioned first embodiment can be referred to each other, and corresponding beneficial effects can also be referred to each other, which will not be repeated in the following improved embodiments.

Embodiment 2:

Referring to FIG. 2, FIG. 2 is another implementation flowchart of a data storage erasure correction method in an embodiment of the present invention, and the method may include the following steps:

S201: Analyze the received target data erasure task to obtain the target erasure task type.

The target data erasure task includes task type information. After receiving the target data erasure task, the received target data erasure task is analyzed to obtain the target erasure task type. Erasure task types include encoding and decoding.

S202: When the target erasure task type is encoding, obtain the target original data block and the target encoding matrix.

When encoding, the original data block and the encoding matrix pre-written into the matrix queue are needed. When the target erasure task type is encoding, obtain the target original data block and target encoding matrix.

S203: When the target erasure erasure task type is decoding, obtain the target remaining data block, the target check data block, and the target decoding matrix.

When performing decoding, the surviving remaining data blocks, the surviving parity data blocks, and the decoding matrix pre-written into the matrix queue are required. When the target erasure task type is decoding, obtain the target original data block, the target check data block, and the target matrix.

S204: When the number of target data erasure tasks is multiple, acquire each resource block that is currently idle.

When it is determined that the number of target data erasure tasks is multiple, for example, there are currently multiple encoding tasks, or there are multiple decoding tasks, or both encoding tasks and decoding tasks currently exist, obtain each currently idle resource block. .

S205: Use each resource block to perform a parallel erasure correction operation on each target data block and each target matrix based on a time division multiplexing algorithm.

After each resource block that is currently idle is acquired, a parallel erasure operation is performed on each target data block and each target matrix by using each resource block based on a time division multiplexing algorithm. By using multiple resource blocks concurrently and time division multiplexing within a single resource block, the resource utilization rate is improved, thereby improving the data throughput rate. And by expanding the number of input and output channels of the hardware structure and the size of the storage unit of the matrix, it can support different numbers of data nodes k and different numbers of check nodes r, which has relatively strong scalability, and can achieve a hardware It can support all erasure combinations below the design index k and r. At the same time, a hardware supports both encoding and decoding by scheduling the matrix (ie, the encoding matrix or the decoding matrix) and the input data (ie, the data block or the data block and the survival check block).

In a specific example application, see FIG. 3 , which is a structural block diagram of a single resource block. As shown in FIG. 3 , the proposed RS erasure resource block takes a maximum supported data node number k=6 and a maximum supported check node number r=4 as an example. The module is divided into a control path and a data path. The control path is mainly responsible for scheduling the matrix and controlling the flow of data into the multiplication unit; the data path includes data input and output control. The specific functions of each module are introduced as follows:

1. Control path:

Matrix Rows 1 to 4: Store the 1st to 4th rows of the matrix, respectively.

Configuration queue: stores the configuration information that needs to be processed for the resource blocks of the erasure task, including the number of data blocks k, the number of check blocks r, and the block size.

Matrix queue: Store encoding or decoding matrices.

Multiple input one output unit: According to the selection signal, select one signal output from multiple output signals.

Resource block scheduling: by reading the information in the configuration queue, the matrix in the matrix queue is dumped into the first row to the fourth row of the matrix; the data of the control data path flows into the multiplication unit; all (or part) of the 4-row matrix Time division multiplexed call-in multiplication unit; for the output data, according to the configured r information, the control selection signal selects one channel of output data and sends it into the output data buffer.

2. Data path:

Output data buffer: used to buffer input and output data.

Read data control: Under the control of the processing unit scheduling, the data in the output buffer to be processed is read out. For example, in a 4+2 erasure coding configuration, only the first 4 output buffers will be read.

Galois Field Multiplication Unit: completes the multiplication of Galois Field.

Galois field addition unit: completes Galois field addition, that is, XOR operation.

One-input multiple-output unit: Under the control of the selection signal, one output signal is selected to be sent to one of the output channels.

The step-by-step explanation of erasure data flow is as follows:

Step 1: The data is sent to the input buffer 1, 2, 3, 4, 5, 6. When the number of input nodes is less than 6, the input data will only be input to part of the input buffer. For example, for a 2+1 encoding task, only Data will be input to input buffers 1 and 2, and no data will be stored in other input buffers. For encoding or decoding tasks, the input data types are also different. Take k+r encoding or decoding as an example: for encoding tasks, the input data is all k data nodes. For decoding tasks, L data nodes need to be restored as For example, the input data is divided into surviving (k-L) data node data and surviving L check node data, and the sum of the input data nodes is k.

Step 2: When the processing and scheduling unit detects that there is a task input in the configuration queue, it reads the input task type from the configuration queue, including whether the task type is encoding or decoding, the number of data blocks k, and the number of check blocks r. Distribute the matrix to the 1st, 2nd, 3rd, and 4th rows of the matrix by scheduling the matrices that have been written in the matrix queue in advance. If r<4, distribute the matrix to the 1st, 2nd, 3rd, and 4th rows of the partial matrix. For example, in the encoding scene of r=2, the matrix is only distributed to the 1st and 2nd rows. Then, by controlling the input selection signal, the control matrix is sent to the Galois multiplication unit in a time-division multiplexing manner, specifically the first row of the matrix, the second row, the first row, the second row, and so on; by controlling the input data The selection signal sends the data in the input buffer matrix to the Galois multiplication unit in turn. If k<6, then part of the data in the input data buffer is sent to the Galois multiplication unit. For example, in the encoding scene of k=4, only need Send the 1st, 2nd, 3rd, and 4th input data buffer data to the Galois multiplication unit. Until the matrix corresponding to the task, after the data scheduling is completed, switch to the execution of the next erasure task.

Step 3: Complete the matrix multiplication operation. The specific task is to complete the multiplication of a row of the matrix and the input data. The input data is a data block in the encoding scenario, and is a data block and a check block in the decoding scenario. The order of the operation data is that the Galois multiplication unit completes the operation, sends the output multiplication result to the Galois addition unit, and then outputs the addition operation result from the addition unit. The operation only completes the multiplication and addition operation corresponding to the valid data. For example, in the case of k=4, the multiplication units 1, 2, 3, and 4 perform the operation, while the multiplication units 5 and 6 do not participate in the operation, and the multiplication units 5 and 6 directly output the result. 0, has no effect on the XOR result during addition.

Step 4: The processing and scheduling unit determines the first r output queues to be scheduled according to the number of check blocks r for encoding, and the first r output queues for decoding according to the number L of data blocks to be restored. The object of scheduling output is the first L output queues. At the same time, the size of the data to be output to each output buffer queue is determined according to the output data block size of the encoding and decoding task, and the output data selection signal is controlled, and the data is output to the target queue cyclically. , until all output data are output to the output queue, and then switch to the execution of the next erasure task. For example, for an encoding task with r=3 and a block size equal to 1KByte, the output control signal needs to store data in the output buffer according to the following schedule:

The 1st output buffer stores the 1st Byte-> the 2nd output buffer stores the 2nd Byte-> the 3rd output buffer stores the 3rd Byte-> the 1st output buffer stores the 4th Byte and so on until- >The first output buffer stores the 3070th Byte->The second output buffer stores the 3071st Byte->The third output buffer stores the 3072th Byte.

Step 5: The output data buffer provides the data to the external output, and the external output returns the data to the host side. For example, for 4+2 erasure decoding, the block size is 1Kbyte, and there are data nodes 1 and 2 to be restored. The output data buffers 1 and 2 will generate 1Kbyte data output respectively, and the output data buffers 3 and 4 are in the process of executing the task. No data is generated.

The resource blocks in FIG. 3 are suitable for various RS erasure codes, and can handle both encoding and decoding, so as to achieve the same hardware structure and multiplex to realize all the requirements of RS erasure encoding and decoding.

With 4+2 (that is, four target data blocks, two matrix rows, the following can be compared), 3+1, 4+1 three consecutive encoding tasks, see Figure 4, Figure 4 is the hardware processing in the prior art Schematic diagram of resource division of erasure tasks. Referring to FIG. 5, FIG. 5 is a schematic diagram of resource division of an erasure correction task processed by hardware in an embodiment of the present invention. In Figure 4, time t1 processes 4+2 tasks, time t2 processes 3+1 tasks, and time t3 processes 4+1 tasks. It can be seen that in the time t2, the hardware resource multiplication units 4, 5, 6, 7, 8, and the XOR operation unit 2 are in a completely idle state. During the time t3, the hardware resource multiplication units 5, 6, 7, 8, and the XOR operation unit 2 are in a completely idle state. In Figure 5, it can be seen that at time t1+t2, the task processing unit processes 4+2 tasks, at time t1 processing unit 2 processes 3+1 tasks, and at time t2 processing unit 2 processes 4+1 tasks. It can be seen that using the same hardware resources as in FIG. 4 , the same task can be completed in only t1+t2 time, and only the multiplying unit 8 will be idle in t2 time. It can be seen that the use of multiple resource blocks concurrently and time division multiplexing within resource blocks can improve resource utilization, thereby improving data throughput.

Embodiment three:

Referring to FIG. 6, FIG. 6 is another implementation flowchart of a data storage erasure correction method in an embodiment of the present invention, and the method may include the following steps:

S601: Analyze the received target data erasure task to obtain the target erasure task type.

S602: When the target erasure task type is encoding, obtain the target original data block and the target encoding matrix.

S603: When the target erasure erasure task type is decoding, obtain the target remaining data block, the target check data block, and the target decoding matrix.

S604: When the number of target data erasure tasks is multiple, obtain each resource block that is currently idle.

S605: Obtain the data size of the target data block.

S606: Time-division multiplexing and assigning each resource block to each target data block and each matrix row of each target matrix according to the data size.

S607: Use each resource block to perform an erasure correction operation on each target data block and each matrix row.

Corresponding to the above method embodiments, the embodiments of the present invention further provide a data storage erasure correction device, and the data storage erasure correction device described below and the data storage erasure correction method described above can refer to each other correspondingly.

Referring to FIG. 7, FIG. 7 is a structural block diagram of a data storage erasure correction device in an embodiment of the present invention, and the device may include:

The task parsing module 71 is used for parsing the received target data erasure task to obtain the target data block and the target matrix;

The resource block obtaining module 72 is used for obtaining the target resource block corresponding to the target data erasure task;

The erasure result obtaining module 73 is configured to perform an erasure operation on the target data block and the target matrix based on the time division multiplexing algorithm by using the target resource block to obtain an erasure result.

The device provided by the embodiment of the present invention is applied to analyze the received target data erasure task to obtain a target data block and a target matrix; obtain a target resource block corresponding to the target data erasure task; use the target resource block based on time division multiplexing The algorithm performs the erasure operation on the target data block and the target matrix, and obtains the erasure result. After obtaining the target data block and target matrix required for erasure processing, the time division multiplexing algorithm is used to implement the erasure operation in a specific target resource block. Compared with the existing one, each output data buffer is allocated a resource. Block erasure mode, the present invention greatly reduces the occupancy of CPU computing resources and improves resource utilization.

In a specific embodiment of the present invention, the task analysis module 71 includes:

The task type obtaining sub-module is used to parse the received target data erasure task to obtain the target erasure task type;

The first input data acquisition sub-module is configured to acquire the target original data block and the target encoding matrix when the target erasure task type is encoding.

The second input data acquisition sub-module is configured to acquire the target remaining data block, the target check data block, and the target decoding matrix when the target erasure task type is decoding.

In a specific embodiment of the present invention, the resource block obtaining module 72 is specifically a module for obtaining currently idle resource blocks when the number of target data erasure tasks is multiple;

The erasure result obtaining module 73 is specifically a module that uses each resource block to perform a parallel erasure operation on each target data block and each target matrix based on a time division multiplexing algorithm.

In a specific embodiment of the present invention, it also includes:

The data size obtaining module is used to obtain the data size of the target data block after analyzing the received target data erasure task to obtain the target data block and the target matrix;

The erasure result obtaining module 73 includes:

a resource block allocation sub-module, used for time-division multiplexing and allocating each resource block to each target data block and the matrix row of each target matrix according to the data size;

The erasure operation sub-module is used to perform erasure operation on each target data block and each matrix row by using each resource block.

Corresponding to the above method embodiments, see FIG. 8 , which is a schematic diagram of a data storage erasure correction device provided by the present invention, and the device may include:

memory 81 for storing computer programs;

The processor 82 can implement the following steps when executing the computer program stored in the above-mentioned memory 81:

Analyze the received target data erasure task to obtain the target data block and target matrix; obtain the target resource block corresponding to the target data erasure task; use the target resource block to correct the target data block and target matrix based on the time division multiplexing algorithm Delete operation to get the erasure result.

For the introduction of the device provided by the present invention, please refer to the above method embodiments, which will not be repeated in the present invention.

Corresponding to the above method embodiments, the present invention also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the following steps can be implemented:

Analyze the received target data erasure task to obtain the target data block and target matrix; obtain the target resource block corresponding to the target data erasure task; use the target resource block to correct the target data block and target matrix based on the time division multiplexing algorithm Delete operation to get the erasure result.

The computer-readable storage medium may include: a USB flash drive, a removable hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, etc., which can store program codes. medium.

For the introduction of the computer-readable storage medium provided by the present invention, please refer to the foregoing method embodiments, which will not be repeated in the present invention.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other. For the apparatuses, devices, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and reference may be made to the descriptions of the methods for related parts.

The principles and implementations of the present invention are described herein by using specific examples, and the descriptions of the above embodiments are only used to help understand the technical solutions and core ideas of the present invention. It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can also be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims (8)

1. A data storage erasure method, comprising:

analyzing the received target data erasure task to obtain a target data block and a target matrix;

acquiring a target resource block corresponding to the target data erasure task;

carrying out erasure correction operation on the target data block and the target matrix by using the target resource block based on a time division multiplexing algorithm to obtain an erasure correction result;

analyzing the received target data erasure task to obtain a target data block and a target matrix, comprising:

analyzing the received target data erasure task to obtain a target erasure task type;

when the target erasure task type is coding, acquiring a target original data block and a target coding matrix;

when the target erasure correcting task type is decoding, acquiring a target residual data block, a target verification data block and a target decoding matrix;

performing erasure correction operation on the target data block and the target matrix by using the target resource block based on a time division multiplexing algorithm to obtain an erasure correction result, including:

carrying out Galois field multiplication operation and Galois field addition operation on the target data block and a first matrix row in the target matrix in sequence by using the target resource block in a first time period; carrying out Galois field multiplication operation and Galois field addition operation on the target data block and a second matrix row in the target matrix in sequence by using the target resource block in a second time period; until the Galois field multiplication operation and the Galois field addition operation are carried out on the target data block and each matrix row in the target matrix.

2. The data storage erasure correcting method according to claim 1, wherein when the number of the target data erasure correcting tasks is plural, acquiring a target resource block corresponding to the target data erasure correcting task includes:

acquiring each current idle resource block;

performing erasure operation on the target data block and the target matrix by using the target resource block based on a time division multiplexing algorithm, including:

and performing parallel erasure correction operation on each target data block and each target matrix by using each resource block based on the time division multiplexing algorithm.

3. The data storage erasure method according to claim 2, wherein after parsing the received target data erasure task to obtain a target data block and a target matrix, further comprising:

acquiring the data size of the target data block;

performing parallel erasure operation on each target data block and each target matrix by using each resource block based on the time division multiplexing algorithm, wherein the parallel erasure operation comprises the following steps:

distributing each resource block to each target data block and a matrix row of each target matrix in a time division multiplexing manner according to the data size;

and carrying out erasure correction operation on each target data block and each matrix row by using each resource block.

4. A data storage erasure apparatus, comprising:

the task analysis module is used for analyzing the received target data erasure task to obtain a target data block and a target matrix;

a resource block obtaining module, configured to obtain a target resource block corresponding to the target data erasure correcting task;

an erasure result obtaining module, configured to perform erasure operation on the target data block and the target matrix based on a time division multiplexing algorithm by using the target resource block to obtain an erasure result;

the task analysis module is specifically used for analyzing the received target data erasure correcting task to obtain a target erasure correcting task type;

when the target erasure correcting task type is coding, acquiring a target original data block and a target coding matrix;

when the target erasure correcting task type is decoding, acquiring a target residual data block, a target verification data block and a target decoding matrix;

the erasure result obtaining module is specifically configured to perform galois field multiplication and galois field addition on the target data block and a first matrix row in the target matrix sequentially by using the target resource block in a first time period; carrying out Galois field multiplication operation and Galois field addition operation on the target data block and a second matrix row in the target matrix in sequence by using the target resource block in a second time period; until the Galois field multiplication operation and the Galois field addition operation are carried out on the target data block and each matrix row in the target matrix.

5. The data storage erasure correcting apparatus according to claim 4, wherein the resource block obtaining module is specifically a module for obtaining each currently idle resource block when the number of the target data erasure correcting tasks is multiple;

the erasure result obtaining module is specifically a module for performing parallel erasure operation on each target data block and each target matrix by using each target resource block based on the time division multiplexing algorithm.

6. The data storage erasure apparatus of claim 5, further comprising:

the data size acquisition module is used for acquiring the data size of the target data block after analyzing the received target data erasure task to obtain a target data block and a target matrix;

the erasure result obtaining module includes:

the resource block distribution submodule is used for distributing each resource block to each target data block and each matrix row of each target matrix in a time division multiplexing mode according to the data size;

and the erasure correction operation submodule is used for carrying out erasure correction operation on each target data block and each matrix row by using each resource block.

7. A data storage erasure device, comprising:

a memory for storing a computer program;

a processor for implementing the steps of the data storage erasure method according to any one of claims 1 to 3 when executing said computer program.

8. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the data storage erasure method according to any one of claims 1 to 3.

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