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CN112039484A - A thin-film bulk acoustic wave resonator and its manufacturing method - Google Patents

A thin-film bulk acoustic wave resonator and its manufacturing method Download PDF

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CN112039484A
CN112039484A CN202010229389.2A CN202010229389A CN112039484A CN 112039484 A CN112039484 A CN 112039484A CN 202010229389 A CN202010229389 A CN 202010229389A CN 112039484 A CN112039484 A CN 112039484A
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cavity
electrode
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CN112039484B (en
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黄河
罗海龙
李伟
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China Core Integrated Circuit Ningbo Co Ltd
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/15Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
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Abstract

本发明提供了一种薄膜体声波谐振器及其制造方法,其中,薄膜体声波谐振器包括:承载衬底,所述承载基底包括第一半导体层和第一器件层;第一微器件,所述第一微器件嵌入于所述承载衬底中,且所述第一微器件的至少部分位于所述第一器件层中;介质层,键合于所述第一器件层上,所述介质层围成第一空腔,所述第一空腔暴露出所述承载衬底的表面;压电叠层结构,覆盖所述第一空腔,所述压电叠层结构从下至上包括依次层叠的第一电极、压电层和第二电极;所述第一空腔形成于所述压电叠层结构之前,位于所述压电叠层结构的下方;第一电连接结构,连接所述第一微器件,将所述第一微器件电性引出。本发明能够提高谐振器的集成度。

Figure 202010229389

The present invention provides a thin-film bulk acoustic resonator and a method for manufacturing the same, wherein the thin-film bulk acoustic resonator includes: a carrier substrate, the carrier substrate includes a first semiconductor layer and a first device layer; a first micro-device, the The first micro-device is embedded in the carrier substrate, and at least part of the first micro-device is located in the first device layer; a dielectric layer is bonded on the first device layer, and the dielectric layer is The layers enclose a first cavity, and the first cavity exposes the surface of the carrier substrate; the piezoelectric laminated structure covers the first cavity, and the piezoelectric laminated structure includes sequentially from bottom to top The laminated first electrode, the piezoelectric layer and the second electrode; the first cavity is formed before the piezoelectric laminated structure, and is located below the piezoelectric laminated structure; the first electrical connection structure is connected to the The first micro device is electrically led out. The present invention can improve the integration degree of the resonator.

Figure 202010229389

Description

一种薄膜体声波谐振器及其制造方法A thin-film bulk acoustic wave resonator and its manufacturing method

技术领域technical field

本发明涉及半导体器件制造领域,尤其涉及一种薄膜体声波谐振器及其制造方法。The invention relates to the field of semiconductor device manufacturing, in particular to a thin-film bulk acoustic wave resonator and a manufacturing method thereof.

背景技术Background technique

随着无线通讯技术的不断发展,为了满足各种无线通讯终端的多功能化需求,终端设备需要能够利用不同的载波频谱传输数据,同时,为了在有限的带宽内支持足够的数据传输率,对于射频系统也提出了严格的性能要求。射频滤波器是射频系统的重要组成部分,可以将通信频谱外的干扰和噪声滤出以满足射频系统和通信协议对于信噪比的需求。以手机为例,由于每一个频带需要有对应的滤波器,一台手机中可能需要设置数十个滤波器。With the continuous development of wireless communication technology, in order to meet the multi-functional requirements of various wireless communication terminals, the terminal equipment needs to be able to transmit data using different carrier frequency spectrums. RF systems also impose stringent performance requirements. The radio frequency filter is an important part of the radio frequency system, which can filter out the interference and noise outside the communication spectrum to meet the requirements of the radio frequency system and the communication protocol for the signal-to-noise ratio. Taking a mobile phone as an example, since each frequency band needs a corresponding filter, dozens of filters may need to be set in a mobile phone.

通常,薄膜体声波谐振器包括两个薄膜电极,并且两个薄膜电极之间设有压电薄膜层,其工作原理为利用压电薄膜层在交变电场下产生振动,该振动激励出沿压电薄膜层厚度方向传播的体声波,此声波传至上下电极与空气交界面被反射回来,进而在薄膜内部来回反射,形成震荡。当声波在压电薄膜层中传播正好是半波长的奇数倍时,形成驻波震荡。Generally, a thin-film bulk acoustic wave resonator includes two thin-film electrodes, and a piezoelectric thin-film layer is arranged between the two thin-film electrodes. The bulk acoustic wave propagating in the thickness direction of the electric film layer is transmitted to the interface between the upper and lower electrodes and the air and is reflected back, and then reflected back and forth inside the film to form an oscillation. Standing wave oscillations are formed when a sound wave propagates in a piezoelectric film layer that is exactly an odd multiple of a half-wavelength.

但是,传统制作出的空腔型薄膜体声波谐振器,由于空腔的形成工艺受限,空腔下方的衬底中无法集成微器件,只能通过外部器件连接谐振器实现相关功能,导致器件体积大、引线长,使谐振器的集成度不高,无法满足器件小型化的需求。However, the traditionally fabricated cavity-type thin-film BAW resonator cannot integrate micro-devices in the substrate under the cavity due to the limitation of the cavity formation process, and can only connect the resonator with external devices to realize related functions, resulting in the device Due to the large volume and long lead wires, the integration of the resonator is not high, which cannot meet the requirements of miniaturization of the device.

发明内容SUMMARY OF THE INVENTION

本发明揭示了一种薄膜体声波谐振器及其制造方法,能够解决薄膜体声波谐振器集成度不高的问题。The invention discloses a thin film bulk acoustic wave resonator and a manufacturing method thereof, which can solve the problem of low integration of the thin film bulk acoustic wave resonator.

为解决上述技术问题,本发明提供了一种薄膜体声波谐振器,包括:In order to solve the above-mentioned technical problems, the present invention provides a thin-film bulk acoustic resonator, comprising:

承载衬底,所述承载基底包括第一半导体层和第一器件层;a carrier substrate, the carrier substrate includes a first semiconductor layer and a first device layer;

第一微器件,所述第一微器件嵌入于所述承载衬底中,且所述第一微器件的至少部分位于所述第一器件层中;a first micro-device, the first micro-device is embedded in the carrier substrate, and at least a portion of the first micro-device is located in the first device layer;

介质层,键合于所述第一器件层上,所述介质层围成第一空腔,所述第一空腔暴露出所述承载衬底的表面;a dielectric layer, bonded on the first device layer, the dielectric layer encloses a first cavity, and the first cavity exposes the surface of the carrier substrate;

压电叠层结构,覆盖所述第一空腔,所述压电叠层结构从下至上包括依次层叠的第一电极、压电层和第二电极;所述第一空腔形成于所述压电叠层结构之前,位于所述压电叠层结构的下方;The piezoelectric laminated structure covers the first cavity, and the piezoelectric laminated structure includes a first electrode, a piezoelectric layer and a second electrode stacked in sequence from bottom to top; the first cavity is formed in the Before the piezoelectric stack structure, it is located below the piezoelectric stack structure;

第一电连接结构,连接所述第一微器件,将所述第一微器件电性引出。The first electrical connection structure connects the first micro-device and electrically leads the first micro-device.

本发明还提供了一种薄膜体声波谐振器的制造方法,包括:The present invention also provides a method for manufacturing the thin-film bulk acoustic wave resonator, comprising:

提供临时衬底;provision of temporary substrates;

在所述临时衬底上形成压电叠层结构,所述压电叠层结构包括由下至上依次设置的第二电极、压电层、第一电极;forming a piezoelectric stack structure on the temporary substrate, the piezoelectric stack structure comprising a second electrode, a piezoelectric layer, and a first electrode sequentially arranged from bottom to top;

形成介质层,覆盖所述压电叠层结构;forming a dielectric layer to cover the piezoelectric laminated structure;

图形化所述介质层,形成第一空腔,所述第一空腔贯穿所述介质层;patterning the dielectric layer to form a first cavity, the first cavity passing through the dielectric layer;

提供承载衬底,所述承载基底包括第一半导体层和第一器件层,所述承载衬底的第一表面嵌入有第一微器件,所述第一器件层所在侧为所述承载基底的第一表面所在侧;A carrier substrate is provided, the carrier substrate includes a first semiconductor layer and a first device layer, a first micro-device is embedded in a first surface of the carrier substrate, and the side where the first device layer is located is the side of the carrier substrate. the side where the first surface is located;

键合所述承载衬底至所述介质层上、覆盖所述第一空腔,并使所述第一表面朝向所述第一空腔;bonding the carrier substrate to the dielectric layer, covering the first cavity, and making the first surface face the first cavity;

去除所述临时衬底;removing the temporary substrate;

形成第一电连接结构,将所述第一微器件与外部信号电连接。A first electrical connection structure is formed to electrically connect the first micro device with an external signal.

本发明的有益效果在于:The beneficial effects of the present invention are:

在键合承载衬底前,在承载衬底中预先形成第一微器件,与谐振器的制作分开,缩短制程时间。微器件可以单独制作,不用在谐振器制造流程中制作,避免谐振器结构承受制作微器件时的工艺环境,提高谐振器的稳定性。由于本结构是通过键合的方式将承载衬底键合在介质层上,使在承载衬底中预先形成第一微器件成为可能。Before bonding the carrier substrate, the first micro device is pre-formed in the carrier substrate, which is separated from the fabrication of the resonator and shortens the process time. The micro-devices can be fabricated independently without being fabricated in the resonator manufacturing process, so that the resonator structure can be prevented from being subjected to the process environment when the micro-devices are fabricated, and the stability of the resonator can be improved. Since the structure is to bond the carrier substrate on the dielectric layer by means of bonding, it is possible to form the first micro device in the carrier substrate in advance.

进一步地,封盖基板中也形成有微器件,进一步提高了谐振器的集成度。Further, micro-devices are also formed in the cover substrate, which further improves the integration degree of the resonator.

进一步地,介质层与承载衬底键合面(第一器件层)的材质相同,可以通过原子键直接键合,提高键合强度,简化工艺流程。Further, the material of the bonding surface (the first device layer) of the dielectric layer and the carrier substrate is the same, and can be directly bonded by atomic bonds, which improves the bonding strength and simplifies the process flow.

进一步地,第一导电插塞和第二导电插塞位于谐振器的同侧,方便工艺的制造流程。Further, the first conductive plug and the second conductive plug are located on the same side of the resonator, which facilitates the manufacturing process of the process.

进一步地,沿有效谐振区的边界设置凸起,使有效谐振区内部和凸起所在的区域声阻抗失配,有效防止声波的横向泄露,提高了谐振器的品质因数;Further, the bulge is arranged along the boundary of the effective resonant area, so that the acoustic impedance of the inside of the effective resonant area and the area where the bulge is located are mismatched, the lateral leakage of the acoustic wave is effectively prevented, and the quality factor of the resonator is improved;

进一步地,通过第一沟槽和第二沟槽定义出谐振器的有效谐振区,第一沟槽和第二沟槽分别贯穿第一电极和第二电极,压电层保持完整的膜层未经过刻蚀,保证了谐振器的结构强度,提高了制造谐振器的成品率。Further, the effective resonance area of the resonator is defined by the first groove and the second groove, the first groove and the second groove penetrate the first electrode and the second electrode respectively, and the piezoelectric layer keeps a complete film layer. After etching, the structural strength of the resonator is ensured, and the yield of manufacturing the resonator is improved.

附图说明Description of drawings

通过结合附图对本发明示例性实施例进行更详细的描述,本发明的上述以及其它目的、特征和优势将变得更加明显,在本发明示例性实施例中,相同的参考标号通常代表相同部件。The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of the exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which the same reference numerals generally refer to the same parts .

图1示出了实施例1的一种薄膜体声波谐振器的结构示意图。FIG. 1 shows a schematic structural diagram of a thin film bulk acoustic wave resonator of Example 1. FIG.

图2至图11示出了实施例2的一种薄膜体声波谐振器的制造方法的不同步骤对应的结构示意图。2 to 11 are schematic structural diagrams corresponding to different steps of a method for manufacturing a thin film bulk acoustic resonator according to Embodiment 2.

附图标记说明:Description of reference numbers:

100A-第一半导体层;100B-第一器件层;1000-第一微器件;1001-第一导电插塞;101-键合层;102介质层;103-第一电极;104-压电层;105-第二电极;106-接合层;110a-第一空腔;110b-第二空腔;120-导电互连结构;130a-第一沟槽;130b-第二沟槽;141-第一导电互连层;142-第一导电凸起;151-第二导电互连层;152-第二导电凸起;160-绝缘层;200A-第二半导体层;200B-第二器件层;2000-第二微器件;2001-第二导电插塞;40-凸起;300-临时衬底。100A-first semiconductor layer; 100B-first device layer; 1000-first micro-device; 1001-first conductive plug; 101-bonding layer; 102-dielectric layer; 103-first electrode; 104-piezoelectric layer 105-second electrode; 106-bonding layer; 110a-first cavity; 110b-second cavity; 120-conductive interconnection structure; 130a-first trench; 130b-second trench; 141-th A conductive interconnection layer; 142-first conductive bump; 151-second conductive interconnection layer; 152-second conductive bump; 160-insulation layer; 200A-second semiconductor layer; 200B-second device layer; 2000-second micro-device; 2001-second conductive plug; 40-bump; 300-temporary substrate.

具体实施方式Detailed ways

以下结合附图和具体实施例对本发明作进一步详细说明。根据下面的说明和附图,本发明的优点和特征将更清楚,然而,需说明的是,本发明技术方案的构思可按照多种不同的形式实施,并不局限于在此阐述的特定实施例。附图均采用非常简化的形式且均使用非精准的比例,仅用以方便、明晰地辅助说明本发明实施例的目的。The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and accompanying drawings. However, it should be noted that the concept of the technical solution of the present invention can be implemented in various forms, and is not limited to the specific implementation described here. example. The accompanying drawings are all in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

应当明白,当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本发明教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等,在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语意图还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,然后,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。Spatial relational terms such as "under", "below", "below", "under", "above", "above", etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时,单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”,当在该说明书中使用时,确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

如果本文的方法包括一系列步骤,且本文所呈现的这些步骤的顺序并非必须是可执行这些步骤的唯一顺序,且一些的步骤可被省略和/或一些本文未描述的其他步骤可被添加到该方法。若某附图中的构件与其他附图中的构件相同,虽然在所有附图中都可轻易辨认出这些构件,但为了使附图的说明更为清楚,本说明书不会将所有相同构件的标号标于每一图中。If a method herein includes a series of steps, the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the steps may be omitted and/or some other steps not described herein may be added to this method. If the components in a certain drawing are the same as the components in other drawings, although these components can be easily identified in all the drawings, in order to make the description of the drawings clearer, this specification will not refer to all the same components. Numbers are attached to each figure.

实施例1Example 1

本实施例提供了一种薄膜体声波谐振器,图1示出了实施例1的一种薄膜压电声波谐振器的结构示意图,请参考图1,所述薄膜体声波谐振器包括:This embodiment provides a thin-film bulk acoustic resonator. FIG. 1 shows a schematic structural diagram of a thin-film piezoelectric acoustic resonator according to Embodiment 1. Please refer to FIG. 1. The thin-film bulk acoustic resonator includes:

承载衬底,所述承载衬底包括第一半导体层100A和第一器件层100B;a carrier substrate, the carrier substrate includes a first semiconductor layer 100A and a first device layer 100B;

第一微器件1000,所述第一微器件1000嵌入于所述承载衬底中,且所述第一微器件1000的至少部分位于所述第一器件层100B中;a first micro device 1000, the first micro device 1000 is embedded in the carrier substrate, and at least part of the first micro device 1000 is located in the first device layer 100B;

介质层102,键合于所述第一器件层100B上,所述介质层102围成第一空腔110a,所述第一空腔110a暴露出所述承载衬底的表面;The dielectric layer 102 is bonded to the first device layer 100B, the dielectric layer 102 encloses a first cavity 110a, and the first cavity 110a exposes the surface of the carrier substrate;

压电叠层结构,覆盖所述第一空腔110a,所述压电叠层结构从下至上包括依次层叠的第一电极103、压电层104和第二电极105,所述第一空腔110a形成于所述压电叠层结构之前,位于所述压电叠层结构的下方;The piezoelectric stack structure covers the first cavity 110a, the piezoelectric stack structure includes a first electrode 103, a piezoelectric layer 104 and a second electrode 105 stacked in sequence from bottom to top, the first cavity 110a is formed before the piezoelectric stack structure, and is located below the piezoelectric stack structure;

第一电连接结构,连接于所述第一微器件,所述第一电连接结构用于对所述第一微器件供电。The first electrical connection structure is connected to the first micro-device, and the first electrical connection structure is used for supplying power to the first micro-device.

需要说明的是,所述第一空腔110a形成于所述压电叠层结构之前,位于所述压电叠层结构的下方做如下解释:现有技术中,谐振器在制造过程为,在基板上刻蚀形成空腔,在空腔中填充牺牲层材料,在牺牲层材料和基板的上方形成压电叠层结构,释放牺牲层后,形成下空腔,压电叠层结构悬空于下空腔之上。压电叠层结构形成之后还可以在压电叠层的上表面形成封盖层,封盖层与压电叠层结构之间的空腔为上空腔。本发明的第一空腔对应于下空腔。本实施例的承载衬底是在形成第一空腔后键合在介质层上的。承载衬底需要为谐振器第二电极的图案化制程、接合层的制作及图案化、封盖层的制作/研磨,或者第二电连接结构的制作等提供较好的支撑。由于本结构是通过键合的方式将承载衬底键合在介质层上,使在承载衬底中预先形成第一微器件成为可能。通过牺牲层的方法形成下空腔,无法在下空腔的底部形成微器件。在键合承载衬底前,在承载衬底中预先形成第一微器件,缩短制程时间。微器件可以单独制作,不用在谐振器制造流程中制作,避免谐振器结构承受制作微器件时的工艺环境,提高谐振器的稳定性。It should be noted that, the first cavity 110a is formed before the piezoelectric stack structure, and is located under the piezoelectric stack structure as follows: In the prior art, the resonator is manufactured as follows: A cavity is formed by etching on the substrate, the sacrificial layer material is filled in the cavity, and a piezoelectric laminate structure is formed above the sacrificial layer material and the substrate. After the sacrificial layer is released, a lower cavity is formed, and the piezoelectric laminate structure is suspended at the bottom. above the cavity. After the piezoelectric stack structure is formed, a capping layer may also be formed on the upper surface of the piezoelectric stack, and the cavity between the capping layer and the piezoelectric stack structure is an upper cavity. The first cavity of the present invention corresponds to the lower cavity. The carrier substrate of this embodiment is bonded on the dielectric layer after the first cavity is formed. The carrier substrate needs to provide better support for the patterning process of the second electrode of the resonator, the fabrication and patterning of the bonding layer, the fabrication/grinding of the capping layer, or the fabrication of the second electrical connection structure. Since the structure is to bond the carrier substrate on the dielectric layer by means of bonding, it is possible to form the first micro device in the carrier substrate in advance. The lower cavity is formed by the method of the sacrificial layer, and the micro device cannot be formed at the bottom of the lower cavity. Before bonding the carrier substrate, the first micro device is pre-formed in the carrier substrate to shorten the process time. The micro-devices can be fabricated independently without being fabricated in the resonator manufacturing process, so that the resonator structure can be prevented from being subjected to the process environment when the micro-devices are fabricated, and the stability of the resonator can be improved.

具体地,本实施例中,所述承载基底包括第一半导体层100A和第一器件层100B,所述第一器件层100B靠近所述第一空腔110a所在侧,所述第一微器件1000至少部分形成于所述第一器件层100B中。所述第一微器件1000包括:二极管、三极管、MOS晶体管、静电释放保护器件、电阻、电容或电感。当所述第一微器件1000为电阻、电容或电感时,第一微器件1000可以全部位于所述器件层100B中,当第一微器件1000为三极管、MOS晶体管时,其源级和漏级可以位于第一半导体层100A中。Specifically, in this embodiment, the carrier substrate includes a first semiconductor layer 100A and a first device layer 100B, the first device layer 100B is close to the side where the first cavity 110a is located, and the first micro device 1000 at least partially formed in the first device layer 100B. The first micro-device 1000 includes: diodes, triodes, MOS transistors, electrostatic discharge protection devices, resistors, capacitors or inductors. When the first micro-device 1000 is a resistor, a capacitor or an inductor, the first micro-device 1000 may all be located in the device layer 100B. When the first micro-device 1000 is a triode or a MOS transistor, the source and drain stages of the first micro-device 1000 are may be in the first semiconductor layer 100A.

第一半导体层100A的材料包括硅(Si)、锗(Ge)、锗硅(SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V化合物半导体等。第一器件层100B的材料包括氧化硅、氮化硅、氮氧化硅、碳氮化硅。第一器件层100B和介质层102通过键合的方式进行结合。介质层102的材料可以是任意适合的介电材料,包括但不限于氧化硅、氮化硅、氮氧化硅、碳氮化硅或硅酸乙酯。当第一器件层100B和介质层102的材料相同时,可以采用原子键键合直接进行键合。当第一器件层100B和介质层102的材料不同时,可以在两者的键合面形成键合层,所述键合层的材料包括:氧化硅、氮化硅、多晶硅、硅酸乙酯或有机固化膜。本实施例,第一器件层100B和介质层均为氧化硅,采用原子键进行键合,键合结构强且工艺流程简单。当通过键合层进行键合时,在所述介质层101与所述承载衬底之间形成有一层键合层结构。通过介质层与键合层的材料可知,两者的材料可以相同也可以不同。The material of the first semiconductor layer 100A includes silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs) , indium phosphide (InP) or other III/V compound semiconductors, etc. Materials of the first device layer 100B include silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride. The first device layer 100B and the dielectric layer 102 are combined by bonding. The material of the dielectric layer 102 may be any suitable dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or ethyl silicate. When the materials of the first device layer 100B and the dielectric layer 102 are the same, atomic bonding can be used for direct bonding. When the materials of the first device layer 100B and the dielectric layer 102 are different, a bonding layer can be formed on the bonding surfaces of the two, and the material of the bonding layer includes: silicon oxide, silicon nitride, polysilicon, ethyl silicate or organic cured film. In this embodiment, the first device layer 100B and the dielectric layer are both silicon oxides, which are bonded by atomic bonds. The bonding structure is strong and the process flow is simple. When bonding is performed through a bonding layer, a bonding layer structure is formed between the dielectric layer 101 and the carrier substrate. It can be known from the materials of the dielectric layer and the bonding layer that the materials of the two can be the same or different.

本实施例中,第一空腔110a为封闭的空腔,第一空腔110a可以通过刻蚀工艺刻蚀介质层102形成。第一空腔110a的底面的形状为矩形,但在本发明的其他实施例中,第一空腔110a在第一电极103底面的形状还可以是圆形、椭圆形或是矩形以外的多边形,例如五边形、六边形等。In this embodiment, the first cavity 110a is a closed cavity, and the first cavity 110a can be formed by etching the dielectric layer 102 through an etching process. The shape of the bottom surface of the first cavity 110a is a rectangle, but in other embodiments of the present invention, the shape of the bottom surface of the first cavity 110a on the bottom surface of the first electrode 103 may also be a circle, an ellipse, or a polygon other than a rectangle. For example, pentagons, hexagons, etc.

第一空腔110a的上方设有压电叠层结构,压电叠层结构从下至上依次包括第一电极103、压电层104和第二电极105。第一电极103位于介质层102上,压电层104位于第一电极103上,第二电极105位于压电层104上。第一空腔110a的上方的第一电极103、压电层104和第二电极105在垂直于承载衬底100的方向上设有重叠区域为有效谐振区,所述有效谐振区的边界位于所述第一空腔110a包围的区域内。有效谐振区的形状为不规则多边形,如不存在平行对边的五边形、六边形等。A piezoelectric laminated structure is disposed above the first cavity 110a, and the piezoelectric laminated structure includes a first electrode 103, a piezoelectric layer 104 and a second electrode 105 in sequence from bottom to top. The first electrode 103 is located on the dielectric layer 102 , the piezoelectric layer 104 is located on the first electrode 103 , and the second electrode 105 is located on the piezoelectric layer 104 . The first electrode 103, the piezoelectric layer 104 and the second electrode 105 above the first cavity 110a are provided with overlapping regions in the direction perpendicular to the carrier substrate 100 as an effective resonance region, and the boundary of the effective resonance region is located at the within the area surrounded by the first cavity 110a. The shape of the effective resonance region is an irregular polygon, such as a pentagon or a hexagon without parallel opposite sides.

本实施例中,压电层104遮盖所述第一空腔110a,遮盖所述第一空腔110a应当理解为压电层104为完整的膜层,没有经过刻蚀。并不意味着压电层104将第一空腔110a全部遮盖,形成密封的空腔。当然,压电层104可以完全遮盖第一空腔110a,形成密封的空腔。压电层不经过刻蚀可以保证压电叠层结构具有一定的厚度,使谐振器具有一定的结构强度。提高制作谐振器的成品率。In this embodiment, the piezoelectric layer 104 covers the first cavity 110a, and covering the first cavity 110a should be understood as the piezoelectric layer 104 is a complete film layer without being etched. It does not mean that the piezoelectric layer 104 completely covers the first cavity 110a to form a sealed cavity. Of course, the piezoelectric layer 104 can completely cover the first cavity 110a to form a sealed cavity. Without etching the piezoelectric layer, the piezoelectric laminated structure can be guaranteed to have a certain thickness, so that the resonator has a certain structural strength. Improve the yield of making resonators.

在一个实施例中,介质层102与第一电极103之间还设置有刻蚀停止层,其材质包括但不限于氮化硅(Si3N4)和氮氧化硅(SiON)。刻蚀停止层一方面可以用于增加最终制造的薄膜体声波谐振器的结构稳定性,另一方面,刻蚀停止层与介质层102相比具有较低的刻蚀速率,可以在刻蚀介质层102形成第一空腔110a的过程中防止过刻蚀,保护位于其下的第一电极103的表面不受到损伤,从而提高器件性能与可靠性。In one embodiment, an etch stop layer is further disposed between the dielectric layer 102 and the first electrode 103, and its material includes but not limited to silicon nitride (Si3N4) and silicon oxynitride (SiON). On the one hand, the etch stop layer can be used to increase the structural stability of the final fabricated thin-film bulk acoustic wave resonator; In the process of forming the first cavity 110a of the layer 102, over-etching is prevented, and the surface of the first electrode 103 located thereunder is protected from damage, thereby improving the performance and reliability of the device.

本实施例中,压电叠层的结构上方包括接合层106,所述接合层106围成第二空腔110b,所述第二空腔110b暴露出所述压电叠层结构的表面,所述第二空腔110b位于所述第一空腔110a上方。还包括封盖基板,设置于接合层106上,并覆盖所述第二空腔110b。本实施例中,所述封盖基板中靠近所述第二空腔110b侧嵌入有第二微器件2000。In this embodiment, a bonding layer 106 is included on top of the piezoelectric stack structure, the bonding layer 106 encloses a second cavity 110b, and the second cavity 110b exposes the surface of the piezoelectric stack structure, so The second cavity 110b is located above the first cavity 110a. It also includes a capping substrate, which is disposed on the bonding layer 106 and covers the second cavity 110b. In this embodiment, a second micro device 2000 is embedded in the cover substrate near the second cavity 110b.

本实施例中,封盖基板为双层结构,包括第二半导体层200A和第二器件层200B。所述第二器件层100B靠近所述第二空腔110b所在侧,所述第一微器件1000至少部分形成于所述第二器件层200B中。第二微器件1000的种类及与封盖基板的位置关系参照第一微器件1000的种类及与承载衬底的位置关系的相关描述,第二半导体层200A的可选材料参照第一半导体层100A的材料种类,第二器件层200B的可选材料参照第一器件层100B的材料种类,此处不在赘述。接合层106可以采用常规的键合材料,例如氧化硅、氮化硅、氮氧化硅、硅酸乙酯等,也可以是光固化材料或热固化材料等黏结剂,例如粘片膜(Die Attach Film,DAF)或干膜(Dry Film),制作和图案化工艺相对简单。接合层的材料和封盖基板200的材料可以相同,两者为一体结构,第二空腔110b通过在膜层(形成接合层106和封盖基板200)中形成空间而形成。In this embodiment, the capping substrate has a double-layer structure, including a second semiconductor layer 200A and a second device layer 200B. The second device layer 100B is close to the side where the second cavity 110b is located, and the first micro device 1000 is at least partially formed in the second device layer 200B. For the type of the second micro-device 1000 and the positional relationship with the cover substrate, please refer to the description of the type of the first micro-device 1000 and the positional relationship with the carrier substrate. For the optional material of the second semiconductor layer 200A, refer to the first semiconductor layer 100A For the optional material of the second device layer 200B, refer to the material type of the first device layer 100B, which will not be repeated here. The bonding layer 106 may use conventional bonding materials, such as silicon oxide, silicon nitride, silicon oxynitride, ethyl silicate, etc., or may be adhesives such as light-curing materials or thermal-curing materials, such as die attach film. Film, DAF) or dry film (Dry Film), the production and patterning process is relatively simple. The material of the bonding layer and the material of the capping substrate 200 may be the same, and the two have an integral structure. The second cavity 110b is formed by forming a space in the film layer (for forming the bonding layer 106 and the capping substrate 200 ).

为了给第一微器件1000和第二微器件2000供电,谐振器还包括连接于第一微器件1000的第一电连接结构以及连接于第二微器件2000的第二电连接结构,本实施例中,第一电连接结构为第一导电插塞1001,第二电连接结构为第二导电插塞2001。In order to supply power to the first micro-device 1000 and the second micro-device 2000, the resonator further includes a first electrical connection structure connected to the first micro-device 1000 and a second electrical connection structure connected to the second micro-device 2000. This embodiment Among them, the first electrical connection structure is the first conductive plug 1001 , and the second electrical connection structure is the second conductive plug 2001 .

本实施例中,第一导电插塞1001从所述承载衬底的底面延伸至所述第一微器件1000。第二导电插塞2001从所述承载衬底的底面延伸至所述第二微器件2000。In this embodiment, the first conductive plug 1001 extends from the bottom surface of the carrier substrate to the first micro device 1000 . The second conductive plug 2001 extends from the bottom surface of the carrier substrate to the second micro device 2000 .

在另一个实施例中,第一导电插塞可以从所述封盖基板的顶面延伸至所述第一微器件。第二导电插塞也从所述封盖基板的顶面延伸至所述第二微器件。以上两种情况两导电插塞都是从谐振器的同侧电连接于微器件。主要是考虑制作导电插塞时导电插塞的相对侧需要有一定强度的支撑。在制作导电插塞时,制作导电插塞的一侧(承载衬底或封盖基板)需要进行减薄处理,厚度约100微米,导电插塞的相对侧(承载衬底或封盖基板)不做减薄处理,厚度约几百微米,为制造工艺的提供一定强度的支撑。当然,在工艺条件允许的情况下,第一导电插塞和第二导电插塞可以设置于谐振器的相对两侧。在一个实施例中,还可以包括第三电连接结构,如第三导电插塞,将第一微器件和第二微器件进行电连接。In another embodiment, a first conductive plug may extend from the top surface of the capping substrate to the first micro-device. A second conductive plug also extends from the top surface of the capping substrate to the second micro-device. In the above two cases, the two conductive plugs are electrically connected to the micro-device from the same side of the resonator. The main consideration is that the opposite side of the conductive plug needs to be supported with a certain strength when making the conductive plug. When making conductive plugs, the side of the conductive plugs (the carrier substrate or the cover substrate) needs to be thinned to a thickness of about 100 microns, and the opposite side of the conductive plugs (the carrier substrate or the cover substrate) is not Do thinning treatment, the thickness is about several hundred microns, which provides a certain strength support for the manufacturing process. Of course, if the process conditions permit, the first conductive plug and the second conductive plug may be disposed on opposite sides of the resonator. In one embodiment, a third electrical connection structure, such as a third conductive plug, may also be included to electrically connect the first micro-device and the second micro-device.

本实施例中,还包括第一电极引出部、第二电极引出部,第一电极引出部用于将电信号引入有效谐振区的第一电极103,第二电极引出部用于将电信号引入有效谐振区的第二电极105。第一电极103和第二电极105通电后,压电层104上下表面产生压差,形成驻波振荡。导电互连结构120用于将有效谐振区外的第一电极和第二电极短接。由图可知,有效谐振区外也包含在垂直于压电层方向上压电层、第一电极、第二电极相互重叠的区域。当第一电极和第二电极通电,有效谐振区外部的压电层表面上下也能够产生压差,也产生了驻波振荡,然而有效谐振区外部的驻波振荡是不希望发生的,本实施例将有效谐振区外部的第一电极和第二电极短接,使有效谐振区外部的压电层上下电压一致,有效谐振区外部不能够产生驻波振荡,提高了谐振器的Q值。具体的第一电极引出部、第二电极引出部和导电互连结构120的结构如下:In this embodiment, a first electrode lead-out portion and a second electrode lead-out portion are further included. The first electrode lead-out portion is used for introducing electrical signals into the first electrode 103 of the effective resonance region, and the second electrode lead-out portion is used for introducing electrical signals into the first electrode 103 of the effective resonance region. The second electrode 105 of the effective resonance region. After the first electrode 103 and the second electrode 105 are energized, a voltage difference is generated between the upper and lower surfaces of the piezoelectric layer 104 to form a standing wave oscillation. The conductive interconnect structure 120 is used to short the first electrode and the second electrode outside the effective resonance region. It can be seen from the figure that the area where the piezoelectric layer, the first electrode and the second electrode overlap each other in the direction perpendicular to the piezoelectric layer is also included outside the effective resonance area. When the first electrode and the second electrode are energized, a voltage difference can also be generated above and below the surface of the piezoelectric layer outside the effective resonance area, and standing wave oscillation is also generated. However, the standing wave oscillation outside the effective resonance area is undesirable. For example, the first electrode and the second electrode outside the effective resonance area are short-circuited, so that the upper and lower voltages of the piezoelectric layer outside the effective resonance area are consistent, and standing wave oscillation cannot be generated outside the effective resonance area, which improves the Q value of the resonator. The specific structures of the first electrode lead-out portion, the second electrode lead-out portion and the conductive interconnection structure 120 are as follows:

第一电极引出部包括:The first electrode lead-out part includes:

第一通孔140,所述第一通孔140贯穿有效谐振区外部的所述第一电极103的下层结构,暴露出所述第一电极103;第一导电互连层141,覆盖所述第一通孔140的内表面、及第一通孔140外周的所述承载衬底100的部分表面,与所述第一电极103连接;绝缘层160,覆盖所述第一导电互连层141和所述承载衬底100的表面;导电凸起142,设置于所述承载衬底100的表面、与所述第一导电互连层电141连接。A first through hole 140, the first through hole 140 penetrates the lower layer structure of the first electrode 103 outside the effective resonance area, exposing the first electrode 103; a first conductive interconnection layer 141, covering the first electrode 103 The inner surface of a through hole 140 and a part of the surface of the carrier substrate 100 around the first through hole 140 are connected to the first electrode 103 ; the insulating layer 160 covers the first conductive interconnect layer 141 and the first electrode 103 . The surface of the carrier substrate 100 ; the conductive bumps 142 are disposed on the surface of the carrier substrate 100 and electrically connected to the first conductive interconnect layer 141 .

所述第二电极引出部包括:The second electrode lead-out part includes:

第二通孔150,所述第二通孔150贯穿有效谐振区外部的所述第一电极103的下层结构,暴露出所述第一电极103;第二导电互连层151,覆盖所述第二通孔150的内表面、及第二通孔150外周的所述承载衬底100的部分表面,与所述第一电极103连接;绝缘层160,覆盖所述第二导电互连层151和所述承载衬底100的表面;第二导电凸起152,设置于所述承载衬底100的表面、与所述第二导电互连层电151连接。The second through hole 150, the second through hole 150 penetrates the lower layer structure of the first electrode 103 outside the effective resonance area, exposing the first electrode 103; the second conductive interconnection layer 151 covers the first electrode 103 The inner surface of the second through hole 150 and part of the surface of the carrier substrate 100 around the second through hole 150 are connected to the first electrode 103 ; the insulating layer 160 covers the second conductive interconnection layer 151 and The surface of the carrier substrate 100 ; the second conductive bumps 152 are disposed on the surface of the carrier substrate 100 and electrically connected to the second conductive interconnect layer 151 .

本实施例中,有效谐振区边界处设置有凸起40,所述凸起40设置于所述压电叠层结构上表面或下表面;或,所述凸起40部分设置于所述压电叠层结构的上表面,部分设置于所述压电叠层结构的下表面。In this embodiment, a protrusion 40 is provided at the boundary of the effective resonance region, and the protrusion 40 is provided on the upper surface or the lower surface of the piezoelectric laminated structure; or, the protrusion 40 is partially provided on the piezoelectric layered structure. The upper surface of the stacked structure is partially disposed on the lower surface of the piezoelectric stacked structure.

本实施例中,所述凸起40全部位于压电叠层结构的下表面。全部位于第一空腔110a所在的一侧。所述凸起40包围的区域为有效谐振区,凸起40外部为无效谐振区。所述有效谐振区内的所述第一电极103、压电层104和第二电极105在垂直于所述承载衬底100方向上相互重叠。在其他实施例中,所述凸起40可以全部位于压电叠层结构的上表面,背离第一空腔110a所在侧。所述凸起40还可以部分设置于所述压电叠层结构的上表面,部分设置于所述压电叠层结构的下表面。In this embodiment, the protrusions 40 are all located on the lower surface of the piezoelectric laminate structure. All are located on the side where the first cavity 110a is located. The area surrounded by the protrusions 40 is an effective resonance area, and the outside of the protrusions 40 is an ineffective resonance area. The first electrode 103 , the piezoelectric layer 104 and the second electrode 105 in the effective resonance region overlap each other in a direction perpendicular to the carrier substrate 100 . In other embodiments, the protrusions 40 may all be located on the upper surface of the piezoelectric laminate structure, away from the side where the first cavity 110a is located. The protrusions 40 may also be partially disposed on the upper surface of the piezoelectric laminated structure, and partially disposed on the lower surface of the piezoelectric laminated structure.

本实施例中,所述凸起40在承载衬底100上的投影围成封闭的环形,如封闭的不规则多边形、圆形或椭圆形。所述凸起40使其内部有效谐振区和凸起40所在的区域声阻抗失配,可以有效防止声波的横向泄露,提高谐振器的品质因数。在其他实施例中,所述凸起40在承载衬底100上的投影可以不是完全封闭的图形。应当理解,当凸起40在承载衬底100上的投影为封闭图形时,更有利于防止声波的横向泄露。In this embodiment, the projection of the protrusions 40 on the carrier substrate 100 forms a closed annular shape, such as a closed irregular polygon, circle or ellipse. The bulge 40 has its internal effective resonance area mismatched with the acoustic impedance of the area where the bulge 40 is located, which can effectively prevent lateral leakage of sound waves and improve the quality factor of the resonator. In other embodiments, the projection of the protrusions 40 on the carrier substrate 100 may not be a completely closed figure. It should be understood that when the projection of the protrusions 40 on the carrier substrate 100 is a closed figure, it is more beneficial to prevent the lateral leakage of sound waves.

所述凸起40的材料可以为导电材料也可以为介质材料,当凸起40的材料为导电材料时,可以和第一电极103或第二电极105的材料相同,当凸起40的材料为介质材料时,可以为氧化硅、氮化硅、氮氧化硅或碳氮化硅中的任意一种,但不限于以上材料。The material of the protrusion 40 can be a conductive material or a dielectric material. When the material of the protrusion 40 is a conductive material, it can be the same as the material of the first electrode 103 or the second electrode 105. When the material of the protrusion 40 is The dielectric material can be any one of silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, but is not limited to the above materials.

本实施例中,压电叠层结构的表面还包括第一沟槽130a和第二沟槽130b,第一沟槽130a位于压电叠层结构的下表面、所述第一空腔110a所在侧,贯穿所述第一电极103,环绕于所述凸起40所在区域的外周。第二沟槽130b位于压电叠层结构的上表面,贯穿所述第二电极105,环绕于所述凸起40所在区域的外周。第一沟槽130a的两个端部与第二沟槽130b的两个端部相对设置,使所述第一沟槽130a与所述第二沟槽130b在所述承载衬底100的投影的两个交界处相接或设有间隙。本实施例中,所述凸起40在压电层104的投影为封闭的多边形,第一沟槽130a和第二沟槽130b的内边缘沿着所述凸起40的外边界设置,即所述凸起40的外边界与第一沟槽130a和所述第二沟槽130b的内边缘重合。第一沟槽130a与第二沟槽130b在所述承载衬底100的投影为封闭的图形,与凸起40在承载衬底100的投影的图形形状一致,位于凸起40形成的投影的外周。In this embodiment, the surface of the piezoelectric laminate structure further includes a first trench 130a and a second trench 130b, and the first trench 130a is located on the lower surface of the piezoelectric laminate structure and on the side where the first cavity 110a is located. , runs through the first electrode 103 and surrounds the outer periphery of the area where the protrusion 40 is located. The second groove 130b is located on the upper surface of the piezoelectric stack, penetrates through the second electrode 105, and surrounds the outer periphery of the area where the protrusion 40 is located. The two ends of the first trench 130a and the two ends of the second trench 130b are disposed opposite to each other, so that the projections of the first trench 130a and the second trench 130b on the carrier substrate 100 are opposite to each other. The two junctions meet or have a gap. In this embodiment, the projection of the protrusion 40 on the piezoelectric layer 104 is a closed polygon, and the inner edges of the first groove 130a and the second groove 130b are arranged along the outer boundary of the protrusion 40, that is, all the The outer boundary of the protrusion 40 coincides with the inner edges of the first groove 130a and the second groove 130b. The projections of the first grooves 130a and the second grooves 130b on the carrier substrate 100 are closed figures, which are consistent with the projections of the projections 40 on the carrier substrate 100 , and are located at the outer periphery of the projections formed by the projections 40 . .

应当理解,凸起40为环形(当凸起40全部位于压电叠层结构的下表面或上表面时,凸起40构成环形;当凸起40位于压电叠层结构的两个表面时,两部分凸起的投影共同构成一个整体环形)。当凸起40全部位于压电叠层结构的上表面或下表面,第一沟槽130a环绕于部分所述凸起40的外周,第二沟槽130b环绕于剩余部分凸起40的外周(此时第二沟槽130b环绕于凸起40的外周意思为环绕于凸起40所述区域的压电叠层结构表面的外周,并不直接环绕于凸起40的外周)。当所述凸起40部分设置于所述压电叠层结构的上表面,部分设置于所述压电叠层结构的下表面时,第一沟槽130a可以环绕于位于压电叠层结构下表面的凸起40的外周,第二沟槽130b可以环绕于位于压电叠层结构上表面的凸起40的外周。但本发明并不限于此,只要第一沟槽130a和第二沟槽130b相互配合环绕于凸起40所在区域的外周即可。It should be understood that the protrusions 40 are annular (when the protrusions 40 are all located on the lower surface or the upper surface of the piezoelectric laminate structure, the protrusions 40 form an annular shape; when the protrusions 40 are located on both surfaces of the piezoelectric laminate structure, The projections of the two parts together form a whole ring). When the protrusions 40 are all located on the upper surface or the lower surface of the piezoelectric laminate structure, the first groove 130a surrounds part of the outer circumference of the protrusion 40, and the second groove 130b surrounds the remaining part of the outer circumference of the protrusion 40 (this When the second groove 130b surrounds the outer circumference of the protrusion 40, it means that the second groove 130b surrounds the outer circumference of the surface of the piezoelectric laminate structure in the region of the protrusion 40, and does not directly surround the outer circumference of the protrusion 40). When the protrusions 40 are partially disposed on the upper surface of the piezoelectric laminate structure and partially disposed on the lower surface of the piezoelectric laminate structure, the first groove 130a can surround the first groove 130a located under the piezoelectric laminate structure. On the outer circumference of the protrusion 40 on the surface, the second groove 130b may surround the outer circumference of the protrusion 40 on the upper surface of the piezoelectric laminate structure. However, the present invention is not limited to this, as long as the first groove 130a and the second groove 130b cooperate with each other to surround the outer circumference of the area where the protrusion 40 is located.

凸起40使凸起内部区域的声阻抗和凸起所在区域的声阻抗失配,界定了谐振器有效谐振区的边界。第一沟槽130a和第二沟槽130b分别将第一电极103和第二电极105隔断,使谐振器不能满足工作条件(工作条件为第一电极103、压电层104和第二电极105在厚度方向上相互重叠),进一步界定了谐振器的有效谐振区的边界。凸起40通过质量块的添加使声阻抗失配,第一沟槽130a和第二沟槽130b通过使电极端面和空气接触,使声阻抗失配,两者均起到阻止横波泄露的问题,提高了谐振器的Q值。当然,在其他实施例中,也可以只单独设置第一沟槽130a或第二沟槽130b,由于第一电极103和第二电极105需要引入电信号,第一沟槽130a或第二沟槽130b不适宜形成封闭的环形,此时第一沟槽130a或第二沟槽130b不能完全包围凸起40所在的区域。可以将第一沟槽130a或第二沟槽130b构成接近封闭的环形,非封闭的区域用于引入电信号。这种设置方式可以简化工艺流程,降低谐振器成本。The bump 40 mismatches the acoustic impedance of the region inside the bump with the acoustic impedance of the region where the bump is located, defining the boundary of the effective resonant region of the resonator. The first trench 130a and the second trench 130b separate the first electrode 103 and the second electrode 105 respectively, so that the resonator cannot meet the working conditions (the working condition is that the first electrode 103, the piezoelectric layer 104 and the second electrode 105 are overlapping each other in the thickness direction), which further defines the boundary of the effective resonance region of the resonator. The protrusion 40 makes the acoustic impedance mismatch through the addition of the mass, and the first groove 130a and the second groove 130b make the acoustic impedance mismatch by contacting the electrode end face with the air, both of which play a role in preventing the leakage of the shear wave, Improves the Q of the resonator. Of course, in other embodiments, only the first trench 130a or the second trench 130b may be provided alone. Since the first electrode 103 and the second electrode 105 need to introduce electrical signals, the first trench 130a or the second trench 130b The 130b is not suitable to form a closed ring, and at this time, the first groove 130a or the second groove 130b cannot completely surround the area where the protrusion 40 is located. The first groove 130a or the second groove 130b can be formed into a nearly closed ring, and the non-closed area is used for introducing electrical signals. This arrangement simplifies the process flow and reduces the cost of the resonator.

本实施例中,还包括导电互连结构120,导电互连结构120包括两部分,一部分设置于第二沟槽130b的外部区域,连接第一电极103和第二电极105,通过第一电极103与第一电极引出部电连接。导电互连结构120的另一部分设置于第一沟槽130a的外部区域,连接第一电极103和第二电极105,通过第一电极103与第二电极引出部电连接。两部分导电互连结构120均设有覆盖第二电极105部分表面的区域,此区域增大了与第二电极105的接触面积,减少了接触阻抗,能够防止电流过大引起的局部高温。In this embodiment, the conductive interconnect structure 120 is further included. The conductive interconnect structure 120 includes two parts. It is electrically connected to the first electrode lead-out portion. The other part of the conductive interconnect structure 120 is disposed in the outer region of the first trench 130a, connects the first electrode 103 and the second electrode 105, and is electrically connected to the lead-out portion of the second electrode through the first electrode 103. The two parts of the conductive interconnect structure 120 are provided with an area covering part of the surface of the second electrode 105 , this area increases the contact area with the second electrode 105 , reduces the contact resistance, and can prevent local high temperature caused by excessive current.

需要说明的是,第二电极引出部并不直接与第二电极电连接,而是连接于有效谐振区外部的第一电极,通过导电互连结构120与有效谐振区的第二电极电连接。可以看出,第一电极引出部和第二电极引出部在结构上一致,只是设置的位置不同,第一电极引出部与有效谐振区内部的第一电极电连接,给有效谐振区内部的第一电极供电,第一电极引出部通过有效谐振区外部的第一电极和导电互连结构120与有效谐振区外部的第二电极电连接,并不连接于有效谐振区内部的第二电极。同理,第二电极引出部连接于有效谐振区外部的第一电极和有效谐振区内部的第二电极,实现对有效谐振区内部的第二电极供电。It should be noted that the second electrode lead-out portion is not directly electrically connected to the second electrode, but is connected to the first electrode outside the effective resonance area, and is electrically connected to the second electrode of the effective resonance area through the conductive interconnect structure 120 . It can be seen that the first electrode lead-out part and the second electrode lead-out part are the same in structure, but the positions are different. An electrode is powered, and the first electrode lead-out portion is electrically connected to the second electrode outside the effective resonance region through the first electrode outside the effective resonance region and the conductive interconnect structure 120, and is not connected to the second electrode inside the effective resonance region. Similarly, the second electrode lead-out portion is connected to the first electrode outside the effective resonance area and the second electrode inside the effective resonance area, so as to supply power to the second electrode inside the effective resonance area.

实施例2Example 2

实施例2提供了一种薄膜体声波谐振器的制造方法,包括以下步骤:Embodiment 2 provides a method for manufacturing a thin film bulk acoustic resonator, comprising the following steps:

S01:提供临时衬底;S01: Provide a temporary substrate;

S02:在所述临时衬底上形成压电叠层结构,所述压电叠层结构包括由下至上依次设置的第二电极、压电层、第一电极;S02: forming a piezoelectric stack structure on the temporary substrate, where the piezoelectric stack structure includes a second electrode, a piezoelectric layer, and a first electrode sequentially arranged from bottom to top;

S03:形成介质层,覆盖所述压电叠层结构;S03: forming a dielectric layer to cover the piezoelectric laminated structure;

S04:图形化所述介质层,形成第一空腔,所述第一空腔贯穿所述介质层;S04: pattern the dielectric layer to form a first cavity, and the first cavity penetrates the dielectric layer;

S05:提供承载衬底,所述承载基底包括第一半导体层和第一器件层,所述承载衬底的第一表面嵌入有第一微器件,所述第一器件层所在侧为所述承载基底的第一表面所在侧;S05: Provide a carrier substrate, the carrier substrate includes a first semiconductor layer and a first device layer, a first micro-device is embedded in a first surface of the carrier substrate, and the side where the first device layer is located is the carrier the side where the first surface of the substrate is located;

S06:键合所述承载衬底至所述介质层上、覆盖所述第一空腔,并使所述第一表面朝向所述第一空腔;S06: bond the carrier substrate to the dielectric layer, cover the first cavity, and make the first surface face the first cavity;

S07:去除所述临时衬底;S07: remove the temporary substrate;

S08:形成第一电连接结构,将所述第一微器件与外部信号电连接。S08: Form a first electrical connection structure to electrically connect the first micro device with an external signal.

需要说明的是,S0N并不用于限定步骤的先后顺序。图2至图11示出了根据本发明实施例2的一种薄膜压电声波谐振器的制造方法不同阶段的结构示意图,请参考图2至图11,详细说明各步骤。It should be noted that the SON is not used to limit the sequence of steps. FIGS. 2 to 11 are schematic structural diagrams of different stages of a method for manufacturing a thin-film piezoelectric acoustic resonator according to Embodiment 2 of the present invention. Please refer to FIGS. 2 to 11 for detailed description of each step.

参考图2,执行步骤S01:提供临时衬底300。Referring to FIG. 2 , step S01 is performed: a temporary substrate 300 is provided.

临时衬底300可以是以下所提到的材料中的至少一种:硅(Si)、锗(Ge)、锗硅(SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V化合物半导体,也可为氧化铝等的陶瓷基底、石英或玻璃基底等。The temporary substrate 300 may be at least one of the following mentioned materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and may also be ceramic substrates such as alumina, quartz or glass substrates, and the like.

参考图3,执行步骤S02:在所述临时衬底300上形成压电叠层结构,所述压电叠层结构包括由下至上依次设置的第二电极105、压电层104、第一电极103。Referring to FIG. 3 , step S02 is performed: forming a piezoelectric stack structure on the temporary substrate 300 , and the piezoelectric stack structure includes a second electrode 105 , a piezoelectric layer 104 , and a first electrode sequentially arranged from bottom to top 103.

第二电极105和第一电极103的材料可以使用本领域技术人员熟知的任意合适的导电材料或半导体材料,其中,导电材料可以为具有导电性能的金属材料,例如,由钼(Mo)、铝(Al)、铜(Cu)、钨(W)、钽(Ta)、铂(Pt)、钌(Ru)、铑(Rh)、铱(Ir)、铬(Cr)、钛(Ti)、金(Au)、锇(Os)、铼(Re)、钯(Pd)等金属中一种制成或由上述金属形成的叠层制成,半导体材料例如是Si、Ge、SiGe、SiC、SiGeC等。可以通过磁控溅射、蒸镀等物理气相沉积或者化学气相沉积方法形成第二电极105和第一电极103。压电层104的材料可以使用氮化铝(AlN)、氧化锌(ZnO)、锆钛酸铅(PZT)、铌酸锂(LiNbO3)、石英(Quartz)、铌酸钾(KNbO3)或钽酸锂(LiTaO3)等具有纤锌矿型结晶结构的压电材料及它们的组合。当压电层104包括氮化铝(AlN)时,压电层104还可包括稀土金属,例如钪(Sc)、铒(Er)、钇(Y)和镧(La)中的至少一种。此外,当压电层104包括氮化铝(AlN)时,压电层104还可包括过渡金属,例如锆(Zr)、钛(Ti)、锰(Mn)和铪(Hf)中的至少一种。可以使用化学气相沉积、物理气相沉积或原子层沉积等本领域技术人员熟知的任何适合的方法沉积形成压电层104。可选的,本实施例中,第二电极105和第一电极103由金属钼(Mo)制成,压电层104由氮化铝(AlN)制成。The material of the second electrode 105 and the first electrode 103 can be any suitable conductive material or semiconductor material known to those skilled in the art, wherein the conductive material can be a metal material with conductive properties, such as molybdenum (Mo), aluminum (Al), Copper (Cu), Tungsten (W), Tantalum (Ta), Platinum (Pt), Ruthenium (Ru), Rhodium (Rh), Iridium (Ir), Chromium (Cr), Titanium (Ti), Gold (Au), osmium (Os), rhenium (Re), palladium (Pd) and other metals, or a laminate of the above metals, and semiconductor materials such as Si, Ge, SiGe, SiC, SiGeC, etc. . The second electrode 105 and the first electrode 103 may be formed by physical vapor deposition such as magnetron sputtering, evaporation, or chemical vapor deposition. The piezoelectric layer 104 can be made of aluminum nitride (AlN), zinc oxide (ZnO), lead zirconate titanate (PZT), lithium niobate (LiNbO3), quartz (Quartz), potassium niobate (KNbO3) or tantalic acid Piezoelectric materials having a wurtzite crystal structure, such as lithium (LiTaO3), and combinations thereof. When the piezoelectric layer 104 includes aluminum nitride (AlN), the piezoelectric layer 104 may further include a rare earth metal such as at least one of scandium (Sc), erbium (Er), yttrium (Y), and lanthanum (La). In addition, when the piezoelectric layer 104 includes aluminum nitride (AlN), the piezoelectric layer 104 may further include a transition metal such as at least one of zirconium (Zr), titanium (Ti), manganese (Mn), and hafnium (Hf). kind. The piezoelectric layer 104 may be deposited using any suitable method known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Optionally, in this embodiment, the second electrode 105 and the first electrode 103 are made of metal molybdenum (Mo), and the piezoelectric layer 104 is made of aluminum nitride (AlN).

参考图4,执行步骤S03:形成介质层102,覆盖所述压电叠层结构。Referring to FIG. 4 , step S03 is performed: forming a dielectric layer 102 to cover the piezoelectric stack structure.

通过物理气相沉积或化学气相沉积形成介质层102。介质层102的材料可以是任意适合的介电材料,包括但不限于氧化硅、氮化硅、氮氧化硅、碳氮化硅等材料中的至少一种。The dielectric layer 102 is formed by physical vapor deposition or chemical vapor deposition. The material of the dielectric layer 102 may be any suitable dielectric material, including but not limited to at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride and other materials.

参考图5,执行步骤S05:图形化所述介质层102,形成第一空腔110a,所述第一空腔110a贯穿所述介质层102。Referring to FIG. 5 , step S05 is performed: the dielectric layer 102 is patterned to form a first cavity 110 a , and the first cavity 110 a penetrates the dielectric layer 102 .

通过刻蚀工艺刻蚀介质层102形成第一空腔110a,并暴露出底部的第一电极层103。该刻蚀工艺可以是湿法刻蚀或者干法刻蚀工艺,干法刻蚀包括但不限于反应离子刻蚀(RIE)、离子束刻蚀、等离子体刻蚀。第一空腔110a的深度和形状均取决于待制造的体声波谐振器所需空腔的深度和形状,即可以通过形成介质层102的厚度来确定第一空腔110a的深度。第一空腔110a底面的形状可以为矩形或是矩形以外的多边形,例如五边形、六边形、八边形等,也可以为圆形或椭圆形。The first cavity 110a is formed by etching the dielectric layer 102 through an etching process, and the first electrode layer 103 at the bottom is exposed. The etching process may be wet etching or dry etching, and dry etching includes but is not limited to reactive ion etching (RIE), ion beam etching, and plasma etching. The depth and shape of the first cavity 110a depend on the depth and shape of the cavity required for the bulk acoustic wave resonator to be fabricated, that is, the depth of the first cavity 110a can be determined by forming the thickness of the dielectric layer 102 . The shape of the bottom surface of the first cavity 110a may be a rectangle or a polygon other than a rectangle, such as a pentagon, a hexagon, an octagon, etc., or a circle or an ellipse.

参考图6,执行步骤S05:提供承载衬底,所述承载基底包括第一半导体层100A和第一器件层100B,所述承载衬底的第一表面嵌入有第一微器件1000,所述第一器件层100B所在侧为所述承载基底的第一表面所在侧。第一半导体层100A的材质、第一器件层100B的材质,第一微器件1000的种类及与承载衬底的结构关系参照实施例1的相关描述,此处不再赘述。Referring to FIG. 6 , step S05 is performed: a carrier substrate is provided, the carrier substrate includes a first semiconductor layer 100A and a first device layer 100B, a first surface of the carrier substrate is embedded with a first micro-device 1000 , and the first micro-device 1000 is embedded in the first surface of the carrier substrate. The side where a device layer 100B is located is the side where the first surface of the carrier substrate is located. For the material of the first semiconductor layer 100A, the material of the first device layer 100B, the type of the first micro-device 1000 and the structural relationship with the carrier substrate, refer to the relevant description of Embodiment 1, and will not be repeated here.

参考图7,执行步骤S06:键合所述承载衬底至所述介质层102上、覆盖所述第一空腔110a,并使所述第一表面朝向所述第一空腔110a。介质层的材料以及介质层与承载衬底的键合方式参照实施例1的相关描述。Referring to FIG. 7 , step S06 is performed: bonding the carrier substrate to the dielectric layer 102 , covering the first cavity 110 a , and making the first surface face the first cavity 110 a . For the material of the dielectric layer and the bonding method between the dielectric layer and the carrier substrate, refer to the relevant description in Embodiment 1.

参考图8,执行步骤S07:去除所述临时衬底。去除临时衬底的方法可以采用机械研磨。Referring to FIG. 8 , step S07 is performed: removing the temporary substrate. The method of removing the temporary substrate may employ mechanical grinding.

参考图9和图10,本实施例中,在形成第一电连接结构,连接所述第一微器件之前还还包括:在所述压电叠层结构上形成接合层106,所述接合层106围成第二空腔110b,所述第二空腔110b暴露出所述压电叠层结构的表面,所述第二空腔110b位于所述第一空腔110a上方。提供封盖基板,所述封盖基板包括第二半导体层200A和第二器件层200B,所述承盖基板的第一表面嵌入有第二微器件2000,所述第二器件层200B所在侧为所述封盖基板的第一表面所在侧。将所述封盖基板设置于所述接合层106上、覆盖所述第二空腔110b,并使所述封盖基板的第一表面朝向所述第二空腔110b。结合层106的材料、第二半导体层200A的材质、第二器件层200B的材质,第二微器件2000的种类及与封盖基板的结构关系参照实施例1的相关描述,此处不再赘述。Referring to FIG. 9 and FIG. 10 , in this embodiment, before forming the first electrical connection structure and connecting the first micro-device, it further includes: forming a bonding layer 106 on the piezoelectric stack structure, the bonding layer 106 encloses a second cavity 110b, the second cavity 110b exposes the surface of the piezoelectric laminate structure, and the second cavity 110b is located above the first cavity 110a. A cover substrate is provided, the cover substrate includes a second semiconductor layer 200A and a second device layer 200B, a second micro device 2000 is embedded in the first surface of the cover substrate, and the side where the second device layer 200B is located is the side where the first surface of the cover substrate is located. The capping substrate is disposed on the bonding layer 106 to cover the second cavity 110b, and the first surface of the capping substrate faces the second cavity 110b. The material of the bonding layer 106 , the material of the second semiconductor layer 200A, the material of the second device layer 200B, the type of the second micro-device 2000 and the structural relationship with the capping substrate refer to the relevant description of Embodiment 1, and will not be repeated here. .

参考图11,执行步骤S08:形成第一电连接结构,将所述第一微器件与外部信号电连接。本实施例例中还包括:形成第二电连接结构,将所述第二微器件与外部信号电连接。第一电连接结构和第二电连接结构分别为第一导电插塞1001和第二导电插塞2001。本实施例中,形成第一导电插塞1001和第二导电插塞2001包括:从所述承载衬底侧形成贯穿所述承载衬底的第一通孔(图中未示出)以及贯穿所述承载衬底及所述承载衬底上方结构(本实施例中上方结构包括介质层102,压电叠层结构、接合层106以及部分第二器件层200B)的第二通孔(图中未示出),所述第一通孔暴露出所述第一微器件1000,所述第二通孔暴露出所述第二微器件2000,在所述第一通孔1000和所述第二通孔2000中形成导电材料,以形成所述第一导电插塞1001及所述第二导电插塞2001。形成第一通孔和第二通孔可以采用干法刻蚀工艺,在第一通孔和第二通孔中形成导电材料可以采用电镀或化镀工艺。Referring to FIG. 11 , step S08 is performed: forming a first electrical connection structure to electrically connect the first micro device with an external signal. This embodiment further includes: forming a second electrical connection structure to electrically connect the second micro device with an external signal. The first electrical connection structure and the second electrical connection structure are the first conductive plug 1001 and the second conductive plug 2001, respectively. In this embodiment, forming the first conductive plug 1001 and the second conductive plug 2001 includes: forming a first through hole (not shown in the figure) penetrating the carrier substrate from the side of the carrier substrate and penetrating the carrier substrate. The second through hole (not shown in the figure) of the carrier substrate and the upper structure of the carrier substrate (in this embodiment, the upper structure includes the dielectric layer 102, the piezoelectric stack structure, the bonding layer 106 and part of the second device layer 200B) shown), the first through hole exposes the first micro device 1000, the second through hole exposes the second micro device 2000, and the first through hole 1000 and the second through hole expose the second micro device 2000. Conductive material is formed in the hole 2000 to form the first conductive plug 1001 and the second conductive plug 2001 . The first through hole and the second through hole may be formed by a dry etching process, and the conductive material in the first through hole and the second through hole may be formed by an electroplating or electroless plating process.

在另一个实施例中,形成第一导电插塞1001和第二导电插塞2001包括:从所述封盖基板侧形成贯穿所述封盖基板的第三通孔以及贯穿所述封盖基板及所述封盖基板下方结构的第四通孔,所述第三通孔暴露出所述第二微器件,所述第四通孔暴露出所述第一微器件,在所述第三通孔和所述第四通孔中形成导电材料,以形成所述第二导电插塞及所述第一导电插塞。In another embodiment, forming the first conductive plug 1001 and the second conductive plug 2001 includes: forming a third through hole penetrating the capping substrate from a side of the capping substrate and penetrating the capping substrate and the fourth through hole of the structure under the cover substrate, the third through hole exposes the second micro device, the fourth through hole exposes the first micro device, and the third through hole exposes the first micro device and forming a conductive material in the fourth through hole to form the second conductive plug and the first conductive plug.

以上两导电插塞均形成于谐振器的同侧(承载衬底所在侧或封盖基板所在侧),这样设置的原因参照实施例1的相关描述。导电插塞形成于承载衬底所在侧之前,还包括以封盖基板为支撑,减薄承载衬底;导电插塞形成于封盖基板所在侧之前,还包括以承载衬底为支撑,减薄封盖基板。The above two conductive plugs are formed on the same side of the resonator (the side where the carrier substrate is located or the side where the cover substrate is located). The conductive plug is formed before the side where the carrier substrate is located, and further includes using the cover substrate as a support to reduce the thickness of the carrier substrate; the conductive plug is formed before the side where the cover substrate is located, and further includes using the carrier substrate as a support to reduce the thickness Cover the substrate.

本实施例中,还包括形成第一电极引出部和第二电极引出部,所述第一电极引出部连接于所述第一电极103,所述第二电极引出部连接于所述第二电极105,所述第一电极引出部、所述第二电极引出部位于所述承载衬底所在侧。当第一导电插塞及所述第二导电插塞位于封盖基板所在侧时,第一电极引出部、所述第二电极引出部优选方案中也位于封盖基板所在侧。In this embodiment, it also includes forming a first electrode lead-out portion and a second electrode lead-out portion, the first electrode lead-out portion is connected to the first electrode 103 , and the second electrode lead-out portion is connected to the second electrode 105. The first electrode lead-out portion and the second electrode lead-out portion are located on the side where the carrier substrate is located. When the first conductive plug and the second conductive plug are located on the side where the cover substrate is located, the first electrode lead-out portion and the second electrode lead-out portion are preferably also located on the side where the cover substrate is located.

其中形成所述第一电极引出部包括:Wherein forming the first electrode lead-out portion includes:

通过刻蚀工艺形成贯穿所述第一电极103下层结构的通孔,所述通孔暴露出所述第一电极103,在通孔中通过电镀工艺或物理气相沉积工艺形成第一导电互连层141,所述第一导电互连层141覆盖所述通孔的内表面、及所述通孔外周的所述承载衬底100的部分表面,与所述第一电极103连接;在所述第一导电互连层141表面通过沉积工艺形成绝缘层160;在所述承载衬底的表面形成第一导电凸起142,所述第一导电凸起142与所述第一导电互连层141电连接。A through hole is formed through the underlying structure of the first electrode 103 through an etching process, the through hole exposes the first electrode 103, and a first conductive interconnect layer is formed in the through hole through an electroplating process or a physical vapor deposition process 141, the first conductive interconnect layer 141 covers the inner surface of the through hole and a part of the surface of the carrier substrate 100 around the through hole, and is connected to the first electrode 103; An insulating layer 160 is formed on the surface of a conductive interconnect layer 141 by a deposition process; first conductive bumps 142 are formed on the surface of the carrier substrate, and the first conductive bumps 142 are electrically connected to the first conductive interconnect layer 141 connect.

形成所述第二电极引出部包括:Forming the second electrode lead-out portion includes:

通过刻蚀工艺形成贯穿所述第一电极103下层结构的通孔,所述通孔暴露出所述第二电极105,在通孔中通过沉积工艺或电镀工艺形成第二导电互连层151,所述第二导电互连层151覆盖通孔内表面、及通孔外周的所述承载衬底的部分表面,与所述第二电极105连接;在所述第二导电互连层151表面通过沉积工艺形成绝缘层160;在所述承载衬底100的表面形成第二导电凸起152,所述第二导电凸起152与所述第二导电互连层151电连接。A through hole is formed through the underlying structure of the first electrode 103 through an etching process, the through hole exposes the second electrode 105, a second conductive interconnect layer 151 is formed in the through hole through a deposition process or an electroplating process, The second conductive interconnect layer 151 covers the inner surface of the through hole and part of the surface of the carrier substrate around the through hole, and is connected to the second electrode 105; A deposition process forms an insulating layer 160 ; a second conductive bump 152 is formed on the surface of the carrier substrate 100 , and the second conductive bump 152 is electrically connected to the second conductive interconnect layer 151 .

需要说明的是,本说明书中的各个实施例均采用相关的方式描述,各个实施例之间相同相似的部分互相参见即可,每个实施例重点说明的都是与其他实施例的不同之处。尤其,对于方法实施例而言,由于其基本相似于结构实施例,所以描述的比较简单,相关之处参见方法实施例的部分说明即可。It should be noted that each embodiment in this specification is described in a related manner, and the same and similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. . In particular, for the method embodiments, since they are basically similar to the structural embodiments, the description is relatively simple, and reference may be made to some descriptions of the method embodiments for related parts.

上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure all belong to the protection scope of the claims.

Claims (26)

1. A thin film bulk acoustic resonator, comprising:
the device comprises a bearing substrate, a first substrate and a second substrate, wherein the bearing substrate comprises a first semiconductor layer and a first device layer;
a first micro device embedded in the carrier substrate, and at least a portion of the first micro device being located in the first device layer;
the dielectric layer is bonded on the first device layer, the dielectric layer surrounds a first cavity, and the surface of the bearing substrate is exposed out of the first cavity;
the piezoelectric laminated structure covers the first cavity and comprises a first electrode, a piezoelectric layer and a second electrode which are sequentially laminated from bottom to top;
and the first electric connection structure is connected with the first micro device and electrically leads out the first micro device.
2. The thin film bulk acoustic resonator of claim 1, further comprising:
the junction layer is arranged above the piezoelectric laminated structure, a second cavity is surrounded by the junction layer, the surface of the piezoelectric laminated structure is exposed out of the second cavity, and the projection of the second cavity and the projection of the first cavity on the piezoelectric laminated structure are overlapped;
and the sealing cover substrate is arranged on the bonding layer and covers the second cavity.
3. The thin film bulk acoustic resonator of claim 2, wherein the capping substrate comprises a second semiconductor layer and a second device layer, the second device layer being adjacent to a side of the second cavity; further comprising:
a second micro device embedded in the capping substrate, at least a portion of the second micro device being located in the second device layer;
and the second electric connection structure is connected with the second micro device and electrically leads out the second micro device.
4. The thin film bulk acoustic resonator of claim 1, wherein the first electrical connection structure comprises:
a first conductive plug extending from a bottom surface of the carrier substrate to the first micro device or; the first conductive plug extends from the top surface of the capping substrate to the first micro device.
5. The film bulk acoustic resonator of claim 3, wherein the second electrical connection structure comprises:
a second conductive plug extending from a bottom surface of the carrier substrate to the first micro device or; the second conductive plug extends from the top surface of the capping substrate to the second micro device.
6. The thin film bulk acoustic resonator of claim 3, further comprising a third electrical connection structure connecting the first micro device and the second micro device.
7. The thin film bulk acoustic resonator of claim 3, wherein the first micro device and/or the second micro device comprises:
a diode, a triode, a MOS transistor, an electrostatic discharge protection device, a resistor, a capacitor or an inductor.
8. The thin film bulk acoustic resonator of claim 1, wherein the material of the first device layer comprises: silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
9. The film bulk acoustic resonator of claim 1, wherein the material of the dielectric layer comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or ethyl silicate.
10. The film bulk acoustic resonator of claim 1, wherein the dielectric layer and the first device layer are made of the same material, and the bonding manner comprises: the atoms are bonded.
11. The film bulk acoustic resonator of claim 1, further comprising a bonding layer disposed between the dielectric layer and the carrier substrate.
12. The film bulk acoustic resonator of claim 11, wherein the bonding layer comprises a material comprising: silicon oxide, silicon nitride, polysilicon, ethyl silicate, or an organic cured film.
13. The film bulk acoustic resonator of claim 12, wherein the dielectric layer and the bonding layer are of the same material.
14. The thin film bulk acoustic resonator of claim 1, further comprising:
a first trench located inside an area surrounded by the first cavity, penetrating the first electrode, or penetrating the first electrode and the piezoelectric layer;
the second groove is positioned in an area enclosed by the second cavity, is arranged opposite to the first groove in the transverse direction, and penetrates through the second electrode or penetrates through the second electrode and the piezoelectric layer;
the first groove and the second groove are connected or provided with a gap at two junctions of the projection of the bearing substrate.
15. The film bulk acoustic resonator according to claim 1, wherein an area where the first electrode, the piezoelectric layer, and the second electrode overlap with each other in a direction perpendicular to the carrier substrate is an effective resonance area, a boundary of the effective resonance area is located in an area surrounded by the first cavity, a protrusion is provided at the boundary of the effective resonance area, and the protrusion is provided on an upper surface or a lower surface of the piezoelectric laminated structure; or the like, or, alternatively,
the protruding part is arranged on the upper surface of the piezoelectric laminated structure, and the part is arranged on the lower surface of the piezoelectric laminated structure.
16. A method of manufacturing a film bulk acoustic resonator, comprising:
providing a temporary substrate;
forming a piezoelectric laminated structure on the temporary substrate, wherein the piezoelectric laminated structure comprises a second electrode, a piezoelectric layer and a first electrode which are sequentially arranged from bottom to top;
forming a dielectric layer to cover the piezoelectric laminated structure;
patterning the dielectric layer to form a first cavity, wherein the first cavity penetrates through the dielectric layer;
providing a carrier substrate, wherein the carrier substrate comprises a first semiconductor layer and a first device layer, a first micro device is embedded in the carrier substrate, and at least part of the first micro device is positioned in the first device layer;
bonding the first device layer of the bearing substrate to the dielectric layer and covering the first cavity;
removing the temporary substrate;
and forming a first electric connection structure to lead out the first micro device electrically.
17. The method of manufacturing a thin film bulk acoustic resonator according to claim 16, further comprising, after removing the temporary substrate and before forming the first electrical connection structure:
forming a bonding layer on the piezoelectric laminated structure, wherein the bonding layer surrounds a second cavity, the second cavity exposes the surface of the piezoelectric laminated structure, and the second cavity is positioned above the first cavity;
and providing a cover substrate, arranging the cover substrate on the junction layer, covering the second cavity, and enabling the first surface of the cover substrate to face the second cavity.
18. The method of manufacturing a thin film bulk acoustic resonator according to claim 17, wherein the step of embedding a second micro device in the first surface of the cover substrate and the step of disposing the cover substrate on the bonding layer further comprises: and forming a second electric connection structure for electrically connecting the second micro device with an external signal.
19. The method of manufacturing a thin film bulk acoustic resonator according to claim 18, wherein the first electrical connection structure is a first conductive plug, the second electrical connection structure is a second conductive plug, and forming the first electrical connection structure and the second electrical connection structure includes:
forming a first through hole penetrating through the bearing substrate and a second through hole penetrating through the bearing substrate and the bearing substrate upper structure from the bearing substrate side, wherein the first through hole exposes the first micro device, the second through hole exposes the second micro device, and a conductive material is formed in the first through hole and the second through hole to form the first conductive plug and the second conductive plug.
20. The method of manufacturing a thin film bulk acoustic resonator according to claim 18, wherein the first electrical connection structure is a first conductive plug, the second electrical connection structure is a second conductive plug, and forming the first electrical connection structure and the second electrical connection structure includes:
and forming a third through hole penetrating through the cover substrate and a fourth through hole penetrating through the cover substrate and the structure below the cover substrate from the side of the cover substrate, wherein the third through hole exposes the second micro device, the fourth through hole exposes the first micro device, and a conductive material is formed in the third through hole and the fourth through hole to form the second conductive plug and the first conductive plug.
21. The method of manufacturing a thin film bulk acoustic resonator according to claim 19 or 20, further comprising: and forming a first electrode leading-out part and a second electrode leading-out part, wherein the first electrode leading-out part is connected with the first electrode, the second electrode leading-out part is connected with the second electrode, and leading-out ends of the first electrode leading-out part, the second conductive plug and the first conductive plug are all positioned on the side where the cover substrate is positioned or the side where the bearing substrate is positioned.
22. The method of manufacturing a thin film bulk acoustic resonator according to claim 16, further comprising, after forming the first cavity and before bonding the carrier substrate:
patterning the first electrode, or the first electrode and the piezoelectric layer, to form part of the boundary of the effective resonance region;
after removing the temporary substrate, the method further comprises:
patterning the second electrode, or the second electrode and the piezoelectric layer, to form another part of a boundary of an effective resonance area, where the boundary of the effective resonance area is located in an area where projections of the first cavity and the second cavity overlap in the direction of the piezoelectric layer.
23. The method of manufacturing a thin film bulk acoustic resonator of claim 18, wherein the first micro device and/or the second micro device comprises:
a diode, a triode, a MOS transistor, an electrostatic discharge protection device, a resistor, a capacitor or an inductor.
24. The method of manufacturing a thin film bulk acoustic resonator according to claim 16, wherein the material of the first device layer includes: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride.
25. The method of manufacturing a thin film bulk acoustic resonator according to claim 24, wherein a material of the dielectric layer is the same as a material of the first device layer, and bonding the carrier substrate on the dielectric layer comprises: bonded directly through an atomic bond.
26. The method of manufacturing a thin film bulk acoustic resonator according to claim 16, wherein bonding the carrier substrate on the dielectric layer comprises:
and forming a bonding layer on the surface of the dielectric layer, and bonding the dielectric layer and the bearing substrate through the bonding layer, wherein the dielectric layer and the bonding layer are made of the same material.
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113395050A (en) * 2021-03-30 2021-09-14 台湾晶技股份有限公司 Crystal oscillator packaging structure
WO2021189965A1 (en) * 2020-03-27 2021-09-30 中芯集成电路(宁波)有限公司 Film bulk acoustic resonator and manufacturing method therefor
WO2021232763A1 (en) * 2020-05-20 2021-11-25 中芯集成电路(宁波)有限公司上海分公司 Film bulk acoustic resonator and manufacturing method therefor
CN114094970A (en) * 2022-01-20 2022-02-25 深圳新声半导体有限公司 Method for manufacturing film bulk acoustic wave resonator and resonator
CN114684778A (en) * 2020-12-31 2022-07-01 中芯集成电路(宁波)有限公司上海分公司 MEMS device and manufacturing method thereof
CN114955976A (en) * 2021-02-26 2022-08-30 中芯集成电路(宁波)有限公司上海分公司 MEMS device and manufacturing method thereof
US11463070B2 (en) 2022-01-18 2022-10-04 Shenzhen Newsonic Technologies Co., Ltd. FBAR structure and manufacturing method of same
CN116599481A (en) * 2023-06-08 2023-08-15 中国科学院上海微系统与信息技术研究所 Preparation method of acoustic wave resonator and acoustic wave resonator
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* Cited by examiner, † Cited by third party
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080051039A1 (en) * 2006-08-25 2008-02-28 Matsushita Electric Industrial Co., Ltd. Film bulkacoustic wave resonator and method for manufacturing the same
US20130147319A1 (en) * 2011-12-12 2013-06-13 International Business Machines Corporation Loading element of a film bulk acoustic resonator
CN106849897A (en) * 2015-12-03 2017-06-13 上海珏芯光电科技有限公司 FBAR and its manufacture method
CN106877836A (en) * 2015-12-14 2017-06-20 中芯国际集成电路制造(上海)有限公司 A kind of FBAR and its manufacture method and electronic installation
CN107947751A (en) * 2016-10-12 2018-04-20 三星电机株式会社 Bulk acoustic wave resonator and its manufacture method
CN108075743A (en) * 2016-11-15 2018-05-25 环球通信半导体有限责任公司 The film bulk acoustic resonator inhibited with stray resonance
CN108336019A (en) * 2017-09-30 2018-07-27 中芯集成电路(宁波)有限公司 The method and wafer level packaging structure of conductive plunger are formed in a kind of wafer-level packaging
US20180358406A1 (en) * 2015-12-24 2018-12-13 Intel Corporation Techniques for integrating three-dimensional islands for radio frequency (rf) circuits
CN109660227A (en) * 2018-12-24 2019-04-19 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 Thin-film bulk acoustic wave filter and its packaging method
CN110401428A (en) * 2018-04-25 2019-11-01 上海珏芯光电科技有限公司 Thin film bulk acoustic wave resonator and its manufacturing method
CN110829997A (en) * 2018-08-07 2020-02-21 上海珏芯光电科技有限公司 Film bulk acoustic resonator and method for manufacturing the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11057017B2 (en) * 2017-08-17 2021-07-06 Samsung Electro-Mechanics Co., Ltd Bulk-acoustic wave resonator
CN110474616A (en) * 2019-08-29 2019-11-19 华南理工大学 A kind of air-gap type thin film bulk acoustic wave resonator and preparation method thereof
CN112039484B (en) * 2020-03-27 2024-12-10 中芯集成电路(宁波)有限公司 A thin film bulk acoustic wave resonator and a method for manufacturing the same

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080051039A1 (en) * 2006-08-25 2008-02-28 Matsushita Electric Industrial Co., Ltd. Film bulkacoustic wave resonator and method for manufacturing the same
US20130147319A1 (en) * 2011-12-12 2013-06-13 International Business Machines Corporation Loading element of a film bulk acoustic resonator
CN106849897A (en) * 2015-12-03 2017-06-13 上海珏芯光电科技有限公司 FBAR and its manufacture method
CN106877836A (en) * 2015-12-14 2017-06-20 中芯国际集成电路制造(上海)有限公司 A kind of FBAR and its manufacture method and electronic installation
US20180358406A1 (en) * 2015-12-24 2018-12-13 Intel Corporation Techniques for integrating three-dimensional islands for radio frequency (rf) circuits
CN107947751A (en) * 2016-10-12 2018-04-20 三星电机株式会社 Bulk acoustic wave resonator and its manufacture method
CN108075743A (en) * 2016-11-15 2018-05-25 环球通信半导体有限责任公司 The film bulk acoustic resonator inhibited with stray resonance
CN108336019A (en) * 2017-09-30 2018-07-27 中芯集成电路(宁波)有限公司 The method and wafer level packaging structure of conductive plunger are formed in a kind of wafer-level packaging
CN110401428A (en) * 2018-04-25 2019-11-01 上海珏芯光电科技有限公司 Thin film bulk acoustic wave resonator and its manufacturing method
CN110829997A (en) * 2018-08-07 2020-02-21 上海珏芯光电科技有限公司 Film bulk acoustic resonator and method for manufacturing the same
CN109660227A (en) * 2018-12-24 2019-04-19 中国科学院苏州纳米技术与纳米仿生研究所南昌研究院 Thin-film bulk acoustic wave filter and its packaging method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
章吉良等: "《微机电系统及其相关技术》", 31 December 1999, 上海交通大学出版社, pages: 1 *

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021189965A1 (en) * 2020-03-27 2021-09-30 中芯集成电路(宁波)有限公司 Film bulk acoustic resonator and manufacturing method therefor
WO2021232763A1 (en) * 2020-05-20 2021-11-25 中芯集成电路(宁波)有限公司上海分公司 Film bulk acoustic resonator and manufacturing method therefor
CN114684778A (en) * 2020-12-31 2022-07-01 中芯集成电路(宁波)有限公司上海分公司 MEMS device and manufacturing method thereof
CN114955976B (en) * 2021-02-26 2025-03-04 中芯集成电路(宁波)有限公司上海分公司 A MEMS device and a method for manufacturing the same
CN114955976A (en) * 2021-02-26 2022-08-30 中芯集成电路(宁波)有限公司上海分公司 MEMS device and manufacturing method thereof
CN113395050B (en) * 2021-03-30 2024-01-26 台湾晶技股份有限公司 Crystal oscillator packaging structure
CN113395050A (en) * 2021-03-30 2021-09-14 台湾晶技股份有限公司 Crystal oscillator packaging structure
US11463070B2 (en) 2022-01-18 2022-10-04 Shenzhen Newsonic Technologies Co., Ltd. FBAR structure and manufacturing method of same
US12088276B2 (en) 2022-01-18 2024-09-10 Shenzhen Newsonic Technologies Co., Ltd. Method of manufacturing an FBAR structure
CN114094970B (en) * 2022-01-20 2022-05-17 深圳新声半导体有限公司 Method for manufacturing film bulk acoustic wave resonator and resonator
CN114094970A (en) * 2022-01-20 2022-02-25 深圳新声半导体有限公司 Method for manufacturing film bulk acoustic wave resonator and resonator
CN116599481A (en) * 2023-06-08 2023-08-15 中国科学院上海微系统与信息技术研究所 Preparation method of acoustic wave resonator and acoustic wave resonator
CN116599481B (en) * 2023-06-08 2025-01-07 中国科学院上海微系统与信息技术研究所 Preparation method of acoustic wave resonator and acoustic wave resonator
CN117728791A (en) * 2023-06-30 2024-03-19 荣耀终端有限公司 Filter, manufacturing process of filter and electronic equipment

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