CN112017974B - Chip packaging structure and packaging method - Google Patents

Abstract

A chip packaging structure and packaging method, the structure comprising: a wafer (1), a groove (2) is arranged in the wafer (1); a first metal wire (3), arranged in the groove (2) and the wafer (1) surface; metal solder balls (4), arranged on the first metal wire (3) or the metal pad of the chip, for welding the metal pad of the chip to the first metal wire (3), to flip the chip Installed in the groove (2); the first plastic film (5) covers the upper surface of the wafer (1), the chip, and the first metal wire (3), and enters into the periphery of the chip functional area and the first metal wire ( 3) in the gap between, to form airtight cavity between wafer (1), groove (2) and chip; Inductive structure (6), is arranged on the upper surface of first plastic film (5) and/or or the lower surface of the wafer (1), and connected to the chip through the first metal wire (3); the pad (7) is arranged on the inductance structure (6).

Description

A chip packaging structure and packaging method

technical field

The present disclosure relates to the technical field of semiconductors, and in particular, to a chip packaging structure and a packaging method.

Background technique

Filters in communication are mainly divided into Surface Acoustic Wave filters (Surface Acoustic Wave, SAW) and Bulk Acoustic Wave filters (Bulk Acoustic Wave, BAW). The upper surface of the device is packaged to form a cavity structure. Traditional SAW usually grows metal bumps on the bare wafer and solders them on the ceramic substrate, and then seals the module with a metal cap, top sealing or coating process to form a cavity structure, but the ceramic substrate makes the soldering cost high and the package The large size and the instability of device installation make the device performance vary. In addition, the SAW can also be covered with the front side down on the upper surface of the printed circuit board (PCB) substrate, the SAW and the PCB substrate are electrically connected through gold balls, and the epoxy resin packaging film is covered on the upper part of the SAW and the PCB substrate , to form a cavity structure, but the epoxy resin film may be hot-pressed into the metal bump of the chip, and its coverage area will affect the package size and package strength, and there are extremely high requirements for SAW hot-pressing pressure. The wafer packaging of BAW chips usually adopts the wafer-level packaging (WLP) scheme, but the WLP process is complicated, requiring two wafers to be bonded, the cost is extremely high, and it also involves through-silicon via etching. Complex processes such as etching and gold-gold bonding are prone to chip failure due to process problems, and WLP cannot directly perform multi-chip integrated packaging.

In order to meet the increasingly complex system functions of products, the packaging technology of multi-chip interconnection integration is developing rapidly. The current mainstream solution is: multiple chips are arranged side by side and soldered to the substrate through bumps, and the signal interconnection between chips is realized through the internal circuit of the substrate. And the chip is protected by plastic packaging, and the module is welded to the PCB as a whole to realize the interconnection and integration of the product. This method requires multi-layer wiring transfer to realize inter-chip interconnection, and the substrate metal layer and dielectric layer are thick, which leads to problems such as signal transmission delay, thick package thickness, and high package cost.

Contents of the invention

(1) Technical problems to be solved

The present disclosure provides a chip packaging structure and a packaging method to at least solve the above technical problems.

(2) Technical solution

The present disclosure provides a chip packaging structure, including: a wafer, a groove is arranged in the wafer; a first metal wire is arranged on the side surface of the groove, both sides of the bottom surface and the wafer Upper surface; metal solder balls, arranged on the first metal wire or the metal pad of the chip, for welding the metal pad of the chip to the first metal wire, so as to flip the chip onto the In the groove; the first plastic film covers the upper surface of the wafer, the chip, and the first metal wire, and enters the gap between the chip functional area and the first metal wire, so that the A sealed cavity is formed between the wafer, the groove and the chip; the inductance structure is arranged on the upper surface of the first plastic packaging film and/or the lower surface of the wafer, and is connected to the The chip; pads are arranged on the inductance structure.

Optionally, the inductance structure is composed of one or more sets of second plastic packaging films, second metal wires and third metal wires, and the third metal wires are arranged on the second plastic packaging film according to a preset shape. On one surface, the second metal wires pass through the openings of the second plastic packaging film to sequentially connect each group of the third metal wires.

Optionally, the inductance structure is arranged on the upper surface of the first plastic packaging film, the first surface is the upper surface, and the second metal wire passes through the window of the first plastic packaging film, so that the first plastic packaging film A set of the third metal lines is connected to the first metal lines.

Optionally, the lead-out line of the first metal wire passes through the vacant window of the wafer and is connected to the first metal wire, and the inductance structure is arranged on the lower surface of the wafer and is located on the first metal wire. The lower surface of the wire lead-out line, the first surface is the lower surface, the second metal wire of the first group is connected with the first metal wire lead-out line (3'), so as to connect the second metal wire of the first group Three metal lines are connected to the first metal line.

Optionally, the chip corresponds to two inductive structures, which are respectively arranged on the upper surface of the first plastic packaging film and the lower surface of the wafer; the inductive structure arranged on the upper surface of the first plastic packaging film corresponds to The first surface is the upper surface, and the first group of the second metal wires passes through the opening of the first plastic film to connect the first group of the third metal wires to the The first metal line; the first surface corresponding to the inductance structure arranged on the lower surface of the wafer is the lower surface, and the lead-out line of the first metal line passes through the vacant window of the wafer and is connected to the first metal The inductance structure is located on the lower surface of the lead-out lines of the first metal wires, and the second metal wires of the first group are connected to the lead-out lines of the first metal wires to connect the first group of the second metal wires Three metal lines are connected to the first metal line.

Optionally, the thickness of the first plastic film on the surface of the first metal line is 20-50 μm.

The present disclosure also provides a chip packaging method, including: S1, preparing a groove in the wafer; S2, preparing a first metal on the side surface of the groove, both sides of the bottom surface, and the upper surface of the wafer. line; S3, preparing metal solder balls on the first metal wire or the metal pad of the chip, and welding the metal pad of the chip to the first metal wire through the metal solder ball, so as to The chip is flipped into the groove; S4, prepare a first plastic film on the upper surface of the wafer, the chip, and the first metal line, so that it enters between the functional area of the chip and the first metal line in the gap between the wafers, grooves and chips to form a closed cavity; S5, prepare an inductance structure on the upper surface of the first plastic film and/or the lower surface of the wafer, and Connecting the inductance structure to the first metal wire; S6, preparing a pad on the inductance structure.

Optionally, the inductance structure is arranged on the upper surface of the first plastic sealing film, and the step S5 includes: S51, preparing a second plastic sealing film on the upper surface of the first plastic sealing film; Open a window on the second plastic film; S53, open a window on the first plastic film to expose the first metal wire; S54, prepare a second metal wire in the empty window after window opening, and follow the preset shape Prepare a third metal wire on the upper surface of the second plastic packaging film; S55, repeat steps S51, S52, and S54 according to a preset number of times.

Optionally, the inductance structure is arranged on the lower surface of the wafer, and the step S5 includes: S51, opening a window on the lower surface of the wafer to expose the first metal wire, and the Prepare the first metal lead-out wire in the empty window of the wafer; S52, prepare a second plastic sealing film on the lower surface of the first metal lead-out wire; S53, open a window on the second plastic sealing film; S54, in the Prepare a second metal wire in the window of the second plastic packaging film, and prepare a third metal wire on the lower surface of the second plastic packaging film according to a preset shape; S55, repeat steps S52, S53, and S54 according to a preset number of times.

Optionally, the chip corresponds to the two inductance structures, which are respectively arranged on the upper surface of the first plastic packaging film and the lower surface of the wafer, and the step S5 includes: S51, for the wafer Open a window on the lower surface to expose the first metal wire, and prepare a first metal lead-out wire in the window of the wafer; S52, on the upper surface of the first plastic film and the first metal Prepare a second plastic film on the lower surface of the lead wire; S53, open a window on the second plastic film; S54, open a window on the first plastic film; S55, prepare a second plastic film in the empty window after window opening; Metal wires, and preparing third metal wires on the second plastic film on the upper and lower surfaces respectively according to a predetermined shape; S56, repeating steps S52, S53, and S55 according to a preset number of times.

(3) Beneficial effects

The chip packaging structure and packaging method provided by the present disclosure have at least the following beneficial effects:

(1) Sealing and high-temperature curing of the chip after flip-chip welding by using a film can prevent the plastic film from entering the functional area of the chip, thereby forming a highly reliable cavity structure, and can use the groove structure to fix the chip, improving the performance of the chip. Improve the mechanical shock resistance of the chip and the airtightness of the package;

(2) Thinning the coated wafer by CMP can eliminate the risk of wafer operation in the manufacturing process of the main chip wafer and reduce the difficulty of the process;

(3) Through re-metal wiring on the surface of the plastic-encapsulated wafer, the integration of inductance circuits can be realized to reduce costs, and through multi-layer metal wiring, the comprehensive impedance matching requirements of various radio frequency chips can be realized, and integrated manufacturing can be realized.

Description of drawings

FIG. 1 schematically shows a schematic diagram of a chip packaging structure provided by an embodiment of the present disclosure.

FIG. 2 schematically shows a flowchart of a chip packaging method provided by an embodiment of the present disclosure.

FIG. 3 schematically shows the distribution of groove units on a wafer provided by an embodiment of the present disclosure.

Fig. 4 schematically shows a schematic cross-sectional view of Fig. 3 along H-H'.

FIG. 5 is a schematic diagram of preparing the first metal wire 3 in step S2 of the packaging method.

6 is a schematic diagram of preparing metal solder balls and flip chips in step S3 of the packaging method.

7A and 7B are schematic diagrams of preparing the first plastic film and thinning the first plastic film in step S4 of the packaging method, respectively.

8A, 8B, 8C and 8D are schematic diagrams of preparing the inductor structure and pads in steps S5 and S6 of the packaging method.

FIG. 9 is a schematic diagram of another chip package structure.

FIG. 10 is a schematic diagram of another chip package structure.

Explanation of reference signs:

1-wafer; 2-groove; 3-first metal wire; 3'-first metal wire lead-out line; 4-metal solder ball; 5-first plastic film; 6-inductance structure; 7-pad; 8-second plastic film; 9'-empty window; 9-second metal wire; 10-third metal wire; 20-chip A groove; 21-chip B groove; 22-chip C groove; 23- Multi-chip groove unit; 24-chip A; 25-chip B; 26-cavity.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The first embodiment of the present disclosure shows a chip packaging structure. Referring to FIG. 1 , FIG. 3 , FIG. 9 and FIG. 10 , the chip packaging structure will be described in detail.

The chip packaging structure includes a wafer 1 , a groove 2 , a first metal wire 3 , a metal solder ball 4 , a first plastic packaging film 5 , an inductor structure 6 and a bonding pad 7 .

The material of the wafer 1 is one of silicon, glass, sapphire, ceramics or a mixed material mainly composed of silicon, glass, sapphire, and ceramics. The groove 2 is arranged in the wafer 1. Further, as shown in FIG. 3 , there may be multiple groups of multi-chip groove units 23 in the wafer 1, and there may be multiple grooves in each group of multi-chip groove units 23, They are respectively used to integrate and package different chips A ₁ , A ₂ , ... An , and in this embodiment, it _is only taken that each group of groove units includes chip A groove 20, chip B groove 21 and chip C groove 22 as an example , it can be understood that the multi-chip groove unit 23 may also include chip grooves of other sizes and numbers. The depth of the groove 2 is not greater than the height of its corresponding chip.

The first metal wire 3 is arranged on the side surface of the groove 2 , both sides of the bottom surface and the upper surface of the wafer 1 . The metal solder ball 4 is arranged on the first metal line 3 or on the metal pad of the chip, specifically, on the first metal line 3 on both sides of the bottom surface of the groove 2 or on the metal pad of the chip, and the metal The solder ball 4 should be aligned with the pin (pad) of the metal silicon chip of the chip, or the metal solder ball 4 should be aligned with the first metal line 3 on both sides of the bottom surface of the groove 2, so that the metal pad of the chip can pass through the metal pad. The solder balls 4 are aligned and soldered to the first metal wires 3 on both sides of the bottom surface of the groove 2 , so as to flip-chip the chip into the groove 2 .

The first plastic film 5 covers the upper surface of the wafer 1, the chip, and the first metal wire 3, and enters into the gap between the chip functional area and the first metal wire 3, so that the wafer 1, the groove 2 A closed cavity is formed between the chip and the chip. The thickness of the first plastic film 5 on the upper surface of the first metal wire 3 is 20-50 μm, so as to prevent the first metal wire 3 from being exposed.

The inductor structure 6 is disposed on the upper surface of the first plastic packaging film 5 and/or the lower surface of the wafer 1 , and is connected to the chip through the first metal wire 3 . The inductance structure 6 is composed of one group or more of the second plastic film 8, the second metal wire 9 and the third metal wire 10, and the shape of each group of the third metal wire 10 can be different, so as to realize the corresponding filtering effect. The inductor structure 6 includes three structures, as shown in FIG. 1 , FIG. 9 and FIG. 10 respectively.

Referring to FIG. 1 , the inductor structure 6 is disposed on the upper surface of the first plastic film 5 . Specifically, the second plastic sealing film 8 is provided with an empty window passing therethrough, the empty window can expose the third metal wire 10, and the first plastic sealing film 5 is also provided with an empty window passing therethrough, the empty window can Expose the first metal wire 3 on the upper surface of the wafer 1; the third metal wire 10 is arranged on the upper surface of the second plastic packaging film 8 according to a preset shape; the second metal wire 9 passes through the empty window of the second plastic packaging film 8 to Connect the third metal wires 10 of each group in turn, and the second metal wires 9 of the first group also pass through the opening of the first plastic film 5, so as to connect the third metal wires 10 of the first group to the first metal wires. wire 3, thereby connecting the inductive structure 6 to the chip.

Referring to FIG. 9 , the inductor structure 6 is disposed on the lower surface of the wafer 1 . Specifically, the second plastic sealing film 8 is provided with an empty window passing therethrough, and the empty window can expose the third metal line 10, and the wafer 1 is also provided with an empty window passing therethrough, and the empty window can expose the concave hole. The first metal wire 3 on both sides of the bottom surface of the groove 2; the third metal wire 10 is arranged on the lower surface of the second plastic film 8 according to the preset shape; the second metal wire 9 passes through the empty window of the second plastic film 8 to Each group of third metal wires 10 is connected in turn, and a first metal wire lead-out line 3' is also provided. The first metal wire lead-out line 3' passes through the window of the wafer 1. The wire 9 is connected to the first metal wire lead-out line 3', so as to connect the third metal wire 10 of the first group to the first metal wire 3 through the first metal wire lead-out line 3' and the second metal wire 9, thereby connecting the inductance Structure 6 is connected to the chip. It can be understood that under this structure, the first metal wire 3 may not be arranged on the upper surface of the wafer 1 , that is, the first metal wire 3 is only arranged on both sides of the bottom surface of the groove 2 .

Referring to FIG. 10 , in order to meet more complex circuit connection requirements, an inductance structure 6 can be provided on both the upper surface of the first plastic packaging film 5 and the lower surface of the wafer 1 . Specifically, the lower surface of the wafer 1 is provided with a first metal wire lead-out line 3 ′, and the lower surface of the wafer 1 is provided with an empty window passing therethrough, which can expose the first metal wires on both sides of the bottom surface of the groove 2 . Line 3; the second plastic sealing film 8 on the lower surface of the wafer 1 is provided with an empty window passing therethrough, which can expose the third metal line 10 on the lower surface of the wafer 1 and also expose the lower surface of the wafer 1 at the same time. The first metal wire leads 3'; the second plastic film 8 on the upper surface of the wafer 1 (specifically the upper surface of the first plastic film 5) is provided with an empty window passing therethrough, and the first plastic seal on the upper surface of the wafer 1 The film 5 is also provided with an empty window passing therethrough, which can expose the first metal wire 3 on the upper surface of the wafer 1; the third metal wire 10 arranged in the inductor structure 6 on the upper surface of the first plastic packaging film Arranged on the upper surface of the second plastic sealing film 8 according to the preset shape, the third metal wire 10 arranged in the inductance structure 6 on the lower surface of the wafer 1 is arranged on the lower surface of the second plastic sealing film 8 according to the preset shape; The metal wires 9 pass through the openings of the second plastic packaging film 8 to sequentially connect the third metal wires 10 of each group, and the second metal wires 9 of the first group in the two inductance structures 6 also pass through the first plastic packaging film respectively. 5 and the second plastic film 8 to connect the third metal wire 10 of the first group to the first metal wire 3 and the first metal wire lead-out wire 3', so that the two inductance structures 6 Connect to chip.

The pad 7 is disposed on the inductance structure 6 , specifically, on the last group of third metal lines 10 of the inductance structure 6 .

The second embodiment of the present disclosure shows a chip packaging method. As shown in FIG. 2, the packaging method will be described in detail with reference to FIG. 3 to FIG. 10, mainly including the following operations:

S1 , preparing grooves 2 in wafer 1 .

The material of the wafer 1 is one of silicon, glass, sapphire, ceramics or a mixed material mainly composed of silicon, glass, sapphire, and ceramics. In this embodiment, a glass wafer is used as the chip carrier and packaging material, which greatly reduces the cost of materials compared with the use of ceramic substrates, plastic substrates, and silicon gold-gold bonded wafer-level packaging structures.

Grooves 2 are prepared in the wafer 1. Referring to FIG. 3, there may be multiple groups of groove units in the wafer 1, and each group of groove units may have multiple grooves, which are respectively used to integrate and package different chips A ₁ , A ₂ ,..., An, in this embodiment, it _is only taken as an example that each group of groove units contains three kinds of chip grooves A, B, and C. It can be understood that the groove units can also contain other sizes and numbers chip groove. The depth of the groove 2 is not greater than the height of its corresponding chip.

In this embodiment, it is only taken that each group of groove units includes three kinds of chips A, B, and C as an example, and the cross-section along the H-H' direction in Fig. 3 is taken as an example, and its schematic diagram is as shown in Fig. 4. 4 contains multiple groups of groove units, and each group of groove units has two grooves, which are chip A groove 20 and chip B groove 21.

S2 , preparing the first metal wire 3 on the side surface of the groove 2 , both sides of the bottom surface and the upper surface of the wafer 1 .

Referring to FIG. 5 , the first metal line 3 is prepared by metal sputtering, photolithography, etching or LIFF-OFF process.

S3, preparing metal solder balls 4 on the first metal wire 3 or the metal pad of the chip, and welding the metal pad of the chip to the first metal wire 3 through the metal solder ball 4, so as to flip the chip into the groove 2 .

Referring to FIG. 6 , metal solder balls 4 are prepared on the first metal lines 3 on both sides of the bottom surface of the groove 2 . Using ultrasonic thermocompression bonding or thermocompression bonding, chip A and chip B are respectively flipped to their corresponding chip A groove 20 and chip B groove 21, so that the metal pads of chip A and chip B are aligned with the groove 2 4 alignment solders within the metal solder balls.

In addition, metal solder balls 4 may also be formed on chip A and chip B, and then chip A and chip B are soldered to the metal pad in the groove 2 through the metal solder balls 4 .

It can be understood that all the _chips A ₁ , A ₂ , .

S4, prepare the first plastic film 5 on the upper surface of the wafer 1, the chip, and the first metal wire 3, so that it enters the gap between the periphery of the chip functional area and the first metal wire 3, so that the wafer 1, the concave A closed cavity 26 is formed between the groove 2 and the chip.

First, a packaging film (i.e., the first plastic film 5) is pasted on the wafer 1, the chip, and the upper surface of the first metal wire 3 by hot pressing. The first plastic film 5 can be a layer of film, or it can be multilayer film. In this embodiment, grooves 2 suitable for various types of chips are formed on the wafer 1 in advance, and the flip-chip soldered chips are sealed by a coating method, and the cavity structure of the chip functional area is formed at the same time. By controlling the depth and width of the groove of the wafer 1, and controlling the precise alignment of the flip chip, a relatively narrow gap can be reserved between the periphery of the chip and the groove 2, and the film pressure and temperature of the operation S4 can be precisely controlled. The plastic sealing film enters the depth of the gap above, and completely prevents the plastic sealing film from entering the functional area of the chip, forming a highly reliable cavity structure.

Secondly, high-temperature curing is performed to form a closed cavity structure between the surface of the groove 2 in the wafer 1 and the functional area of the chip, as shown in FIG. 7A . In operation S4, high-temperature curing is carried out, and the plastic sealing film is plastic-encapsulated and cured, which can fix the chip in the packaging structure, making it difficult for the chip to move in the packaging structure, greatly increasing the mechanical shock resistance of the chip and packaging airtightness, and improving the reliability of the chip.

Then, carry out CMP thinning to the plastic cover of wafer 1 (namely the first plastic sealing film 5), and control thinning thickness, make thinning stop above the first metal line 3 on the upper surface of wafer 1, preferably, A first plastic film 5 with a thickness of 20-50 μm is reserved on the first metal wire 3 , as shown in FIG. 7B . After each chip is flip-chip packaged into the groove 2 of the wafer 1, the plastic surface of the wafer 1 is thinned by CMP, which can save the thinning process of the main chip wafer in the manufacturing process, and eliminate the main chip wafer in the groove 2. In the manufacturing process, the risk of thin sheet operation reduces the difficulty of its process; and because the depth of the groove is limited, the chip is embedded in the groove when it is thinned, so ultra-thin packaging can be realized.

S5 , preparing the inductance structure 6 on the upper surface of the first plastic packaging film 5 and/or the lower surface of the wafer 1 , and connecting the inductance structure 6 to the first metal wire 3 .

The packaging method in this embodiment is aimed at the three chip packaging structures shown in the first embodiment, so operation S5 is divided into three situations:

(1) Prepare an inductive structure 6 on the upper surface of the first plastic film 5, and operation S5 includes the following sub-operations:

S51, covering a layer of second plastic film 8 on the upper surface of the thinned first plastic film 5, and curing at high temperature, as shown in FIG. 8A .

S52, using a photolithographic etching process to open a window on the second plastic sealing film 8 .

S53 , using a photolithographic etching process to open a window on the first plastic packaging film 5 to expose the first metal lines 3 on the upper surface of the wafer 1 , as shown in FIG. 8B .

S54, using metal sputtering, electroplating or vapor deposition process, forming a metal layer (that is, the second metal line 9) in the empty window 9' after opening the window, so as to lead out the metal line under the window; and then using a photolithography etching process Or the LIFT-OFF process is used to perform metal rewiring on the upper surface of the second plastic packaging film 8, so as to prepare the third metal line 10 on the upper surface of the second plastic packaging film 8 according to a preset shape, as shown in FIG. 8C.

S55 , repeating operations S51 , S52 , and S54 according to a preset number of times to form multilayer metal wiring for manufacturing an inductance structure required by the filter circuit. In addition, in this operation, a dielectric layer may also be deposited instead of covering the second plastic film 8 in operation S51 , as shown in FIG. 8D .

(2) Prepare the inductor structure 6 on the lower surface of the wafer 1, and the formed chip package structure is shown in FIG. 9 . Operation S5 includes the following sub-operations:

S51 , opening a window on the lower surface of the wafer 1 to expose the first metal wire 3 , and preparing the lead-out line 3 ′ of the first metal wire in the window of the wafer 1 .

S52, covering the upper surface and the lower surface of the wafer 1 with a second plastic sealing film 8, and curing at high temperature.

S53 , using a photolithography process, opening a window on the second plastic film 8 on the lower surface of the wafer 1 , and exposing the first metal lead-out line 3 ′ on the lower surface of the wafer 1 .

S54, using metal sputtering, electroplating or vapor deposition process, forming a metal layer (that is, the second metal line 9) in the empty window after opening the window, so as to lead out the metal line above the window; then using photolithography etching process or LIFT -OFF process performs metal rewiring on the lower surface of the second plastic packaging film 8 to prepare the third metal wire 10 on the lower surface of the second plastic packaging film 8 according to the preset shape.

S55 , repeating operations S52 , S53 , and S54 according to a preset number of times to form multilayer metal wiring for manufacturing an inductance structure required by the filter circuit. In addition, in this operation, a dielectric layer may also be deposited instead of covering the second plastic sealing film 8 in operation S51.

(3) Prepare the inductor structure 6 on the upper surface of the first plastic packaging film 5 and the lower surface of the wafer 1 respectively, and the formed chip package structure is shown in FIG. 10 . Operation S5 includes the following sub-operations:

S51 , opening a window on the lower surface of the wafer 1 to expose the first metal wire 3 , and preparing the lead-out line 3 ′ of the first metal wire in the window of the wafer 1 .

S52 , respectively covering the upper surface of the thinned first plastic sealing film 5 and the lower surface of the first metal wire lead-out line 3 ′ of the wafer 1 with a layer of second plastic sealing film 8 , and performing high-temperature curing.

S53 , using a photolithographic etching process to respectively open windows on the second plastic film 8 on the upper surface and the lower surface. At this time, the first metal lead-out lines 3 ′ on the lower surface of the wafer 1 have been exposed.

S54, using a photolithographic etching process to open a window on the first plastic packaging film 5 on the upper surface, so as to expose the first metal lines 3 on the upper surface of the wafer 1 .

S55, using metal sputtering, electroplating or evaporation process, forming a metal layer (that is, the second metal line 9) in the empty window after opening the window, so as to respectively lead out the metal lines above and below the window; and then use photolithography to etch process or LIFT-OFF process on the upper surface of the second plastic film 8 (the second plastic film 8 is located on the first plastic film 5 ) and the second plastic film 8 (the second plastic film 8 is located on the second plastic film 8 below the wafer 1 ). Metal rewiring is carried out on the lower surface of a metal wire lead-out line 3′, so that the upper surface of the second plastic packaging film 8 (the second plastic packaging film 8 is located under the wafer 1) and the second plastic packaging film according to the preset shape 8 (The second plastic packaging film 8 is located under the first metal wire lead-out line 3' under the wafer 1) Prepare the third metal wire 10 on the lower surface.

S56 , repeating operations S52 , S53 , and S55 according to a preset number of times to form multi-layer metal wiring for manufacturing an inductance structure required by the filter circuit. In addition, in this operation, a dielectric layer may also be deposited instead of covering the second plastic sealing film 8 in operation S51.

In operation S5, the metal wiring is re-wired on the surface of the plastic-encapsulated wafer to realize the integration of the inductance circuit, thereby eliminating the costly and complicated substrate manufacturing process. In this embodiment, multi-chip grooves are prepared, and after multi-chip plastic packaging, metal wiring is carried out on the surface of the wafer, which can meet the integrated packaging requirements of various chips, and can greatly reduce the packaging area through reasonable planning. Realize extremely small size ultra-thin package.

In addition, multi-layer metal wiring after the integration and packaging of various chips can meet the comprehensive impedance matching requirements of various RF chips, realize the modularization and integrated manufacturing of RF front-end chips, and reduce the debugging work for users.

It should also be noted that the second plastic sealing film 8 in this embodiment can also be replaced by black epoxy resin or glass film.

S6 , preparing pads 7 on the inductor structure 6 .

Metal bumps or pads 7 are prepared on the last layer of metal wiring, and the multi-chip modules on the wafer 1 are diced, tested and packaged.

Therefore, the chip packaging structure and packaging method provided by the present disclosure have been described in detail, which is mainly suitable for multi-chip fan-out system-in-package, and can form a cavity packaging structure with reliable performance, especially suitable for acoustic wave filters, A micro-electro-mechanical system (Micro-Electro-Mechanical System, MEMS) device package with a cavity structure formed on the surface is required for microphones and the like. The packaging structure and method of the present disclosure can also realize multi-chip rewiring, and can realize the function of multi-chip system integrated inductance wiring; in addition, it can also realize the function of simultaneous thinning of multi-chips after cutting and flipping, avoiding the risk of chip sheet processing. The process is abnormal, and finally achieves ultra-thin packaging.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above descriptions are only specific embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims (10)

1. A chip packaging structure, comprising: A wafer (1), wherein grooves (2) are arranged in the wafer (1); The first metal wire (3) is arranged on the side surface of the groove (2), both sides of the bottom surface and the upper surface of the wafer (1); Metal solder balls (4), arranged on the first metal wire (3) or the metal pad of the chip, for welding the metal pad of the chip to the first metal wire (3), so as to The chip is flipped into the groove (2); The first plastic film (5) covers the upper surface of the wafer (1), the chip, and the first metal wire (3), and enters the area between the surrounding area of the chip function area and the first metal wire (3). gap to form a closed cavity between the wafer (1), the groove (2) and the chip; An inductance structure (6), arranged on the upper surface of the first plastic packaging film (5) and/or the lower surface of the wafer (1), and connected to the chip through the first metal wire (3) ; The welding pad (7) is arranged on the inductance structure (6). 2. The chip packaging structure according to claim 1, wherein the inductance structure (6) is composed of one group or more of the second plastic film (8), the second metal wire (9) and the third metal wire (10) ), the third metal wire (10) is arranged on the first surface of the second plastic film (8) according to a preset shape, and the second metal wire (9) passes through the second plastic film ( 8) to connect the third metal wires (10) of each group in sequence. 3. The chip packaging structure according to claim 2, wherein the inductance structure (6) is arranged on the upper surface of the first plastic packaging film (5), the first surface is the upper surface, and the second The metal wires (9) pass through the empty windows of the first plastic packaging film (5), so as to connect the first group of the third metal wires (10) to the first metal wires (3). 4. The chip package structure according to claim 2, wherein the lead-out wire (3') of the first metal wire passes through the vacant window of the wafer (1) and is connected to the first metal wire (3), The inductance structure (6) is arranged on the lower surface of the wafer (1) and is located on the lower surface of the first metal lead-out line (3'), the first surface is the lower surface, and the first group The second metal wire (9) of the first group is connected to the first metal wire lead-out wire (3') to connect the third metal wire (10) of the first group to the first metal wire (3 ). 5. The chip packaging structure according to claim 2, wherein the chip corresponds to two inductive structures (6), which are respectively arranged on the upper surface of the first plastic sealing film (5) and the wafer ( 1) the lower surface; The first surface corresponding to the inductance structure (6) arranged on the upper surface of the first plastic packaging film (5) is the upper surface, and the second metal wires (9) of the first group pass through the first the empty window of the plastic sealing film (5) to connect the first group of said third metal wires (10) to said first metal wires (3); The first surface corresponding to the inductance structure (6) arranged on the lower surface of the wafer (1) is the lower surface, and the first metal wire lead-out line (3') passes through the vacant window of the wafer (1) And connected to the first metal wire (3), the inductance structure (6) is located on the lower surface of the first metal wire lead-out line (3'), and the first group of the second metal wire (9) connected with the first metal wire lead-out wire (3') to connect the third metal wire (10) of its first group to the first metal wire (3). 6. The chip packaging structure according to claim 1, wherein the thickness of the first plastic film (5) on the upper surface of the first metal wire (3) is 20-50 μm. 7. A chip packaging method, comprising: S1, preparing grooves (2) in the wafer (1); S2, preparing a first metal wire (3) on the side surface of the groove (2), both sides of the bottom surface, and the upper surface of the wafer (1); S3, preparing a metal solder ball (4) on the first metal wire (3) or the metal pad of the chip, and welding the metal pad of the chip to the first metal pad through the metal solder ball (4) on a metal wire (3), so as to flip-chip the chip into the groove (2); S4, prepare the first plastic film (5) on the upper surface of the wafer (1), the chip, and the first metal wire (3), so that it enters between the periphery of the chip functional area and the first metal wire (3) In the gap between, to form a closed cavity between the wafer (1), the groove (2) and the chip; S5, preparing an inductance structure (6) on the upper surface of the first plastic packaging film (5) and/or the lower surface of the wafer (1), and connecting the inductance structure (6) to the first metal wire (3); S6, preparing pads (7) on the inductor structure (6). 8. The chip packaging method according to claim 7, wherein the inductance structure (6) is arranged on the upper surface of the first plastic film (5), and the step S5 comprises: S51, preparing a second plastic film (8) on the upper surface of the first plastic film (5); S52, opening a window on the second plastic film (8); S53, opening a window on the first plastic film (5) to expose the first metal wire (3); S54, preparing the second metal wire (9) in the empty window after opening the window, and preparing the third metal wire (10) on the upper surface of the second plastic film (8) according to the preset shape; S55, repeatedly executing steps S51, S52, and S54 according to a preset number of times. 9. The chip packaging method according to claim 7, the inductance structure (6) is arranged on the lower surface of the wafer (1), and the step S5 comprises: S51, opening a window on the lower surface of the wafer (1) to expose the first metal line (3), and preparing a first metal lead-out line (3' in the window of the wafer (1) ); S52, preparing a second plastic film (8) on the lower surface of the first metal lead-out wire (3'); S53, opening a window on the second plastic film (8); S54, preparing a second metal wire (9) in the window of the second plastic sealing film (8), and preparing a third metal wire (10) on the lower surface of the second plastic sealing film (8) according to a preset shape ); S55, repeatedly execute steps S52, S53, and S54 according to a preset number of times. 10. The chip packaging method according to claim 7, wherein the chip corresponds to two inductive structures (6), which are respectively arranged on the upper surface of the first plastic sealing film (5) and the wafer (1) the lower surface, the step S5 includes: S51, opening a window on the lower surface of the wafer (1) to expose the first metal line (3), and preparing a first metal lead-out line (3' in the window of the wafer (1) ); S52, preparing a second plastic film (8) on the upper surface of the first plastic film (5) and the lower surface of the first metal lead wire (3') respectively; S53, opening a window on the second plastic film (8); S54, opening a window on the first plastic film (5); S55, preparing a second metal wire (9) in the empty window after opening the window, and preparing a third metal wire (10) on the second plastic film (8) on the upper and lower surfaces respectively according to the preset shape; S56, repeatedly execute steps S52, S53, and S55 according to a preset number of times.

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