CN112017575A - Driving method, driving module and display device - Google Patents
Driving method, driving module and display device Download PDFInfo
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- CN112017575A CN112017575A CN202010618781.6A CN202010618781A CN112017575A CN 112017575 A CN112017575 A CN 112017575A CN 202010618781 A CN202010618781 A CN 202010618781A CN 112017575 A CN112017575 A CN 112017575A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The invention provides a driving method, a driving module and a display device. The driving method is applied to a display panel, the display panel comprises a plurality of rows of grid lines, a plurality of columns of data lines and a plurality of rows and a plurality of columns of pixel circuits, and the driving method comprises the following steps: judging whether the data voltage provided to the pixel circuits of the first a row included in the display panel and included in the display data of the mth frame has periodicity or not, and setting a dummy data voltage according to a judgment result; m is a positive integer; a is a positive integer, a is greater than the predetermined number of rows; supplying the dummy data voltage to the data line during an mth dummy data voltage supply period. The invention can make the brightness of the first row pixel circuit consistent with the brightness of the non-first row same gray scale pixel circuit.
Description
The invention claims priority of Chinese patent application No. 202010580289.4, which is filed on 6, 23/2020.
Technical Field
The invention relates to the technical field of display, in particular to a driving method, a driving module and a display device.
Background
The problem that pixels in a first row are slightly bright or dark exists in the existing large-size display screen, and the problem is mainly caused by the fact that charging initial positions of the pixels in the first row are different from those of pixels in the same gray scale, and further charging effects of the pixels in the first row are different from those of pixels in the same gray scale. The existing methods for improving the brightness of the first line and the darkness of the first line are all the Dummy Data (pseudo Data voltage) inserted in a certain mode before the first line Data of each frame, and the following three methods are commonly used for inserting the Dummy Data: insert dummy data voltage corresponding to gray level 0, insert dummy data voltage corresponding to gray level 127, insert first column data. These methods can improve the quality of the first line pixels of some patterns, but the opposite effect appears in other patterns. They are not reasonable in theory and practice, so that the quality of the first row pixels cannot be improved in some cases, but rather the first row pixels are deteriorated.
In the future, with the improvement of the resolution and the frame frequency of the display screen, the brightness difference between the first line of pixels and the other pixels in the same gray scale line is more obvious. Theoretically, the generation mechanism of the undesirable product is analyzed, a general solution is provided, and the method has important significance for the existing product and the future product.
Disclosure of Invention
The invention mainly aims to provide a driving method, a driving module and a display device, which solve the problems that the first line is brighter and the first line is darker when the existing display panel displays.
In order to achieve the above object, the present invention provides a driving method applied to a display panel including a plurality of rows of gate lines, a plurality of columns of data lines, and a plurality of rows and a plurality of columns of pixel circuits, the driving method including:
judging whether the data voltage provided to the pixel circuits of the first a row included in the display panel and included in the display data of the mth frame has periodicity or not, and setting a dummy data voltage according to a judgment result; m is a positive integer; a is a positive integer, a is greater than the predetermined number of rows;
supplying the dummy data voltage to the data line during an mth dummy data voltage supply period.
Optionally, the step of setting the dummy data voltage according to the determination result includes:
when the data voltage is judged to have periodicity, setting the data voltage provided to the pixel circuit of the nth row in the display data of the mth frame as a pseudo data voltage; when the data voltage is judged not to have periodicity, setting the data voltage provided to the pixel circuits in the first row in the display data of the mth frame as a pseudo data voltage;
n is a ratio between a period of the data voltage variation and a line scanning time, and n is a positive integer.
Optionally, the setting the dummy data voltage according to the determination result includes:
when the data voltages provided to the pixel circuits of the first a row in B display areas are judged to have periodicity respectively and the periods of the data voltage change corresponding to each display area are not equal, the data voltage provided to the pixel circuits of the A row in the m-th frame of display data is set as a pseudo data voltage;
a is a positive integer, A is the least common multiple of the ratios corresponding to the B display regions;
the ratio corresponding to the b-th display area is the ratio between the period of the data voltage variation supplied to the pixel circuits of the previous a row and one row scanning time in the b-th display area;
b is an integer greater than 1, B is a positive integer less than or equal to B.
Optionally, the setting the dummy data voltage according to the determination result includes:
when it is judged that the data voltages provided to the pixel circuits of the former a rows in the B display areas are respectively periodic and the periods of the data voltage changes corresponding to each display area are not equal, respectively setting dummy data voltages for the B display areas; b is an integer greater than 1.
Optionally, the step of respectively setting the dummy data voltages for the B display regions includes:
when it is determined that the data voltages supplied to the pixel circuits of the first a row in the b-th display area have periodicity, setting the data voltages supplied to the pixel circuits of the n-th row in the b-th display area in the display data of the m-th frame to dummy data voltages corresponding to the b-th display area; b is a positive integer less than or equal to B;
n is the ratio of the period of the change of the data voltage provided to the pixel circuits of the previous a rows in the b-th display area to the scanning time of one row, and n is a positive integer.
Optionally, the step of providing the dummy data voltage to the data line specifically includes:
the dummy data voltage corresponding to the b-th display area is supplied to the data line located in the b-th display area.
Optionally, a duration of the m-th dummy data voltage supplying period is equal to a difference between a duration of one-time opening of the gate line and a one-line scanning time;
the mth dummy data voltage supply period is immediately adjacent to a first row data voltage supply period included in the m +1 th frame screen display time;
the period of time in which the first row gate line is turned on in the (m + 1) th frame picture display time includes the m-th dummy data voltage supply period and the first row data voltage supply period, which are sequentially set.
The invention also provides a driving module, which comprises an analysis processing unit and a control unit;
the analysis processing unit is used for judging whether the data voltage provided to the pixel circuits of the first a row included in the display panel and included in the display data of the mth frame has periodicity or not and setting a pseudo data voltage according to the judgment result; m is a positive integer; a is a positive integer, a is greater than the predetermined number of rows;
the control unit is used for controlling the supply of the dummy data voltage to the data line in an mth dummy data voltage supply time period.
Optionally, the driving module of the present invention further includes a storage unit;
the storage unit is used for storing the pseudo data voltage.
Optionally, the analysis processing unit is specifically configured to set a data voltage provided to the pixel circuit in the nth row in the mth frame of display data as a dummy data voltage when it is determined that the data voltage has periodicity; when the data voltage is judged not to have periodicity, setting the data voltage provided to the pixel circuits in the first row in the display data of the mth frame as a pseudo data voltage;
n is a ratio between a period of the data voltage variation and a line scanning time, and n is a positive integer.
Optionally, the analysis processing unit is specifically configured to set, as the dummy data voltage, the data voltage provided to the row a pixel circuit in the m-th frame of display data when it is determined that, in the B display areas, the data voltages provided to the row a pixel circuits respectively have periodicity and the periods of the data voltage changes corresponding to each display area are not equal to each other;
a is a positive integer, A is the least common multiple of the ratios corresponding to the B display regions;
the ratio corresponding to the b-th display area is the ratio between the period of the data voltage variation supplied to the pixel circuits of the previous a row and one row scanning time in the b-th display area;
b is an integer greater than 1, B is a positive integer less than or equal to B.
Optionally, the analysis processing unit is specifically configured to set dummy data voltages for B display areas when it is determined that the data voltages provided to the pixel circuits in the first row a in the B display areas have periodicity respectively and the periods of the data voltage changes corresponding to each display area are not equal; b is an integer greater than 1.
The invention also provides a display device which comprises the driving module.
Optionally, the display device includes a timing controller, and the analysis processing unit is disposed in the timing controller.
Compared with the prior art, the driving method, the driving module and the display device can enable the charging effect of the first row of pixel circuits to be consistent with the charging effect of the non-first row of same-gray-scale pixel circuits, further enable the brightness of the first row of pixel circuits to be consistent with the brightness of the non-first row of same-gray-scale pixel circuits, and solve the problems that the first row is slightly bright and the first row is slightly dark.
Drawings
Fig. 1 is a flowchart of a driving method according to an embodiment of the present invention;
fig. 2 is a waveform diagram of gate driving signals on a first row gate line G1 through a fourth row gate line G4 included in the display panel when the gate driving circuit scans a plurality of rows of gate lines of the display panel row by row;
FIGS. 3A and 3B are schematic diagrams of two checkerboard pictures, respectively;
FIGS. 3C and 3D are schematic diagrams of two kinds of crosstalk pictures, respectively;
FIG. 3E is a diagram of a color bar picture;
FIG. 3F is a schematic illustration of a tiled display;
FIG. 3G is a schematic view of another tiled display;
FIG. 3H is a diagram of a 1+2Dot picture;
FIG. 3I is a diagram of a 2Dot picture
FIG. 4 is a diagram of a display;
FIG. 5 is a block diagram of a driving module according to an embodiment of the present invention;
fig. 6 is a block diagram of a driving module according to another embodiment of the invention;
fig. 7 is a schematic diagram of a timing controller included in the display panel according to the embodiment of the invention;
fig. 8 is a schematic workflow diagram of an analysis processing unit in a display panel according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The driving method according to the embodiment of the present invention is applied to a display panel, where the display panel includes a plurality of rows of gate lines, a plurality of columns of data lines, and a plurality of rows and a plurality of columns of pixel circuits, as shown in fig. 1, the driving method includes:
s1: judging whether the data voltage provided to the pixel circuits of the first a row included in the display panel and included in the display data of the mth frame has periodicity or not, and setting a dummy data voltage according to a judgment result; m is a positive integer; a is a positive integer, a is greater than the predetermined number of rows;
s2: supplying the dummy data voltage to the data line during an mth dummy data voltage supply period.
In the driving method according to the embodiment of the present invention, according to a result of periodically determining whether a data voltage provided to the pixel circuits in the first a row included in the display panel included in the mth frame of display data has a periodicity, a dummy data voltage is set, and the dummy data voltage is provided to the data line in the mth dummy data voltage providing time period, so that a charging effect of the pixel circuit in the first row and a charging effect of the pixel circuits in the non-first row and the gray scale are consistent at the display time of the (m + 1) th frame of picture, and further, a luminance of the pixel circuit in the first row and a luminance of the pixel circuits in the non-first row and the gray scale are consistent, thereby solving the problems of the first row being brighter and the first row being darker.
The difference between the brightness of the pixels in the first row and the brightness of the pixels in the same gray scale in the non-first row is caused by the difference of the charging effect between the two. The influence factors of the charging effect are mainly reflected in three aspects: charging time, a charging starting point and a charging target point. The charging time of each row of pixels in the display panel is the same (the time for each row of grid to be opened is the same); for the pixels in the first row and the pixels in the same gray scale in the non-first row, the gray scales are the same, so that the charging target points of the pixels in the first row and the pixels in the non-first row are the same in order to reach the same gray scale voltage, namely the charging target points are the same. Therefore, the difference in the charging effects between the two is mainly reflected on the charging start point.
The dummy data voltage is set before the first row in order to provide the pixels in the first row with a charge starting point same as that of the pixels in the same gray scale as that in the non-first row. In the periodic picture, the charging starting point of the pixels with the same gray scale in the non-first row is the gray scale voltage of the pixels in the upper row. Therefore, the charging starting point of the first row of pixels should be consistent with the charging starting point of the first row of pixels, so that the same charging effect can be achieved, and the same brightness value can be achieved. In the scheme, the nth data in a periodic (the period is set as n-line scanning time) picture is inserted before the first line of pixels to be used as a pseudo data voltage, namely, the charging starting point of the first line of pixels is kept at the gray scale voltage level of the previous line of pixels which are not the first line of pixels with the same gray scale.
In practical implementation, the data voltage provided to the pixel circuits of the first a row included in the display panel has periodicity that: among data voltages supplied to pixel circuits of a first a rows included in the display panel, a c-th row data voltage is the same as a d × n + c-th row data voltage, n is a positive integer, c is a positive integer less than or equal to n, d is a positive integer, and d × n + c is less than or equal to a.
In the embodiment of the invention, a is more than the preset number of rows; for example, a may be equal to 20 or 30, but is not limited thereto.
In an embodiment of the present invention, a duration of the m-th dummy data voltage supplying period is equal to a difference between a duration of one-time opening of the gate line and a one-line scanning time;
the mth dummy data voltage supply period is immediately adjacent to a first row data voltage supply period included in the m +1 th frame screen display time;
the period of time in which the first row gate line is turned on in the (m + 1) th frame picture display time includes the m-th dummy data voltage supply period and the first row data voltage supply period, which are sequentially set.
In this embodiment of the present invention, at the display time of the (m + 1) th frame, a plurality of rows of gate lines included in the display panel may be sequentially opened, but not limited thereto.
In a specific implementation, the number of lines into which the dummy data voltage is inserted should be equal to the number of pre-charged lines of the pixel circuit, that is, the m-th dummy data voltage supply period lasts for a time equal to a difference between a time for which the gate line is once opened and a one-line scanning time. For example, when the number of precharge rows is two, the dummy data voltage should be inserted also in a scanning time of two rows before the first row data voltage supply period included in one frame screen display time to improve the difference between the luminance of the pixel circuit of the first row and the luminance of the pixel circuits of the other rows.
In the embodiment of the present invention, the number of rows of the inserted dummy data voltage is set to be equal to the number of rows of the precharge voltage, also in order to make the charge start points of the pixel circuits of the first row and the pixel circuits of the non-first row of the same gray scale coincide as much as possible. In the pre-charging stage, the non-first row pixels are pre-charged by the data voltage on the data line, and the corresponding first row pixels should have the same effect.
In the embodiment of the present invention, the display panel may include a gate driving circuit, and when the gate driving circuit scans a plurality of rows of gate lines of the display panel row by row, a row scanning time may refer to a time interval between time points at which adjacent rows of gate lines are changed from an off state to an on state, but is not limited thereto.
For example, when the gate driving circuit scans a plurality of rows of gate lines of the display panel row by row, at the m +1 th frame picture display time, the waveform of the gate driving signal on the first row of gate lines G1 included in the display panel, the waveform of the gate driving signal on the second row of gate lines G2 included in the display panel, the waveform of the gate driving signal on the third row of gate lines G3 included in the display panel, and the waveform of the gate driving signal on the fourth row of gate lines G4 included in the display panel may be as shown in fig. 2, a row scanning time is denoted by T0, a time when the first row of gate lines is turned on is denoted by T1, an mth dummy data voltage supply time period is denoted by T1, and a first row data voltage supply time period is denoted by T2. In the embodiment shown in FIG. 2, the number of pre-charged rows is two.
In the embodiment of the present invention, the gate line is opened by: the electric potential of the grid driving signal on the grid line is effective voltage; for example, when the data writing transistor in which the gate electrode in the pixel circuit is connected to the gate line is an n-type transistor, the effective voltage is a high voltage; when the data writing transistor in which the gate electrode in the pixel circuit is connected to the gate line is a p-type transistor, the effective voltage is a low voltage.
In the embodiment of the present invention, the effective voltage is taken as an example for explanation.
According to a specific embodiment, the step of setting the dummy data voltage according to the determination result includes:
setting a data voltage supplied to pixel circuits of an nth row in display data of an mth frame as a dummy data voltage when it is determined that the data voltage supplied to the pixel circuits of the first a rows included in the display panel included in the display data of the mth frame has periodicity;
when the data voltage provided to the pixel circuits of the first row a included in the display panel and included in the display data of the mth frame is judged not to have periodicity, the data voltage provided to the pixel circuits of the first row in the display data of the mth frame is set to be the pseudo data voltage;
n is a ratio between a period of the data voltage variation and a line scanning time, and n is a positive integer.
In specific implementation, when the data voltage provided to the pixel circuits of the first a row included in the display panel and included in the display data of the mth frame is judged to have periodicity, the data voltage provided to the pixel circuits of the nth row in the display data of the mth frame is set as a pseudo data voltage;
when it is judged that the data voltage supplied to the pixel circuits of the first a rows included in the display panel included in the display data of the mth frame does not have periodicity, the data voltage supplied to the pixel circuits of the first row in the display data of the mth frame is set to the dummy data voltage.
In the embodiment of the present invention, the period of the data voltage variation supplied to the pixel circuits of the first a row included in the display panel included in the m-th frame display data refers to: when the data voltage provided to the pixel circuits of the first a rows included in the display panel is the same as the data voltage of the d × n + c rows, the n row scanning time is the variation period of the data voltage;
n is a positive integer, c is a positive integer less than or equal to n, d is a positive integer, and d × n + c is less than or equal to a.
Table 1 shows waveforms of data voltages in five typical frames (i.e., a frame with a grayscale of 255, a frame with a grayscale of 127, a frame with a grayscale of 0, a frame with an H1line255, and a frame with an H1line 127) when different dummy data voltages are inserted before first line data. As can be seen from table 1, when the frame is a gray scale 255 frame, it is better to insert the data voltage corresponding to the gray scale 255 or the data of the first row before the first row; when the picture is a gray level 127 picture, it is preferable to insert a data voltage corresponding to the gray level 127 or first line data before the first line; when the picture is a gray scale 0 picture, it is preferable to insert a data voltage corresponding to the gray scale 0 or first row data before the first row; when the picture is an H1line255 picture, it is preferable to insert a data voltage corresponding to a gray level 0 before the first line; when the frame is an H1line127 frame, it is preferable to insert a data voltage corresponding to gray level 0 before the first row.
Table 1:
table 2 shows the luminance of the pixels in the first row when different dummy data voltages are inserted before the data in the first row in the five typical frames (i.e., frame 255 with gray scale, frame 127 with gray scale, frame 0 with gray scale, frame 255 with H1line, and frame 127 with H1 line).
Table 2:
in specific implementation, for a checkerboard picture, a color strip picture, a transverse gray scale expansion picture and a crosstalk picture, the period of the data voltage change is a line of scanning time;
for an H1Line picture (the H1Line picture refers to a bright picture and a dark picture in one Line) and a 1Dot picture, the period of the data voltage change is two lines of scanning time;
for a 1+2Dot picture and a 2Dot picture, the period of the data voltage change is four rows of scanning time;
the data voltage is not periodic for longitudinal gray scale expansion pictures and some picture pictures.
The 1Dot picture refers to: the odd-numbered row pixels of the odd-numbered rows are bright, the even-numbered row pixels of the odd-numbered rows are dark, the even-numbered row pixels of the even-numbered rows are bright, and the odd-numbered row pixels of the even-numbered rows are dark; or, the pixels in the odd-numbered rows and the odd-numbered columns are bright, the pixels in the even-numbered rows and the even-numbered columns are dark, the pixels in the odd-numbered rows and the even-numbered columns are bright, and the pixels in the odd-numbered rows and the odd-numbered columns are dark.
In the embodiment of the invention, a pixel may include a red pixel circuit, a green pixel circuit, and a blue pixel circuit in the same row, but not limited thereto.
In a specific implementation, the red pixel circuit, the green pixel circuit, and the blue pixel circuit are sub-pixels included in the pixel.
The 1+2Dot picture refers to: the first row odd-numbered line pixels and the first row even-numbered line pixels are bright and dark respectively; in other rows, pixels in odd-numbered columns of a 4p-2 th row and pixels in odd-numbered columns of the 4p-1 th row are dark, pixels in even-numbered columns of the 4p-2 th row and pixels in even-numbered columns of the 4p-1 th row are bright, pixels in odd-numbered columns of the 4p th row and pixels in odd-numbered columns of a 4p +1 th row are bright, and pixels in even-numbered columns of the 4p th row and pixels in even-numbered columns of the 4p +1 th row are dark; or the pixels in the odd-numbered rows and the pixels in the even-numbered rows are dark and bright respectively; in other rows, pixels in odd-numbered columns of a 4p-2 th row and pixels in odd-numbered columns of a 4p-1 th row are bright, pixels in even-numbered columns of the 4p-2 th row and pixels in even-numbered columns of the 4p-1 th row are dark, pixels in odd-numbered columns of the 4p th row and pixels in odd-numbered columns of a 4p +1 th row are dark, and pixels in even-numbered columns of the 4p th row and pixels in even-numbered columns of the 4p +1 th row are bright; p is a positive integer.
The 2Dot picture refers to: pixels in odd-numbered columns of a 4p-3 th row and pixels in odd-numbered columns of a 4p-2 th row are bright, pixels in even-numbered columns of the 4p-3 th row and pixels in even-numbered columns of the 4p-2 th row are dark, pixels in odd-numbered columns of the 4p-1 th row and pixels in odd-numbered columns of the 4p-1 th row are dark, and pixels in even-numbered columns of the 4p-1 th row and pixels in even-numbered columns of the 4p-2 th row are bright; or the pixels in the odd-numbered columns in the 4p-3 th row and the pixels in the odd-numbered columns in the 4p-2 th row are dark, the pixels in the even-numbered columns in the 4p-3 th row and the pixels in the even-numbered columns in the 4p-2 th row are bright, the pixels in the odd-numbered columns in the 4p-1 th row and the pixels in the odd-numbered columns in the 4p-1 th row are bright, and the pixels in the even-numbered columns in the 4p-1 th row and the pixels in the even-numbered columns in the 4; p is a positive integer.
FIGS. 3A and 3B are schematic diagrams of two checkerboard pictures, respectively;
FIGS. 3C and 3D are schematic diagrams of two kinds of crosstalk pictures, respectively;
FIG. 3E is a diagram of a color bar picture; in fig. 3E, from left to right, there may be a yellow bar, a pink bar, a sky blue bar, a dark blue bar, a green bar, a red bar, and a black bar, respectively.
FIG. 3F is a schematic illustration of a tiled display; on the left side of fig. 3F, a checkerboard screen is shown, and on the right side of fig. 3F, a gray screen is shown.
FIG. 3G is a schematic view of another tiled display; in fig. 3G, a red screen is provided on the upper left, a green screen is provided on the upper right, a blue screen is provided on the lower left, and a checkerboard screen is provided on the lower right.
Fig. 3H is a schematic diagram of a 1+2Dot picture, and fig. 3I is a schematic diagram of a 2Dot picture.
For the display screen in fig. 3A, the display screen in fig. 3B, the display screen in fig. 3C, the display screen in fig. 3D, the display screen in fig. 3E, the display screen in fig. 3F, and the display screen in fig. 3G, the period of the data voltage variation supplied to the first 20 rows of pixel circuits (exemplified by a being equal to 20) is one row scanning time.
In fig. 3H and 3I, reference numeral RL denotes that the red pixel circuit is bright, reference numeral RE denotes that the red pixel circuit is dark, reference numeral GL denotes that the green pixel circuit is bright, reference numeral GE denotes that the green pixel circuit is dark, reference numeral BL denotes that the blue pixel circuit is bright, and reference numeral BE denotes that the blue pixel circuit is dark. For the 1+2Dot picture in fig. 3H and the 2Dot picture in fig. 3I, the minimum line period is equal to 4.
According to another specific embodiment, the setting of the dummy data voltage according to the determination result includes:
when the data voltages provided to the pixel circuits of the first a row in B display areas are judged to have periodicity respectively and the periods of the data voltage change corresponding to each display area are not equal, the data voltage provided to the pixel circuits of the A row in the m-th frame of display data is set as a pseudo data voltage;
a is a positive integer, A is the least common multiple of the ratios corresponding to the B display regions;
the ratio corresponding to the b-th display area is the ratio between the period of the data voltage variation supplied to the pixel circuits of the previous a row and one row scanning time in the b-th display area;
b is an integer greater than 1, B is a positive integer less than or equal to B.
In a specific implementation, when the data voltages provided to the pixel circuits of the first a row in different display regions of the display panel have periodicity respectively, and the periods of the data voltage changes corresponding to each display region are not equal, the interpolation may be performed by taking the least common multiple of the minimum row periods of the display regions.
In the embodiment of the present invention, the minimum line period refers to: a period of the data voltage variation corresponding to each display region;
the interpolation by taking the least common multiple of the minimum line period of each display area refers to: setting a data voltage supplied to the a-th row pixel circuit in the m-th frame display data to a dummy data voltage;
a is the least common multiple of the ratio corresponding to the B display areas;
the ratio corresponding to the b-th display area is a ratio between a period of a data voltage variation supplied to the pixel circuits of the previous a-th row and a one-row scanning time in the b-th display area.
According to still another embodiment, the setting of the dummy data voltage according to the determination result includes:
when it is judged that the data voltages provided to the pixel circuits of the former a rows in the B display areas are respectively periodic and the periods of the data voltage changes corresponding to each display area are not equal, respectively setting dummy data voltages for the B display areas; b is an integer greater than 1.
In a specific implementation, the step of setting the dummy data voltages for the B display regions respectively includes:
when it is determined that the data voltages supplied to the pixel circuits of the first a row in the b-th display area have periodicity, setting the data voltages supplied to the pixel circuits of the n-th row in the b-th display area in the display data of the m-th frame to dummy data voltages corresponding to the b-th display area; b is a positive integer less than or equal to B;
n is the ratio of the period of the change of the data voltage provided to the pixel circuits of the previous a rows in the b-th display area to the scanning time of one row, and n is a positive integer.
In an embodiment of the present invention, the step of providing the dummy data voltage to the data line specifically includes:
the dummy data voltage corresponding to the b-th display area is supplied to the data line located in the b-th display area.
In a specific implementation, when the data voltages provided to the pixel circuits in the first a row in different display regions of the display panel have periodicity respectively, and the periods of the data voltage changes corresponding to each display region are not equal, the interpolation may be performed in different regions, that is, the data voltage provided to the pixel circuit in the n row in the b display region in the m-th frame of display data is set to be the dummy data voltage corresponding to the b display region.
As shown in fig. 4, at the display time of the mth frame, a gray-scale screen is displayed in the first display area a1 of the display panel; in the second display area a2 of the display panel, an H1line screen is displayed; in the third display area a3 of the display panel, a 2Dot picture is displayed;
for the first display region a1, n is equal to 1;
for the second display region a2, n is equal to 2;
for the third display region a3, n equals 4;
the data voltage supplied to the pixel circuit in the fourth row in the display data of the mth frame is set to the dummy data voltage in the mth dummy data voltage supply period.
As shown in fig. 5, the driving module according to the embodiment of the present invention includes an analysis processing unit 51 and a control unit 52;
the analysis processing unit 51 is configured to determine whether a data voltage provided to the pixel circuits of the first a row included in the display panel included in the m-th frame of display data has periodicity, and set a dummy data voltage according to a determination result; m is a positive integer; a is a positive integer, a is greater than the predetermined number of rows;
the control unit 52 is configured to control the dummy data voltage to be supplied to the data line during an mth dummy data voltage supply period.
When the driving module according to the embodiment of the present invention works, the analysis processing unit 51 sets the dummy data voltage according to a result of periodically determining whether the data voltage provided to the pixel circuits in the first a row included in the display panel and included in the mth frame of display data has a periodicity, and the control unit 52 provides the dummy data voltage to the data line in the mth dummy data voltage providing time period, so that the charging effect of the pixel circuit in the first row and the charging effect of the pixel circuits in the non-first row and the gray-scale pixel circuits can be consistent at the display time of the (m + 1) th frame of picture, and further the luminance of the pixel circuit in the first row and the luminance of the pixel circuits in the non-first row and the gray-scale pixel circuits are consistent, thereby solving the problem that the first row is brighter and the first row is darker.
Optionally, as shown in fig. 6, on the basis of the embodiment of the driving module shown in fig. 5, the driving module according to the embodiment of the present invention further includes a storage unit 53;
the storage unit 53 is electrically connected to the analysis processing unit 51 and the control unit 52, respectively, and is configured to store the dummy data voltage.
According to a specific embodiment, the analysis processing unit is specifically configured to set the data voltage supplied to the pixel circuit of the nth row in the display data of the mth frame as the dummy data voltage when it is determined that the data voltage has periodicity; when the data voltage is judged not to have periodicity, setting the data voltage provided to the pixel circuits in the first row in the display data of the mth frame as a pseudo data voltage;
n is a ratio between a period of the data voltage variation and a line scanning time, and n is a positive integer.
According to another specific embodiment, the analysis processing unit is specifically configured to set, as the dummy data voltage, the data voltage provided to the row a pixel circuit in the m-th frame of display data when it is determined that the data voltages provided to the pixel circuits in the row a in the B display areas have periodicity respectively and the periods of the data voltage changes corresponding to each display area are not equal;
a is a positive integer, A is the least common multiple of the ratios corresponding to the B display regions;
the ratio corresponding to the b-th display area is the ratio between the period of the data voltage variation supplied to the pixel circuits of the previous a row and one row scanning time in the b-th display area;
b is an integer greater than 1, B is a positive integer less than or equal to B.
According to another specific embodiment, the analysis processing unit is specifically configured to set dummy data voltages for B display areas when it is determined that the data voltages provided to the pixel circuits in the first a row in the B display areas respectively have periodicity and the periods of the data voltage variation corresponding to each display area are not equal; b is an integer greater than 1.
The display device provided by the embodiment of the invention comprises the driving module.
In a specific implementation, the display device includes a timing controller, and the analysis processing unit is disposed in the timing controller.
In specific implementation, an analysis processing unit and a storage unit are added behind a data conversion module in a TCON (timing controller); the analysis processing unit and the storage unit can be communicated with each other, namely the analysis processing unit can store data in the storage unit and can also call the data in the data storage unit; the analysis processing unit is integrated in the TCON, and the storage unit can be integrated in the TCON, and can also be integrated in Flash or be independently arranged.
As shown in fig. 7, the display panel according to the embodiment of the present invention includes a timing controller 70;
the timing controller 70 includes a signal receiving unit 71, a signal converting unit 72, an analyzing processing unit 51, and a signal transmitting unit 73; the analysis processing unit 51 is electrically connected with the storage unit 53;
the signal receiving unit 71 is configured to receive Vby1(Vby1 is a serialization interface technology for video signal transmission) signals;
the signal conversion unit 72 is used for converting the Vby1 signal into a USIT (USIT is a universal serial interface) signal;
the analysis processing unit 51 can analyze and process signal data besides normally receiving and transmitting data;
the main functions of the analysis processing unit 51 are represented by the following two aspects:
firstly, when receiving the m-th frame USIT data, the analysis processing unit 51 analyzes whether the frame initial a-line USIT data (a can be set by software) has line periodicity; if the line periodicity exists, recording the period as n and storing the nth data of the frame in the storage unit 53; if there is no line periodicity, then set n to 1 and store the first line data of the frame in the storage unit 53;
second, when the USIT data of the (m + 1) th frame arrives, the analysis processing unit 51 may call the data in the storage unit 53 (i.e., the nth row data of the (m) th frame) and insert it in a dummy data voltage manner before the first row data of the USIT signal of the (m + 1) th frame.
In an embodiment of the present invention, the USIT data is a data voltage.
In the embodiment of the present invention, the embodiment of the display panel shown in fig. 7 may be a 65-inch 8K display panel, but is not limited thereto.
As shown in fig. 8, a schematic diagram of a workflow of the display panel according to the embodiment of the present invention is shown with a start time or a screen switching time as a starting point; after the signal conversion unit 72 in the TCON converts the Vby1 signal into a USIT signal, the USIT signal is transmitted to the analysis processing unit 51; after receiving the first frame of USIT data, the analysis processing unit 51 analyzes the a-line data before the frame of data, and analyzes whether the a-line data before the frame has line periodicity;
after analyzing the line periodicity, the analysis processing unit 51 does two actions simultaneously: first, the frame data is sent to the signal sending unit 73 so as to be sent to the source driver and the rear end thereof; recording the minimum line period of a line data before the first frame as n, and sending the nth line data of the first frame to the storage unit 53 for storage;
here, the cycle n is recorded and the nth data is stored in two cases: if the a-th row data in the first frame exists in the row periodicity, recording the minimum row period value as n and sending the nth row data to the storage unit 53 for temporary storage; if a line of data before the first frame has no line periodicity, recording n as 1, and sending the first line of data to the storage unit 53 for temporary storage;
after the above actions are completed, the analysis processing unit 51 receives the second frame data sent by the signal conversion unit 72, and calls up the data in the storage unit 53 (i.e., the nth data of the first frame). And after receiving the second frame data, continuously analyzing whether the previous a row data of the frame data has row periodicity.
After analyzing the a-line data before the second frame, the analysis processing unit 51 still performs two actions at the same time: first, a number of lines of dummy data voltages are inserted before the first line of data of the frame (second frame), the inserted dummy data voltages use the data called in the memory unit 53, that is, the nth line of data of the first frame, and the number of lines of the inserted dummy data voltages is determined by the number of precharge lines of the display product; outputting second frame data (data of inserting the dummy data voltage before the first line) after the interpolation is finished; secondly, recording a minimum line period n of a line data before the second frame (if no line period exists, n is 1), and temporarily storing the nth line data of the second frame to the storage unit 53, so that the third frame data can call interpolation;
the subsequent processes are analogized in turn; therefore, proper dummy data voltage can be inserted before the data of all frames except the first frame data, so that the brightness of the pixels of the first row is improved, and the problems that the first row is too bright and the first row is too dark are solved.
The first frame data is at the starting-up time or the picture switching time, and the frame information is basically invisible information and can be ignored. Of course, in the prior art, a signal conversion unit in the TCON has a certain time delay (generally about seven rows of data time) during receiving and transmitting data, and if the time delay can reach a large value (it is ensured that the number of data rows that can be analyzed and processed by the time delay is greater than a, that is, the time delay is sufficient for the analysis processing unit 51 to analyze and process the row periodicity of a row of data before the first frame, the value of a is adjustable, but the value is not too small, and is recommended to be more than 20), a suitable dummy data voltage can be inserted before the first frame of data.
In the above description, the analyzing unit 51 and the storing unit 53 are used to analyze, process and store the USIT signal, and their positions are placed before the signal converting module, so that they can analyze, process and store Vby1 the signal to achieve the same effect. In addition, the application range of the scheme of the invention is far wider than that, and the scheme of the invention is not limited by various signal types, panel sizes, pixel inversion modes and the like.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A driving method is applied to a display panel, the display panel comprises a plurality of rows of grid lines, a plurality of columns of data lines and a plurality of rows and a plurality of columns of pixel circuits, and the driving method comprises the following steps:
judging whether the data voltage provided to the pixel circuits of the first a row included in the display panel and included in the display data of the mth frame has periodicity or not, and setting a dummy data voltage according to a judgment result; m is a positive integer; a is a positive integer, a is greater than the predetermined number of rows;
supplying the dummy data voltage to the data line during an mth dummy data voltage supply period.
2. The driving method according to claim 1, wherein the setting the dummy data voltage according to the determination result comprises:
when the data voltage is judged to have periodicity, setting the data voltage provided to the pixel circuit of the nth row in the display data of the mth frame as a pseudo data voltage; when the data voltage is judged not to have periodicity, setting the data voltage provided to the pixel circuits in the first row in the display data of the mth frame as a pseudo data voltage;
n is a ratio between a period of the data voltage variation and a line scanning time, and n is a positive integer.
3. The driving method according to claim 1, wherein the setting the dummy data voltage according to the determination result comprises:
when the data voltages provided to the pixel circuits of the first a row in B display areas are judged to have periodicity respectively and the periods of the data voltage change corresponding to each display area are not equal, the data voltage provided to the pixel circuits of the A row in the m-th frame of display data is set as a pseudo data voltage;
a is a positive integer, A is the least common multiple of the ratios corresponding to the B display regions;
the ratio corresponding to the b-th display area is the ratio between the period of the data voltage variation supplied to the pixel circuits of the previous a row and one row scanning time in the b-th display area;
b is an integer greater than 1, B is a positive integer less than or equal to B.
4. The driving method according to claim 1, wherein the setting the dummy data voltage according to the determination result comprises:
when it is judged that the data voltages provided to the pixel circuits of the former a rows in the B display areas are respectively periodic and the periods of the data voltage changes corresponding to each display area are not equal, respectively setting dummy data voltages for the B display areas; b is an integer greater than 1.
5. The driving method according to claim 4, wherein the step of setting the dummy data voltages for the B display regions respectively comprises:
when it is determined that the data voltages supplied to the pixel circuits of the first a row in the b-th display area have periodicity, setting the data voltages supplied to the pixel circuits of the n-th row in the b-th display area in the display data of the m-th frame to dummy data voltages corresponding to the b-th display area; b is a positive integer less than or equal to B;
n is the ratio of the period of the change of the data voltage provided to the pixel circuits of the previous a rows in the b-th display area to the scanning time of one row, and n is a positive integer.
6. The driving method according to claim 4 or 5, wherein the step of supplying the dummy data voltage to the data line specifically includes:
the dummy data voltage corresponding to the b-th display area is supplied to the data line located in the b-th display area.
7. The driving method of any one of claims 1 to 5, wherein the m-th dummy data voltage supplying period lasts for a time equal to a difference between a time for which the gate line is once opened and a one-row scanning time;
the mth dummy data voltage supply period is immediately adjacent to a first row data voltage supply period included in the m +1 th frame screen display time;
the period of time in which the first row gate line is turned on in the (m + 1) th frame picture display time includes the m-th dummy data voltage supply period and the first row data voltage supply period, which are sequentially set.
8. A driving module is characterized by comprising an analysis processing unit and a control unit;
the analysis processing unit is used for judging whether the data voltage provided to the pixel circuits of the first a rows included in the display panel and included in the display data of the mth frame has periodicity or not and setting a pseudo data voltage according to a judgment result; m is a positive integer; a is a positive integer, a is greater than the predetermined number of rows;
the control unit is used for controlling the supply of the dummy data voltage to the data line in the mth dummy data voltage supply time period.
9. The drive module of claim 8, further comprising a memory cell;
the storage unit is used for storing the pseudo data voltage.
10. The driving module according to claim 8, wherein the analysis processing unit is specifically configured to set a data voltage provided to the pixel circuit in the nth row in the display data of the mth frame as a dummy data voltage when it is determined that the data voltage has periodicity; when the data voltage is judged not to have periodicity, setting the data voltage provided to the pixel circuits in the first row in the display data of the mth frame as a pseudo data voltage;
n is a ratio between a period of the data voltage variation and a line scanning time, and n is a positive integer.
11. The driving module according to claim 8, wherein the analysis processing unit is specifically configured to set the data voltage provided to the row a pixel circuit in the m-th frame of display data to the dummy data voltage when it is determined that the data voltages provided to the row a pixel circuits in the B display regions have periodicity respectively and the periods of the data voltage changes corresponding to each display region are not equal;
a is a positive integer, A is the least common multiple of the ratios corresponding to the B display regions;
the ratio corresponding to the b-th display area is the ratio between the period of the data voltage variation supplied to the pixel circuits of the previous a row and one row scanning time in the b-th display area;
b is an integer greater than 1, B is a positive integer less than or equal to B.
12. The driving module according to claim 8, wherein the analysis processing unit is specifically configured to set dummy data voltages for the B display regions when it is determined that the data voltages provided to the pixel circuits in the a-row in the B display regions respectively have periodicity and the periods of the data voltage changes corresponding to each display region are not equal; b is an integer greater than 1.
13. A display device comprising a driving module according to any one of claims 8 to 12.
14. The display device according to claim 13, wherein the display device includes a timing controller, and the analysis processing unit is provided in the timing controller.
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