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CN112000290B - Nor flash erasure interference correction method and device - Google Patents

Nor flash erasure interference correction method and device Download PDF

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Publication number
CN112000290B
CN112000290B CN202010849632.0A CN202010849632A CN112000290B CN 112000290 B CN112000290 B CN 112000290B CN 202010849632 A CN202010849632 A CN 202010849632A CN 112000290 B CN112000290 B CN 112000290B
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block
flash
correction
array
physical storage
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CN112000290A (en
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王志刚
李弦
叶谦
王少龙
张文豪
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Zhuhai Chuangfeixin Technology Co Ltd
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Zhuhai Chuangfeixin Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

The invention provides a Nor flash erasure interference correction method and device. Comprising the following steps: and under the condition that the power-on signal of the flash memory chip is in a power-on reset signal, when the Nor flash array blocks of the nonvolatile flash memory in the physical memory array are subjected to block erase operation for M times, performing erase interference confirmation and correction on all the Nor flash array blocks. And when the block erasing operation is performed on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the remaining N-M times, performing erasing interference confirmation and correction on the Nor flash array blocks in the selected physical storage array. In the scheme, erasing interference confirmation and correction are carried out on all Nor flash array blocks at least M times, and interference confirmation and correction are carried out on the selected Nor flash array blocks every time in the remaining N-M times. To reduce the time and power consumption of the overall erase operation and to avoid overwriting of stored data.

Description

Nor flash erasure interference correction method and device
Technical Field
The present invention relates to the field of flash memory technologies, and in particular, to a method and apparatus for correcting erase disturbance of nonvolatile flash memory (Nor flash).
Background
With the rapid development of portable electronic products, particularly after the process feature size is smaller than 65nnm, the floating gate type flash memory chip storage area is generally placed in a physical concentrated manner to save the chip area, so as to form a physical storage matrix, and logically, each physical storage matrix is divided into a plurality of Nor flash array blocks constructed based on the floating gate technology. Since different Nor flash array blocks are located on the same P-type substrate (PWELL), when one Nor flash array block in the same physical memory array is erased, because the source region and the P-well are connected with each other, the residual Nor flash array blocks in the same physical memory array are disturbed by drain voltage and P-well voltage.
In order to avoid the above-mentioned influence, when an erase operation is performed on a Nor flash array block, an erase disturb correction algorithm is used to detect all memory cells in the Nor flash array block which are not selected to be erased in the same physical memory array, and determine whether each memory cell storing data "0" is disturbed, if so, disturb correction is performed by program refresh.
At present, an erase disturb correction mode in the prior art is often adopted to perform erase disturb confirmation and correction, and one is to perform disturb detection confirmation and correction on each memory cell in all Nor flash array blocks which are not selected to be erased in the same physical memory array. Since it can take a long time to verify and correct erase disturbances, the sum of the time consumed by other operations in the Nor flash array block erase flow is far exceeded. Therefore, the time consumption of the whole erasing operation is increased, and the power consumption of the whole erasing operation is also increased. Alternatively, a random number seed is generated by arranging a random number generation circuit module; in the process of confirming and correcting the erasing interference, a random number seed is used as an address to select one logic storage block in the physical storage array, and the erasing interference is confirmed and corrected. The random number seed of the random number generation circuit module is easy to be in a non-random condition, so that data stored in the physical array is easy to rewrite.
In summary, the existing Nor flash erase interference and correction method has the problems that the time consumption of the whole erase operation is long, the power consumption of the whole erase operation is large, and the background data in the physical array is easy to rewrite.
Disclosure of Invention
In view of the above, the embodiments of the present invention provide a method and an apparatus for correcting Nor flash erase interference, so as to solve the problems in the prior art that the overall erase operation is long in time consumption, the overall erase operation consumes large power, and the data stored in the physical array is easy to be rewritten.
In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:
the embodiment of the invention discloses a Nor flash erasure interference correction method, which comprises the following steps:
when the power-on signal of the flash memory chip is in a power-on reset signal, performing erase interference confirmation and correction on all Nor flash array blocks when performing block erase operation on the Nor flash array blocks of nonvolatile flash memory in a physical memory array for M times, wherein the value of M is a positive integer greater than or equal to 1 and less than N, and the value of N is a positive integer greater than 2;
and when the block erasing operation is performed on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the remaining N-M times, performing erasing interference confirmation and correction on the Nor flash array blocks in the selected physical storage array.
Optionally, when performing the block erase operation on the non-volatile flash memory Nor flash array blocks in the physical storage array M times, performing erase disturbance confirmation and correction on all the Nor flash array blocks includes:
when performing block erase operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the 1 st time, performing erase disturbance confirmation and correction on all the Nor flash array blocks;
and when the Nor flash array blocks in the physical storage array are subjected to block erase operation for the rest N-M times, performing erase disturbance confirmation and correction on the Nor flash array blocks in the selected physical storage array, wherein the erase disturbance confirmation and correction comprises the following steps:
when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the remaining N-1 times, determining block addresses to be subjected to erasing interference confirmation and correction based on a preset rule;
and performing erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
Optionally, when performing a block erase operation on a non-volatile flash Nor flash array block in the physical storage array for the remaining N-1 times, determining a block address to be subjected to erase disturb confirmation and correction based on a preset rule includes:
when performing block erasing operation on a non-volatile flash memory Nor flash array block in a physical storage array for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on a first address block in a preset physical storage array or a next address block of the erased Nor flash array block;
And adding 1 on the basis of the block address of the Nor flash array block selected last time when the block erasing operation is carried out on the Nor flash array block of the nonvolatile flash memory in the physical memory array for each of the remaining N-2 times, and determining the block address to be subjected to the current erasing interference confirmation and correction.
Optionally, when performing the block erase operation on the non-volatile flash memory Nor flash array blocks in the physical storage array M times, performing erase disturbance confirmation and correction on all the Nor flash array blocks includes:
when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the nth time, performing erasing interference confirmation and correction on all the Nor flash array blocks, wherein the value of N is greater than or equal to 1 and less than or equal to N;
and when the Nor flash array blocks in the physical storage array are subjected to block erase operation for the rest N-M times, performing erase disturbance confirmation and correction on the Nor flash array blocks in the selected physical storage array, wherein the erase disturbance confirmation and correction comprises the following steps:
when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the remaining N-1 times, determining block addresses to be subjected to erasing interference confirmation and correction based on a preset rule;
And performing erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
Optionally, when performing the block erase operation on the non-volatile flash memory Nor flash array blocks in the physical storage array M times, performing erase disturbance confirmation and correction on all the Nor flash array blocks includes:
when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the first m times, performing erasing interference confirmation and correction on all the Nor flash array blocks, wherein the value of m is greater than 1 and less than N;
and when the Nor flash array blocks in the physical storage array are subjected to block erase operation for the rest N-M times, performing erase disturbance confirmation and correction on the Nor flash array blocks in the selected physical storage array, wherein the erase disturbance confirmation and correction comprises the following steps:
when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the rest N-m times, determining block addresses to be subjected to erasing interference confirmation and correction based on a preset rule;
and performing erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
The second aspect of the embodiment of the invention discloses a Nor flash erasure interference correction device, which comprises:
The first correction module is used for carrying out erasure interference confirmation and correction on all Nor flash array blocks when carrying out block erasure operation on the Nor flash array blocks of nonvolatile flash memories in the physical memory array for M times under the condition that a power-on signal of the flash memory chip is in a power-on reset signal, wherein the value of M is a positive integer greater than or equal to 1 and less than N, and the value of N is a positive integer greater than 2;
and the second correction module is used for carrying out erasure interference confirmation and correction on the Nor flash array blocks in the selected physical storage array when the residual N-M times of block erasure operation are carried out on the Nor flash array blocks in the physical storage array.
Optionally, the first correction module is specifically configured to: when performing block erase operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the 1 st time, performing erase disturbance confirmation and correction on all the Nor flash array blocks;
the second correction module comprises a first address determination unit and a first correction unit;
the first address determining unit is used for determining a block address to be subjected to erasure interference confirmation and correction based on a preset rule when the block erasure operation is performed on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the remaining N-1 times;
And the first correction unit is used for carrying out erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
Optionally, the first address determining unit is specifically configured to: when performing block erasing operation on a non-volatile flash memory Nor flash array block in a physical storage array for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on a first address block in a preset physical storage array or a next address block of the erased Nor flash array block; and adding 1 on the basis of the block address of the Nor flash array block selected last time when the block erasing operation is carried out on the Nor flash array block of the nonvolatile flash memory in the physical memory array for each of the remaining N-2 times, and determining the block address to be subjected to the current erasing interference confirmation and correction.
Optionally, the first correction module is specifically configured to: when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the nth time, performing erasing interference confirmation and correction on all the Nor flash array blocks, wherein the value of N is greater than or equal to 1 and less than or equal to N;
the second correction module comprises a second address determination unit and a second correction unit;
The second address determining unit is configured to determine, based on a preset rule, a block address to be subjected to erase disturb confirmation and correction when performing a block erase operation on a non-volatile flash Nor flash array block in the physical storage array for the remaining N-1 times;
and the second correction unit is used for carrying out erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
Optionally, the first correction module is specifically configured to: when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the first M times, performing erasing interference confirmation and correction on all the Nor flash array blocks, wherein the value of M is greater than 1 and less than or equal to M;
the second correction module comprises a third address determination unit and a third correction unit;
the third address determining unit is configured to determine, based on a preset rule, a block address to be subjected to erase disturb confirmation and correction when performing a block erase operation on a non-volatile flash Nor flash array block in the physical storage array for the remaining N-m times;
and the third correction unit is used for carrying out erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
Based on the method and the device for correcting Nor flash erase interference provided by the embodiment of the invention. The method comprises the following steps: and under the condition that the power-on signal of the flash memory chip is in a power-on reset signal, when the Nor flash array blocks of the nonvolatile flash memory in the physical memory array are subjected to block erase operation for M times, performing erase interference confirmation and correction on all the Nor flash array blocks. Wherein, the value of M is a positive integer greater than or equal to 1 and less than N, and the value of N is a positive integer greater than 2. And when the block erasing operation is performed on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the remaining N-M times, performing erasing interference confirmation and correction on the Nor flash array blocks in the selected physical storage array. In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in a power-on reset signal, at least one erase disturbance confirmation and correction are carried out on all the Nor flash array blocks, and then in the remaining times of carrying out block erase operation on the Nor flash array blocks, each time, the erase disturbance confirmation and correction are carried out on the selected Nor flash array blocks. When the Nor flash array block is subjected to block erase operation, time consumption of the whole erase operation and power consumption of the whole erase operation are reduced, and stored data can be prevented from being rewritten.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a block erase operation;
FIG. 2 is a schematic flow chart of a Nor flash erase disturb correction method according to an embodiment of the present invention;
FIG. 3 is a schematic flow chart of another Nor flash erase disturb correction method according to an embodiment of the present invention;
FIG. 4 is a schematic flow chart of another Nor flash erase disturb correction method according to an embodiment of the present invention;
FIG. 5 is a schematic flow chart of another Nor flash erase disturb correction method according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a device for correcting Nor flash erase disturbance according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Currently, a Nor flash array block based on a floating gate technology mainly comprises a substrate, and a source end, a drain end, a gate end and a floating gate which are arranged on the substrate.
In order to save the area of the Nor flash memory chip, the Nor flash memory area is usually placed in a physical concentration mode to form a memory matrix, and is logically divided into a plurality of Nor flash array blocks. Therefore, the Nor flash array blocks in the physical memory array are connected through the drain terminal and the source terminal.
The programming operation of the Nor flash array block is based on the CHE principle: the source terminal and the substrate are biased at 0V, the drain terminal is biased at 5V, the control gate terminal is biased at 10V, and the drain terminal hot electrons are stored in the floating gate through the tunneling oxide layer. At this time, the threshold voltage of the memory cell increases, representing writing of "0" data.
The erase operation of the Nor flash array block is based on FN tunneling principles: the source end and the drain end are suspended, the substrate is biased at high voltage of 10V, the control gate end is biased at negative voltage of-8V, electrons stored in the floating gate tunnel to the substrate based on FN tunneling mechanism, and the floating gate electrons are erased. At this time, the threshold voltage of the memory cell is reduced, representing that "1" data is erased back.
The current block erase operation for a Nor flash array block in a physical storage array in a flash memory chip is shown in FIG. 1, and mainly comprises the following steps:
s101: and receiving an erase command of the Nor flash array block.
S102: and pre-programming the selected Nor flash array block.
S103: judging whether the pre-programming is completed or not, if so, executing S104; if not, the process continues to S102.
And S102, programming all memory cells of the selected Nor flash array block, and judging the states of the memory cells in the pre-programming process, namely S103, judging whether the pre-programming is completed or not until all the memory cells are programmed to the 0 state.
S104: and performing block erasing operation on the selected Nor flash array block.
S105: whether over-erasure is performed is checked, and if not, S106 is executed, and if yes, S107 is executed.
S106: an over-erase auto-correction operation is performed.
S107: confirming whether the block erase operation is completed, if so, executing S108; if not, execution continues with S107.
S108: a soft programming operation is performed.
S109: determining whether the soft programming operation is completed, and if so, executing S110; if not, the process continues to S109.
S110: an erasure-and-disturb correction operation is performed.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in a power-on reset signal, at least one erase disturbance confirmation and correction are carried out on all the Nor flash array blocks, and then in the remaining times of carrying out block erase operation on the Nor flash array blocks, each time, the erase disturbance confirmation and correction are carried out on the selected Nor flash array blocks. When the Nor flash array block is subjected to block erase operation, time consumption of the whole erase operation and power consumption of the whole erase operation are reduced, and stored data can be prevented from being rewritten. The specific implementation is illustrated in detail by the following examples.
Referring to fig. 2, a flow chart of a method for correcting a norflash erase disturbance is shown in an embodiment of the present invention; the Nor flash erasure interference correction method comprises the following steps:
step S201: detecting a power-on signal of the flash memory chip, if the power-on signal of the flash memory chip is in a power-on reset signal, executing step S202 to step S203, and if the power-on signal of the flash memory chip is not in the power-on reset signal, continuing to execute step S201.
In the embodiment of the invention, the Nor flash memory chip can only store program codes or data under the condition of no power supply, and can not carry out block erasing operation on the Nor flash array blocks of the nonvolatile flash memory, so that the Nor flash memory chip is required to be powered by the power supply when the Nor flash array blocks of the physical memory array are subjected to block erasing operation. In the specific implementation process of step S201, it is determined whether a power supply is supplying power to the flash memory chip, if so, step S202 to step S203 are executed if the power-on signal of the flash memory chip is a power-on reset signal, if not, it is determined that no power supply is supplying power to the flash memory chip, and whether the power supply is supplying power to the flash memory chip is continuously detected, that is, step S201 is executed again.
Step S202: and when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for M times, carrying out erasing interference confirmation and correction on all the Nor flash array blocks.
In step S202, the value of M is a positive integer greater than or equal to 1 and less than N, and the value of N is a positive integer greater than 2.
In the specific implementation process of step S202, when performing a block erase operation on non-volatile flash memory or flash array blocks in a physical storage array, it is necessary to perform erase disturb verification and correction on all the Nor flash array blocks at least once.
Optionally, in a specific implementation, as shown in fig. 1, the processes in the block erase operation include a pre-program process, a block erase process, an over-erase auto-correction process, a soft program process, and an erase disturbance correction process. When the erase disturbance confirmation and correction is performed on all the Nor flash array blocks, that is, the erase disturbance correction flow is executed, the erase disturbance confirmation and correction can be performed on all the Nor flash array blocks by using an erase disturbance correction algorithm in a programming refreshing mode.
It should be noted that M refers to the number of times of performing erase disturb verification and correction on all the norflash array blocks, and N refers to the total number of times of performing erase disturb verification and correction. Wherein M may be 1 or a positive integer smaller than N.
In the embodiment of the invention, in order to prevent erase interference caused by repeated power-off and power-on to erase the same Nor flash array block, when M is taken as 1, two conditions of performing block erase operation on all Nor flash array blocks can exist.
First kind: the 1 st block erase operation after each power-up is to perform erase disturb verification and correction on all Nor flash array blocks.
Second kind: and any one of the total times of block erase operation after each power-up, namely, the nth block erase operation is to perform erase disturbance confirmation and correction on all Nor flash array blocks.
It should be noted that, when n is 1, the second case of performing the block erase operation on all the nors flash array blocks may be the same as the first case of performing the block erase operation on all the nors flash array blocks.
When M is a positive integer greater than 1, there is also a case where a block erase operation is performed on all the nors flash array blocks.
Third kind: the first m block erase operations after each power-up are to perform erase disturb verification and correction on all Nor flash array blocks.
Step S203: and when the block erasing operation is performed on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the remaining N-M times, performing erasing interference confirmation and correction on the Nor flash array blocks in the selected physical storage array.
In step S203, N-M refers to the remaining number of times of performing erase disturb verification and correction on the selected Nor flash array block.
In the specific implementation of step S203, among the remaining N-M times of block erase operations, each time a block erase operation is performed, first, one Nor flash array block performing the block erase operation is selected. And then, performing erasure disturbance confirmation and correction on the selected Nor flash array block. In the remaining N-M times of block erasing operation, the Nor flash array blocks in the physical storage array are subjected to interference confirmation and correction.
Optionally, in a specific implementation, as shown in fig. 1, the processes in the block erase operation include a pre-program process, a block erase process, an over-erase auto-correction process, a soft program process, and an erase disturbance correction process. For the selected Nor flash array block, that is, when the erase disturbance correction flow is executed on the selected Nor flash array block, the erase disturbance correction algorithm can also be utilized to confirm and correct the erase disturbance of the selected Nor flash array block in a programming refreshing mode.
It should be noted that, if the 1 st block erase operation after each power-up is to perform erase disturb verification and correction on all the nors flash array blocks, or the first m block erase operations after each power-up are to perform erase disturb verification and correction on all the nors flash array blocks, the execution sequence of step S202 and step S203 is as described above, and if the nth block erase operation after each power-up is to perform erase disturb verification and correction on all the nors flash array blocks, and n is not equal to 1, the execution sequence of step S202 and step S203 is to execute step S203 first, and then execute step S202.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in a power-on reset signal, when the non-volatile flash Nor flash array blocks in the physical storage array are subjected to block erase operation for M times, all the Nor flash array blocks are subjected to erase interference confirmation and correction, and when the non-volatile flash Nor flash array blocks in the physical storage array are subjected to block erase operation for the remaining N-M times, the Nor flash array blocks in the selected physical storage array are subjected to erase interference confirmation and correction. When the Nor flash array block is subjected to block erase operation, time consumption of the whole erase operation and power consumption of the whole erase operation are reduced, and stored data can be prevented from being rewritten.
The following describes the method for correcting the erase disturbance of the Nor flash array according to the present application, taking the determination of the 1 st block erase operation after each power-up as an example of performing the erase disturbance confirmation and correction on all the Nor flash array blocks. As shown in fig. 3, a flow chart of a method for correcting a Nor flash erase disturb disclosed in the embodiment of the present application is shown, where the method for correcting a Nor flash erase disturb includes:
step S301: detecting a power-on signal of the flash memory chip, and executing the steps S302 to S303 when the power-on signal of the flash memory chip is in a power-on reset signal, if not, continuing to execute the step S301.
It should be noted that the implementation procedure of step S301 is the same as that of step S201 described above, and reference may be made to each other.
Step S302: and when the Nor flash array blocks of the nonvolatile flash memories in the physical storage array are subjected to block erasing operation for the 1 st time, all the Nor flash array blocks are subjected to erasing interference confirmation and correction.
In the specific implementation process of step S302, the number of times of performing a block erase operation on a non-volatile flash memory norflash array block in the physical storage array is determined, and when the number of times of performing a block erase operation on a non-volatile flash memory norflash array block in the physical storage array is determined to be 1 st, when performing a block erase operation on a non-volatile flash memory norflash array block in the physical storage array, performing erase interference confirmation and correction on all the norflash array blocks.
Step S303: and when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memories in the physical storage array for the remaining N-1 times, determining the block address to be subjected to erasing interference confirmation and correction based on a preset rule.
In the embodiment of the invention, the storage unit of the Nor flash is composed of the Nor flash array block, the Nor flash array block is composed of the pages, and the data is stored on the pages. Such as: the total capacity of the Nor flash is 256M, for a total of 2048 array blocks, each having 64 pages.
The Nor flash performs an erase operation in a block minimum unit.
In the specific implementation process of step S303, in the remaining N-1 times of block erase operations, each time a block erase operation is performed, a block address corresponding to a norflash array block to be performed with the block erase operation is selected by using a preset rule.
It should be noted that the preset rule refers to a first address block in a preset physical storage array or a next address block of an erased Nor flash array block.
Step S304: and performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address.
In the specific implementation step S304, the position of the selected Nor flash array block is determined based on the block address, and then the erase disturbance correction algorithm is utilized to perform erase disturbance confirmation and correction on the selected Nor flash array block in a programming refresh manner.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in the power-on reset signal, when the non-volatile flash Nor flash array blocks in the physical storage array are subjected to the block erase operation for the 1 st time, all the Nor flash array blocks are subjected to the erase interference confirmation and correction. And when the Nor flash array block is erased in each of the remaining N-1 times, determining a block address corresponding to the Nor flash array block to be subjected to block erase operation by utilizing a preset rule, and performing erase interference confirmation and correction on the selected Nor flash array block based on the block address. By the method, the Nor flash array block is subjected to block erase operation, so that time consumption of the whole erase operation and power consumption of the whole erase operation can be reduced, and stored data can be prevented from being rewritten.
Based on the above-mentioned Nor flash erase disturb correction method, when the above-mentioned step S303 is executed to perform the block erase operation on the nonvolatile Nor flash array blocks in the physical storage array for the remaining N-1 times, in the process of determining the block address to be subjected to erase disturb confirmation and correction based on the preset rule, there are two embodiments for determining the block address to be subjected to erase disturb confirmation and correction.
In an embodiment of the present invention, a process of determining a block address to be subjected to erase disturb confirmation and correction based on a preset rule includes the following steps:
step S11: and when the non-volatile flash memory Nor flash array block in the physical storage array is subjected to block erasing operation for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on a head address block in the preset physical storage array.
In the specific implementation step S11, when performing the block erase operation on the non-volatile flash memory norflash array block in the physical storage array for the 2 nd time, a block address corresponding to the first address block in the preset physical storage array is calculated by using a calculation formula of block address=block size×block number, and the calculated block address is set as a block address to be subjected to the erase disturbance confirmation and correction, so that the erase disturbance confirmation and correction operation is performed on the first address block according to the block address to be subjected to the erase disturbance confirmation and correction.
It should be noted that, the first address block in the physical storage array is arbitrarily set. For example, the 150 th Nor flash array block may be set as the first address block.
Such as: the size of each array block is 128K, and the address of the 150 th nors flash array block is 128k×150=4b00.
Step S12: and adding 1 on the basis of the block address of the Nor flash array block selected last time when the block erasing operation is carried out on the Nor flash array block of the nonvolatile flash memory in the physical memory array for each of the remaining N-2 times, and determining the block address to be subjected to the current erasing interference confirmation and correction.
In the specific implementation step S12, in the remaining times of performing block erase operation on the non-volatile flash norflash array blocks in the physical storage array, each time of performing block erase operation on the non-volatile flash norflash array blocks in the physical storage array needs to generate a current block address to be subjected to erase disturb confirmation and correction by adding 1 on the basis of the block address of the norflash array block selected last time by using the internal counter of the norflash chip.
Such as: and if the number of the block erasing operation on the non-volatile flash Nor flash array block in the physical storage array is 3, generating a block address to be subjected to the current erasing interference confirmation and correction by utilizing the internal counter of the Nor flash chip on the basis of the block address of the Nor flash array block selected for the 2 nd time.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in the power-on reset signal, when the non-volatile flash Nor flash array blocks in the physical storage array are subjected to the block erase operation for the 1 st time, all the Nor flash array blocks are subjected to the erase interference confirmation and correction. When performing block erasing operation on a non-volatile flash memory Nor flash array block in a physical storage array for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on a first address block in a preset physical storage array; and adding 1 on the basis of the block address of the Nor flash array block selected last time when the Nor flash array block is erased for each of the remaining N-2 times, and determining the block address to be subjected to erase disturbance confirmation and correction currently. And performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address. By the method, the Nor flash array block is subjected to block erase operation, so that time consumption of the whole erase operation and power consumption of the whole erase operation can be reduced, and stored data can be prevented from being rewritten.
In another embodiment of the present invention, the process of determining the block address to be subjected to the erase disturb confirmation and correction based on the preset rule includes the following steps:
step S21: and when the non-volatile flash memory Nor flash array block in the physical storage array is subjected to block erasing operation for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on the next address block of the erased Nor flash array block.
In the specific implementation process of step S21, a norflash array block for performing a block erase operation is determined, and any one of the norflash array blocks for performing the block erase operation is selected, that is, a block address corresponding to a next norflash array block of the erased norflash array block is a block address to be subjected to erase disturb confirmation and correction.
Specifically, a block address corresponding to a next Nor flash array block of the selected Nor flash array block for executing the block erase operation is calculated by using a calculation formula of block address = block size x block number, so as to obtain a block address to be currently subjected to erase disturbance confirmation and correction.
For example: the Nor flash array blocks determined to perform the block erase operation are a 15 th Nor flash array block, a 150 th Nor flash array block, and a 1100 th Nor flash array block. And selecting the next Nor flash array block of the 150 th Nor flash array block for executing the block erasing operation, namely the 151 th Nor flash array block. And calculating the block address corresponding to the 151Nor flash array block by using a calculation formula of block address = block size x block number to obtain the current block address to be subjected to erasure interference confirmation and correction as 4B80.
Step S22: and adding 1 on the basis of the block address of the Nor flash array block selected last time when the block erasing operation is carried out on the Nor flash array block of the nonvolatile flash memory in the physical memory array for each of the remaining N-2 times, and determining the block address to be subjected to the current erasing interference confirmation and correction.
It should be noted that the specific implementation procedure of step S22 is the same as that of step S12 described above, and reference may be made to each other.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in the power-on reset signal, when the non-volatile flash Nor flash array blocks in the physical storage array are subjected to the block erase operation for the 1 st time, all the Nor flash array blocks are subjected to the erase interference confirmation and correction. When performing block erasing operation on a non-volatile flash memory Nor flash array block in a physical storage array for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on the next address block of the erased Nor flash array block; and adding 1 on the basis of the block address of the Nor flash array block selected last time when the Nor flash array block is erased for each of the remaining N-2 times, and determining the block address to be subjected to erase disturbance confirmation and correction currently. And performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address. By the method, the Nor flash array block is subjected to block erase operation, so that time consumption of the whole erase operation and power consumption of the whole erase operation can be reduced, and stored data can be prevented from being rewritten.
The method for correcting the Nor flash erase disturb disclosed by the application is described below by taking the example of determining that the n-th block erase operation is to perform erase disturb confirmation and correction on all the Nor flash array blocks. As shown in fig. 4, the embodiment of the application discloses a flow diagram of a method for correcting Nor flash erase interference, which comprises the following steps:
step S401: detecting a power-on signal of the flash memory chip, and executing the steps S402 to S403 when the power-on signal of the flash memory chip is in a power-on reset signal, and if not, continuing to execute the step S401.
It should be noted that the specific implementation procedure of step S402 is the same as the specific implementation procedure of step S401 shown above, and can be seen from each other.
Step S402: and when the Nor flash array blocks of the nonvolatile flash memories in the physical storage array are subjected to block erasing operation for the nth time, performing erasing interference confirmation and correction on all the Nor flash array blocks.
In step S402, N is equal to or greater than 1 and equal to or less than N.
In the specific implementation process of step S402, in the total number N of block erase operations performed on all the non-volatile flash nors flash array blocks in the physical storage array, it is determined that erase disturb verification and correction are performed on all the nors flash array blocks for the nth time. When the number of the current block erasing operation on the non-volatile flash memory Nor flash array blocks in the physical storage array is the nth time, performing erasing interference confirmation and correction on all the Nor flash array blocks.
Step S403: and when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memories in the physical storage array for the remaining N-1 times, determining the block address to be subjected to erasing interference confirmation and correction based on a preset rule.
In the embodiment of the invention, when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the rest N-1 times, only one Nor flash array block is erased, disturbed and confirmed and corrected at a time. In the specific implementation process of step S403, when performing the block erase operation on the non-volatile flash memory norflash array blocks in the physical storage array every time, a block address corresponding to the norflash array block to be subjected to the block erase operation may be selected based on a preset rule.
It should be noted that, the implementation process of step S403 may be the same as the implementation process of step S303, or the block address corresponding to a norflash array block to be subjected to the block erase operation may be selected through a preset rule when the remaining non-volatile flash memory norflash array block in the physical storage array is subjected to the block erase operation each time.
Step S404: and performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address.
It should be noted that the implementation process of step S404 and the implementation process of step S304 are the same and refer to each other.
In the embodiment of the application, when the power-on signal of the flash memory chip is in the power-on reset signal, the non-volatile flash Nor flash array blocks in the physical storage array are subjected to block erase operation for the nth time, and all the Nor flash array blocks are subjected to erase interference confirmation and correction. And when the Nor flash array block is erased every time in the remaining N-1 times, determining the block address to be subjected to erasure interference confirmation and correction currently by utilizing a preset rule. And performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address. By the method, the Nor flash array block is subjected to block erase operation, so that time consumption of the whole erase operation and power consumption of the whole erase operation can be reduced, and stored data can be prevented from being rewritten.
The method for correcting the Nor flash erase disturb disclosed in the present application will be described below by taking the example of determining that the erase disturb is confirmed and corrected for all the Nor flash array blocks in the previous m block erase operations. As shown in fig. 5, the embodiment of the present application further discloses a flow chart of another method for correcting the Nor flash erase disturb, where the method for correcting the Nor flash erase disturb includes:
Step S501: detecting a power-on signal of the flash memory chip, and executing step S502 to step S503 when the power-on signal of the flash memory chip is in a power-on reset signal, otherwise, continuing to execute step S501.
Step S502: and when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memories in the physical storage array for the first m times, carrying out erasing interference confirmation and correction on all the Nor flash array blocks.
In step S502, the value of m is greater than 1 and less than N.
In the specific implementation process of step S502, starting the block erase operation on the non-volatile flash memory norflash array blocks in the physical storage array 1 st time after the memory chip is powered up, and performing the erase interference confirmation and correction on all the norflash array blocks until the non-volatile flash memory norflash array blocks in the physical storage array m time after the memory chip is powered up.
Step S503: and when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memories in the physical storage array for the remaining N-m times, determining the block address to be subjected to erasing interference confirmation and correction based on a preset rule.
In the embodiment of the invention, when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for the rest N-m times, only one Nor flash array block is erased, disturbed and confirmed and corrected at a time.
Step S504: and performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address.
It should be noted that the specific implementation procedures of step S503 to step S504 are the same as the specific implementation procedures of step S403 to step S404, and can be seen from each other.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in a power-on reset signal, when the block erase operation is carried out on the non-volatile flash Nor flash array blocks in the physical storage array for the first m times, the erase interference confirmation and correction are carried out on all the Nor flash array blocks. And when the Nor flash array block is erased every time in the remaining N-m times, determining the block address to be subjected to erasure interference confirmation and correction currently by utilizing a preset rule. And performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address. By the method, the Nor flash array block is subjected to block erase operation, so that time consumption of the whole erase operation and power consumption of the whole erase operation can be reduced, and stored data can be prevented from being rewritten.
Based on the method for correcting the Nor flash erase interference disclosed by the embodiment of the invention, the embodiment of the invention correspondingly discloses a corresponding device for correcting the Nor flash erase interference. Fig. 6 is a schematic structural diagram of a device for correcting a Nor flash erase disturbance according to an embodiment of the present invention, where the device includes:
The first correction module 601 is configured to perform erase disturb confirmation and correction on all the Nor flash array blocks when performing a block erase operation on the Nor flash array blocks of the nonvolatile flash memory in the physical memory array M times under a condition that a power-on signal of the flash memory chip is a power-on reset signal.
The value of M is a positive integer greater than or equal to 1 and less than N, and the value of N is a positive integer greater than 2.
And the second correction module 602 is configured to perform erase disturb confirmation and correction on the Nor flash array blocks in the selected physical storage array when performing the block erase operation on the Nor flash array blocks in the physical storage array for the remaining N-M times.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in a power-on reset signal, when the non-volatile flash Nor flash array blocks in the physical storage array are subjected to block erase operation for M times, all the Nor flash array blocks are subjected to erase interference confirmation and correction, and when the non-volatile flash Nor flash array blocks in the physical storage array are subjected to block erase operation for the remaining N-M times, the Nor flash array blocks in the selected physical storage array are subjected to erase interference confirmation and correction. When the Nor flash array block is subjected to block erase operation, time consumption of the whole erase operation and power consumption of the whole erase operation are reduced, and stored data can be prevented from being rewritten.
Based on the Nor flash erasure interference correction device shown in the above embodiment of the present invention, the first correction module 601 is specifically configured to: and when the Nor flash array blocks of the nonvolatile flash memories in the physical storage array are subjected to block erasing operation for the 1 st time, all the Nor flash array blocks are subjected to erasing interference confirmation and correction.
In an embodiment of the present invention, the second correction module 602 includes a first address determination unit and a first correction unit.
The first address determining unit is used for determining a block address to be subjected to erase disturbance confirmation and correction based on a preset rule when the block erase operation is performed on the Nor flash array blocks of the nonvolatile flash memories in the physical memory array for the remaining N-1 times.
Optionally, the first address determining unit is specifically configured to: when performing block erasing operation on a non-volatile flash memory Nor flash array block in a physical storage array for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on a first address block in a preset physical storage array or a next address block of the erased Nor flash array block; and adding 1 on the basis of the block address of the Nor flash array block selected last time when the block erasing operation is carried out on the Nor flash array block of the nonvolatile flash memory in the physical memory array for each of the remaining N-2 times, and determining the block address to be subjected to the current erasing interference confirmation and correction.
And the first correction unit is used for carrying out erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in the power-on reset signal, when the non-volatile flash Nor flash array blocks in the physical storage array are subjected to the block erase operation for the 1 st time, all the Nor flash array blocks are subjected to the erase interference confirmation and correction. And when the Nor flash array block is erased in each of the remaining N-1 times, determining a block address corresponding to the Nor flash array block to be subjected to block erase operation by utilizing a preset rule, and performing erase interference confirmation and correction on the selected Nor flash array block based on the block address. By the method, the Nor flash array block is subjected to block erase operation, so that time consumption of the whole erase operation and power consumption of the whole erase operation can be reduced, and stored data can be prevented from being rewritten.
Based on the Nor flash erasure interference correction device shown in the above embodiment of the present invention, the first correction module 601 is specifically configured to: and when the Nor flash array blocks of the nonvolatile flash memories in the physical storage array are subjected to block erasing operation for the nth time, performing erasing interference confirmation and correction on all the Nor flash array blocks.
Wherein, the value of N is more than or equal to 1 and less than or equal to N;
in an embodiment of the present invention, the second correction module 602 includes a second address determination unit and a second correction unit.
And the second address determining unit is used for determining the block address to be subjected to erasure interference confirmation and correction based on a preset rule when the block erasure operation is performed on the Nor flash array blocks of the nonvolatile flash memories in the physical storage array for the remaining N-1 times.
And the second correction unit is used for carrying out erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
In the embodiment of the invention, when the power-on signal of the flash memory chip is in the power-on reset signal, the non-volatile flash Nor flash array blocks in the physical storage array are subjected to block erase operation for the nth time, and all the Nor flash array blocks are subjected to erase interference confirmation and correction. And when the Nor flash array block is erased every time in the remaining N-1 times, determining the block address to be subjected to erasure interference confirmation and correction currently by utilizing a preset rule. And performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address. By the method, the Nor flash array block is subjected to block erase operation, so that time consumption of the whole erase operation and power consumption of the whole erase operation can be reduced, and stored data can be prevented from being rewritten.
Based on the Nor flash erasure interference correction device shown in the above embodiment of the present invention, the first correction module 601 is specifically configured to: and when the block erasing operation is carried out on the Nor flash array blocks of the nonvolatile flash memories in the physical storage array for the first m times, carrying out erasing interference confirmation and correction on all the Nor flash array blocks.
Wherein, the value of M is more than 1 and less than or equal to M.
The second correction module 602 includes a third address determination unit and a third correction unit.
And the third address determining unit is used for determining the block address to be subjected to erasure interference confirmation and correction based on a preset rule when the block erasure operation is performed on the Nor flash array blocks of the nonvolatile flash memories in the physical storage array for the remaining N-m times.
And the third correction unit is used for carrying out erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
In the embodiment of the invention, under the condition that the power-on signal of the flash memory chip is in a power-on reset signal, when the block erase operation is carried out on the non-volatile flash Nor flash array blocks in the physical storage array for the first m times, the erase interference confirmation and correction are carried out on all the Nor flash array blocks. And when the Nor flash array block is erased every time in the remaining N-m times, determining the block address to be subjected to erasure interference confirmation and correction currently by utilizing a preset rule. And performing erasure disturbance confirmation and correction on the selected Nor flash array block based on the block address. By the method, the Nor flash array block is subjected to block erase operation, so that time consumption of the whole erase operation and power consumption of the whole erase operation can be reduced, and stored data can be prevented from being rewritten.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for a system or system embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, with reference to the description of the method embodiment being made in part. The systems and system embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. A method for correcting Nor flash erasure interference, the method comprising:
when the power-on signal of the flash memory chip is in a power-on reset signal, performing erase interference confirmation and correction on all Nor flash array blocks when performing block erase operation on the Nor flash array blocks in the physical memory array for M times, wherein the value of M is a positive integer greater than or equal to 1 and less than N, the value of N is a positive integer greater than 2, M refers to the number of times of performing erase interference confirmation and correction on all Nor flash array blocks, and N refers to the total number of times of all erase interference confirmation and correction;
when performing block erase operation on non-volatile flash Nor flash array blocks in a physical storage array for the remaining N-M times, performing erase disturbance confirmation and correction on one Nor flash array block in the selected physical storage array, wherein N-M refers to the number of times of performing erase disturbance confirmation and correction on the selected Nor flash array block;
The erase disturbance confirming and correcting process comprises the steps of detecting whether a Nor flash array block is disturbed or not by using an erase disturbance correcting algorithm, and if so, carrying out disturbance correction on the disturbed Nor flash array block by programming refreshing;
when M is a positive integer greater than 1, performing erase disturb confirmation and correction on all Nor flash array blocks when performing block erase operation on the Nor flash array blocks of the nonvolatile flash memory in the physical storage array for M times, including:
when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the first m times, performing erasing interference confirmation and correction on all the Nor flash array blocks, wherein the value of m is greater than 1 and less than N;
when performing block erase operation on non-volatile flash Nor flash array blocks in the physical storage array for the remaining N-M times, performing erase disturb verification and correction on one Nor flash array block in the selected physical storage array, including:
when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the remaining N-m times, determining block addresses to be subjected to erasing interference confirmation and correction based on a preset rule, wherein the preset rule refers to a first address block in a preset physical storage array or a next address block of the erased Nor flash array block;
And performing erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
2. The method of claim 1, wherein when M takes 1, performing erase disturb verification and correction on all the nors flash array blocks in the physical storage array when performing a block erase operation on the non-volatile flash nors flash array blocks M times, comprises:
when performing block erase operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the 1 st time, performing erase disturbance confirmation and correction on all the Nor flash array blocks;
when performing block erase operation on non-volatile flash Nor flash array blocks in the physical storage array for the remaining N-M times, performing erase disturb verification and correction on one Nor flash array block in the selected physical storage array, including:
when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the remaining N-1 times, determining block addresses to be subjected to erasing interference confirmation and correction based on a preset rule, wherein the preset rule refers to a first address block in a preset physical storage array or a next address block of the erased Nor flash array block;
and performing erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
3. The method of claim 2, wherein determining the block address to be erased disturb verified and corrected based on the preset rule when performing the block erase operation on the non-volatile flash Nor flash array block in the physical storage array for the remaining N-1 times, comprises:
when performing block erasing operation on a non-volatile flash memory Nor flash array block in a physical storage array for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on a first address block in a preset physical storage array or a next address block of the erased Nor flash array block;
and adding 1 on the basis of the block address of the Nor flash array block selected last time when the block erasing operation is carried out on the Nor flash array block of the nonvolatile flash memory in the physical memory array for each of the remaining N-2 times, and determining the block address to be subjected to the current erasing interference confirmation and correction.
4. The method of claim 1, wherein when M takes 1, performing erase disturb verification and correction on all the nors flash array blocks in the physical storage array when performing a block erase operation on the non-volatile flash nors flash array blocks M times, comprises:
when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the nth time, performing erasing interference confirmation and correction on all the Nor flash array blocks, wherein the value of N is greater than or equal to 1 and less than or equal to N;
When performing block erase operation on non-volatile flash Nor flash array blocks in the physical storage array for the remaining N-M times, performing erase disturb verification and correction on one Nor flash array block in the selected physical storage array, including:
when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the remaining N-1 times, determining block addresses to be subjected to erasing interference confirmation and correction based on a preset rule, wherein the preset rule refers to a first address block in a preset physical storage array or a next address block of the erased Nor flash array block;
and performing erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
5. The Nor flash erasure interference correcting device is characterized by comprising:
the first correction module is used for carrying out erasure interference confirmation and correction on all Nor flash array blocks when carrying out block erasure operation on the Nor flash array blocks of nonvolatile flash memories in the physical memory array for M times under the condition that a power-on signal of the flash memory chip is in a power-on reset signal, wherein the value of M is a positive integer greater than or equal to 1 and less than N, and the value of N is a positive integer greater than 2;
The second correction module is used for carrying out erasure interference confirmation and correction on one Nor flash array block in the selected physical storage array when the remaining N-M times of block erasure operation are carried out on the Nor flash array blocks in the physical storage array;
the first correction module and the second correction module for performing erasure interference confirmation and correction are specifically configured to detect whether the Nor flash array block is interfered by using an erasure interference correction algorithm, and if so, perform interference correction on the interfered Nor flash array block through programming refreshing;
when M is a positive integer greater than 1, the first correction module is specifically configured to: when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the first M times, performing erasing interference confirmation and correction on all the Nor flash array blocks, wherein the value of M is greater than 1 and less than or equal to M;
the second correction module comprises a third address determination unit and a third correction unit;
the third address determining unit is configured to determine, when performing a block erase operation on a non-volatile flash memory or flash array block in the physical storage array for the remaining N-m times, a block address to be subjected to erase disturb confirmation and correction based on a preset rule, where the preset rule refers to a first address block in a preset physical storage array or a next address block of the erased Nor flash array block;
And the third correction unit is used for carrying out erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
6. The apparatus of claim 5, wherein when M takes 1, the first correction module is specifically configured to: when performing block erase operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the 1 st time, performing erase disturbance confirmation and correction on all the Nor flash array blocks;
the second correction module comprises a first address determination unit and a first correction unit;
the first address determining unit is configured to determine, when performing a block erase operation on a non-volatile flash memory norflash array block in the physical storage array for the remaining N-1 times, a block address to be subjected to erase disturb confirmation and correction based on a preset rule, where the preset rule refers to a first address block in a preset physical storage array or a next address block of the erased norflash array block;
the first correction unit is used for performing erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
7. The apparatus according to claim 6, wherein the first address determining unit is specifically configured to: when performing block erasing operation on a non-volatile flash memory Nor flash array block in a physical storage array for the 2 nd time, determining a block address to be subjected to erasing interference confirmation and correction based on a first address block in a preset physical storage array or a next address block of the erased Nor flash array block; and adding 1 on the basis of the block address of the Nor flash array block selected last time when the block erasing operation is carried out on the Nor flash array block of the nonvolatile flash memory in the physical memory array for each of the remaining N-2 times, and determining the block address to be subjected to the current erasing interference confirmation and correction.
8. The apparatus of claim 5, wherein when M takes 1, the first correction module is specifically configured to: when performing block erasing operation on non-volatile flash memory Nor flash array blocks in a physical storage array for the nth time, performing erasing interference confirmation and correction on all the Nor flash array blocks, wherein the value of N is greater than or equal to 1 and less than or equal to N;
the second correction module comprises a second address determination unit and a second correction unit;
the second address determining unit is configured to determine, when performing a block erase operation on a non-volatile flash memory norflash array block in the physical storage array for the remaining N-1 times, a block address to be subjected to erase disturb confirmation and correction based on a preset rule, where the preset rule refers to a first address block in a preset physical storage array or a next address block of the erased norflash array block;
and the second correction unit is used for carrying out erasure interference confirmation and correction on the selected Nor flash array block based on the block address.
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