CN111987909A - Interleaved parallel DC/DC converter and control method thereof - Google Patents

Abstract

The invention discloses an interleaved parallel DC/DC converter and a control method, wherein the converter includes a switched inductance unit, a boosting unit, and an output circuit. The output terminal of the boosting unit is connected to the output circuit, and the output terminal is led out through the output circuit, and the output terminal outputs the boosted voltage signal. The advantages of the invention are: the whole circuit structure is symmetrical and simple, the control is convenient, and the output voltage gain is higher.

Description

A kind of interleaved parallel DC/DC converter and its control method

technical field

The invention relates to the technical field of power electronics, in particular to an interleaved parallel DC/DC converter and a control method thereof.

Background technique

With the increasing depletion of fossil energy and the pollution of the environment after burning, it has attracted more and more attention from the international community. The search for new, renewable and non-polluting energy has become an urgent task for mankind. Photovoltaic power has become a key topic in people's research on future energy demand due to its inexhaustible, clean and pollution-free advantages, with huge potential.

Since the direct output DC voltage of the photovoltaic panels in the photovoltaic power generation system is low, generally 30-50V, and for the AC220V mains, even if a full-bridge grid-connected inverter is used, the DC input bus voltage is generally 380V. Achieving high-gain DC-DC boost is one of the urgent problems to be solved in the realization of photovoltaic grid-connected power generation systems.

Although the voltage gain of the boost converter can be theoretically close to infinity when the duty cycle is close to 1, with the shortening of the switch off time: its inductor current ripple, power device peak current and output current ripple will gradually increase The voltage stress of the active switch tube and the passive switch tube is equal to the output voltage. Excessive voltage stress will greatly increase the power loss of the converter and reduce the transmission efficiency of the converter.

Because the photovoltaic panel is affected by the environment, the output voltage is unstable and fluctuates, so after the boost of the converter, the output voltage of the converter is unstable and fluctuates, so it is necessary to design a new interleaved parallel DC/DC converter and its control method.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies of the prior art, and to provide an interleaved parallel DC/DC converter, which is used to achieve higher output voltage gain of the converter and can satisfy the stability of the improved voltage output.

In order to achieve the above purpose, the technical solution adopted in the present invention is as follows: an interleaved parallel DC/DC converter, comprising a switched inductance unit, a boosting unit and an output circuit, the input end of the switched inductance unit is connected to a voltage source, and the output end of the switched inductance unit is connected to a voltage source. A boosting unit is connected, an output end of the boosting unit is connected to an output circuit, an output end is led out through the output circuit, and the output end outputs a boosted voltage signal.

The boosting unit receives the control signal and outputs a corresponding voltage according to the control signal.

The switched inductor unit includes a first switched inductor unit and a second switched inductor unit, and the first switched inductor unit and the second switched inductor unit are used for storing the electrical energy of the voltage source or discharging the stored electrical energy.

The first switched inductor unit includes a first inductor L ₁ , a second inductor L ₂ , a first diode D ₁ , a second diode D ₂ and a fifth diode D5;

The second switched inductor unit includes a third inductor L ₃ , a fourth inductor L ₄ , a third diode D ₃ , a fourth diode D ₄ and a sixth diode D ₆ ;

The output anode of the voltage source is respectively connected to one end of the first inductor L1, the anode of the first diode D1, the anode of the third diode D3, and one end of the third inductor L3, and the other end of the first inductor L3 is connected to the first inductor L3 respectively. The anode of the second diode D2, the anode of the fifth diode D5, and the cathode of the fifth diode D5 are respectively connected to the cathode of the first diode D1, one end of the second inductor L2, and the other end of the second inductor L2 The cathode of the second diode D2 is connected, and the cathode of the second diode D2 leads to the output terminal K1 of the first switched inductance unit;

The other end of the third inductor L3 is connected to the anode of the fourth diode D4 and the anode of the sixth diode D6 respectively, and the cathode of the sixth diode D6 is respectively connected to the cathode of the third diode D3 and the fourth inductor L4 one end of the fourth inductance L4, the other end of the fourth inductance L4 is connected to the cathode of the fourth diode D4, and the cathode of the fourth diode D4 leads to the output terminal K2 of the second switched inductance unit;

The output terminals K1 and K2 are used to connect to the input terminals of the boosting unit respectively.

The boosting unit includes MOS transistors S1, S2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a seventh diode D7, an eighth diode D8, and a ninth diode D9;

The gate of the MOS transistor S1 and the gate of the MOS transistor S2 are respectively input with control signals for controlling the conduction of the MOS transistors S1 and S2;

The output terminal K1 is respectively connected to the source of the MOS transistor S2 and one end of the first capacitor C1, and the other end of the first capacitor C1 is respectively connected to the cathode of the ninth diode D9 and one end of the second capacitor C2. The other end is respectively connected to the cathode of the seventh diode D7 and the anode of the eighth diode D8; the output terminal K2 is respectively connected to the source of the MOS transistor S1 and the anode of the seventh diode D7, and one end of the third capacitor C3 is connected to The anode of the seventh diode D7, the other end is connected to the cathode of the eighth diode D8, and the cathode of D8 is connected to the anode of D9;

The drain of the MOS transistor S1 and the drain of S2 are connected to the power ground;

The cathode of the ninth diode D9 leads to the output terminal of the boosting unit.

The output circuit includes an output diode D0 and an output capacitor C0. The output terminal of the boost unit is connected to the anode of the output diode D0, and the cathode of D0 is grounded through the capacitor C0; the terminal between the cathode of D0 and the capacitor C0 is used as DC/ The positive output terminal of the DC converter; the terminal drawn between the output capacitor C0 and the power ground is used as the negative output terminal of the DC/DC converter.

The duty cycle PWM signal is controlled to control the conduction of the MOS transistors S1 and S2 respectively, thereby controlling the output voltage of the converter.

A control method for interleaved parallel DC/DC converters, which adopts a double closed-loop control structure composed of an outer voltage loop and an inner current loop to control the output voltage of the DC/DC converters.

The control method includes: voltage outer loop control and current inner loop control. The voltage outer loop control includes comparing the collected output voltage V0 of the converter with the set ideal reference voltage value Vr to obtain an error value Vw between the two. , send Vw into the PI regulator to adjust the output to reach the current _ir corresponding to the required voltage, and the current _ir is used as the reference current of the current inner loop;

The current inner loop control includes a first current inner loop corresponding to the first switched inductance unit and a second current inner loop corresponding to the second switched inductance unit; half of the reference current is used as the first current inner loop and the second current inner loop respectively. The current given value of the inner loop is compared with the current sampling value of the respective switching inductance unit respectively, and the current deviation value is obtained, which is respectively sent to the corresponding current PI regulator to output the corresponding duty cycle d;

The obtained switching duty cycle d is controlled by the PWM control link G _PWM (s) to realize the control of the switching device, so that the switching duty cycle d outputs the inductor unit current of each phase from the G _id (s) regulator; the two-phase switch inductor unit The sum of the current passes through the total current of the converter inductor to the output voltage regulator G _vi (s), and the output voltage V0 is obtained, thereby realizing double closed-loop control.

The advantages of the invention are: the whole circuit structure is symmetrical and simple, the control is convenient, and the output voltage gain is higher; the circuit of the invention utilizes the parallel charging and series discharging characteristics of the inductor in the switching inductor unit, and the capacitor and the diode form a capacitor series-parallel structure. The parallel charging and series discharging and the effective charging and discharging of the capacitor increase the output voltage. Through the double closed-loop control of the voltage outer loop and the current inner loop, the improvement of the output voltage gain of the high-voltage interleaved parallel DC-DC converter and the stable output are realized. .

Description of drawings

Below is a brief description of the content expressed in each of the drawings in the description of the present invention and the labels in the drawings:

1 is a schematic structural diagram of a high-gain interleaved parallel DC-DC converter in the present invention;

Figures 2(a)-(d) are the equivalent circuit diagrams of the high-gain interleaved parallel DC-DC converters in different conduction states;

FIG. 3 is a timing diagram of switching devices S ₁ and S ₂ being turned on in one cycle;

Fig. 4 is the simulation experiment waveform diagram of the output voltage of the proposed converter and the traditional interleaved parallel converter;

Fig. 5 is the double closed-loop control block diagram of the interleaved parallel converter;

Detailed ways

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and through the description of the preferred embodiments.

An interleaved parallel DC-DC converter, the converter topology unit includes: a switched inductor unit, a boost unit, an output diode D ₀ , and an output capacitor C ₀

The first switched inductor unit is composed of the first inductor L ₁ , the second inductor L ₂ , the first diode D ₁ , the second diode D ₂ and the fifth diode D ₅ ; the third inductor L ₃ , The fourth inductor L ₄ , the third diode D ₃ , the fourth diode D ₄ and the sixth diode D ₆ form a second switched inductor unit; the schematic diagram of the connection between the load R and the converter of the present application is shown in FIG. 1 Show.

The technical scheme adopted by the control method of the interleaved parallel DC-DC converter of the present invention is as follows: a double closed-loop control structure composed of an outer voltage loop and an inner current loop is used to control its voltage, and the inner current loop adopts a current feedback control method or a current loop. In the composite control mode, the sum of the current feedback control output and the current feedforward control output is the control output of the internal current loop;

The double closed-loop control structure consisting of an outer voltage loop and an inner current loop is used to control its output voltage by controlling the output voltage of the converter at its desired voltage, that is, by controlling the duty cycle of the two power switching devices. realized.

As shown in FIG. 1 , a high-gain interleaved parallel DC-DC converter includes a voltage source, two switched inductor units, a first MOS transistor S ₁ , a second MOS transistor S ₂ , a first capacitor C ₁ , a booster The unit, the output diode D ₀ , the output capacitor C ₀ , and the load R constitute a converter circuit.

The specific connection method of the circuit is as follows:

The anode of the voltage source U _in is respectively connected to the first inductor L ₁ , the anode of the first diode D ₁ , one end of the third inductor L ₃ and the anode of the fourth diode D ₄ ; the first inductor L ₁ are respectively connected with the anodes of the _second diode D2 and the _fifth diode D5; the cathodes of the _first diode D1 are respectively connected with the cathodes of the _fifth diode D5 and one end of the _second inductor L2 ; The cathode of the second diode D ₂ is respectively connected with the other end of the second inductor L ₂ , the anode of the first capacitor C ₁ and the source of the second MOS tube S ₂ ; the cathode of the third diode D ₃ is respectively connected with The cathode of the _sixth diode D6 is connected to one end of the _fourth inductance L4; the cathode of the _fourth diode D4 is respectively connected to the other end of the _fourth inductance L4, the source of the _first MOS transistor S1, the The anode of the _seven diodes D7 is connected to the anode of the _third capacitor C3; the cathode of the first capacitor _C1 is connected to the cathode of the _second capacitor C2, the cathode of the _ninth diode D9 and the cathode of the output diode _D0 respectively. The anode is connected; the anode of the eighth diode D8 is respectively connected with the anode of the second capacitor C2 and the cathode of the seventh diode D7; the cathode of the _eighth diode _D8 is respectively connected with the anode of the ninth diode D9 and the cathode of the seventh diode D7; The cathode of the third capacitor C3 is connected; the cathode of the output diode _D0 is connected to the anode of the output capacitor _C0 and one end of the load R respectively; the cathode of the voltage source _Uin is respectively connected to the drain of the _first MOS tube S1, the second MOS _The drain of the tube S2, the cathode of the output capacitor _C0 and the other end of the load (R) are connected. The load R, as a direct load of the output voltage of the converter, can be a load for different applications in the prior art.

The first capacitor C ₁ , the second capacitor C ₂ , the third capacitor C ₃ and the output capacitor C ₀ are all electrolytic capacitors.

Figure 3 shows a schematic diagram of the conduction of the switching devices S1 and S2 in one cycle. Ugs1 corresponds to the gate voltage of S1, and is turned on when it is at a high level; similarly, Ugs2 is the gate voltage of S2. Combined with its conduction diagram, its working principle is as follows:

The concrete working process of the converter of the present invention:

In mode ₁ , as shown in Figure ₂ (a), MOS transistor S1 is turned off and S2 is turned on. Diodes D ₃ , D ₄ , D ₅ , D ₈ , D ₀ are cut off by reverse voltage. The voltage source charges and stores energy to the inductor L ₁ and the inductor L ₂ in the first switched inductor unit 1 , and the voltage source discharges in series with the inductor L ₃ and the inductor L ₄ in the second switched inductor unit 2 . Capacitors C ₂ and C ₃ are discharged in parallel to capacitor C ₁ . The load R is powered by the output capacitor C ₀ . The topological discharge circuit is U _in -L ₃ -D ₆ -L ₄ -D ₇ -C ₂ -C ₁ -S ₂ and U _in -L ₃ -D ₆ -L ₄ -C ₂ -D ₉ -C ₁ -S ₂ .

In mode 2, as shown in Fig. 2(b), the control signal controls the switching devices S ₁ and S ₂ to conduct. The diodes D ₁ , D ₂ , D ₃ , and D ₄ conduct forward, and D ₅ , D ₇ , D ₈ , D ₉ , and D ₀ are cut off by reverse voltage. The voltage source stores energy in parallel with the inductors L ₁ and L ₂ in the first switched inductance unit 1 , and the voltage source stores energy in parallel with the inductors L ₃ and L ₄ in the second switched inductance unit 2 . The output capacitor C ₀ releases the stored energy to the load R.

In mode 3, as shown in Fig. ₂ (c), the control signal turns _on the switching device S1 and turns off S2. The diodes D ₃ , D ₄ , D ₅ , and D ₈ conduct forward, and the diodes D ₁ , D ₂ , D ₆ , D ₇ , D ₉ , and D ₀ are turned off by reverse voltage. The input voltage U _in connects the inductors L ₁ and L ₂ in the switch inductor unit 1 in series, and the capacitor C ₁ charges the capacitors C ₂ and C ₃ . The input voltage U _in stores energy in parallel with the inductors L ₃ and L ₄ in the switched inductor unit 2 . In this mode, the current flowing through the inductors L ₁ and L ₂ gradually decreases, and the voltage across the capacitors C ₂ and C ₃ gradually increases. Topological discharge loops are the first loop U _in -L ₁ -D ₅ -L ₂ -C ₁ -C ₂ -D ₈ -C ₃ -S ₁ and the second loop U _in -L ₃ -D ₄ -S ₁ , the third loop U _in -D ₃ -L ₄ -S ₁ .

In mode 4, as shown in Fig. ₂ (d), the control signal turns _on the switching device S1 and turns off S2. The diodes D ₃ , D ₄ , D ₅ , and D ₈ conduct forward, and the diodes D ₁ , D ₂ , D ₆ , D ₇ , D ₉ , and D ₀ are turned off by reverse voltage. Capacitor C ₁ charges capacitors C ₂ and C ₃ . The input voltage U _in stores energy in parallel with the inductors L ₃ and L ₄ in the switched inductor unit 2 . The voltage across capacitors C ₂ and C ₃ in series is higher than the output capacitor C ₀ voltage, and diode D ₀ conducts forward. The topological discharge circuits are: U _in -L ₁ -D ₅ -L ₂ -C ₁ -D ₀ -C ₀ (R) and U _in -L ₁ -D ₅ -L ₂ -C ₁ -C ₂ -D ₈ - C ₃ -S ₁ .

In one switching cycle, let the output voltage be U ₀ , when the converter enters steady state operation, the following voltage relationship derivation process is obtained.

In Mode 1 and Mode 2 with duration D ₁₀ T _S , the current increase of inductor L ₁ and inductor L ₂ is:

D ₁₀ is the duty cycle of the switching device S ₁ , T _S is the switching period of the switching device S ₁ , and t ₀ -t ₂ is the time period of mode 1 and mode 2

In Mode 3 and Mode 4, the duration is (1-D ₁ )T _S , and the current reduction of inductors L ₁ and L ₂ is

D ₁₀ is the duty cycle of the switching device S ₁ , T _S is the switching period of the switching device S ₁ , and t ₂ -t ₄ is the period of mode 3 and mode 4

The mode 1 duration is (1-D ₂₀ )T _s , and the reduction in inductor L ₃ and L ₄ currents is:

D ₂₀ is the duty cycle of the switching device S ₁ , T _S is the switching period of the switching device S ₂ , and t ₂ -t ₄ is the period during which mode 1 is located

In Mode 2, Mode 3 and Mode 4, the duration is D ₂₀ T _s , and the current increase of inductors L ₃ and L ₄ is:

D ₂₀ is the duty cycle of the switching device S ₁ , T _S is the switching period of the switching device S ₂ , and t ₂ -t ₅ is the period of mode 2, mode 3 and mode 4

From equations (1)-(4), and the volt-second balance theorem for inductance L ₁ and inductance L ₃ , we get:

According to the symmetry of the circuit structure, we get:

From (5)-(6), when the control signal controls the switching device duty cycle D ₁₀ =D ₂₀ =D, the voltage gain of the converter topology proposed in this paper is:

Since the output voltage of the photovoltaic panel is unstable, the control objective is to maintain the high-voltage side voltage U ₀ of the high-gain interleaved parallel DC-DC converter at the ideal value U _ref . To this end, the high-gain interleaved parallel DC-DC converter adopts the voltage and current double closed-loop control method as shown in Figure 5, and its working principle is as follows:

The input voltage U _in of the photovoltaic panel is converted by the converter to obtain the output voltage U ₀ , which is compared with the ideal reference voltage signal value _Ur to determine whether there is a difference between the two, which is the error voltage U _w , and then the error The voltage U _w is fed into the PI regulator to adjust the output current _ir to the desired voltage. Since the converter adopts two-phase interleaved parallel technology, the switching inductance unit in single-phase is half of the given current. The obtained current given value is compared with the sampling value of the current of the negative feedback inductor unit in each phase, the obtained current deviation value is adjusted by the current PI regulator, and the output circuit is the switch duty cycle d that achieves the target voltage. The obtained switching duty cycle d is controlled by the PWM control link G _PWM (s) to realize the control of the switching device, so that the switching duty cycle d outputs the inductor unit current of each phase from the G _id (s) regulator; the two-phase switch inductor unit The sum of the currents passes through the converter inductor total current to the output voltage regulator _Gvi (s), resulting in the output voltage v. When the voltage and current double closed-loop control is used, the output voltage can still be stable after adjustment when the input voltage fluctuates. Among them, G _PWM (s) is the modulator function of the output PWM regulator, Ki (s) and Kv (s) are the current loop and voltage loop adjustment coefficients; G _vi (s) and G _id (s) are the passing state space The method obtains a periodic state space equation, and then performs S transformation on the equation, and finally obtains the duty cycle d to the inductor current transfer function G _id (s), and the duty cycle to the output voltage function G _vi (s). As shown in FIG. 4 , for the waveform diagram of the converter of the present application corresponding to the existing converter after software simulation, it can be seen from the figure that the present application has a higher gain, and can achieve a larger and more stable output. voltage, and the circuit structure is simple and reliable.

Obviously, the specific implementation of the present invention is not limited by the above-mentioned manner, as long as various insubstantial improvements made by adopting the method concept and technical solution of the present invention are all within the protection scope of the present invention.

Claims (9)

1. An interleaved parallel DC/DC converter, characterized in that it comprises a switched inductance unit, a boosting unit, and an output circuit, the input end of the switched inductance unit is connected to a voltage source, and its output is connected to a boosting unit, and the The output terminal of the boosting unit is connected to the output circuit, and the output terminal is led out through the output circuit, and the output terminal outputs the boosted voltage signal. 2 . The interleaved parallel DC/DC converter according to claim 1 , wherein the boosting unit receives a control signal and outputs a corresponding voltage according to the control signal. 3 . 3 . The interleaved parallel DC/DC converter according to claim 1 , wherein the switched inductor unit comprises a first switched inductor unit and a second switched inductor unit, the first switched inductor unit and the first switched inductor unit. The two switched inductance units are used to store the electrical energy of the voltage source or to discharge the stored electrical energy. 4 . The interleaved parallel DC/DC converter according to claim 3 , wherein the first switched inductor unit comprises a first inductor L ₁ , a second inductor L ₂ , and a first diode D ₁ . 5 . , the _second diode D2 and the fifth diode D5; The second switched inductor unit includes a third inductor L ₃ , a fourth inductor L ₄ , a third diode D ₃ , a fourth diode D ₄ and a sixth diode D ₆ ; The output anode of the voltage source is respectively connected to one end of the first inductor L1, the anode of the first diode D1, the anode of the third diode D3, and one end of the third inductor L3, and the other end of the first inductor L3 is connected to the first inductor L3 respectively. The anode of the second diode D2, the anode of the fifth diode D5, and the cathode of the fifth diode D5 are respectively connected to the cathode of the first diode D1, one end of the second inductor L2, and the other end of the second inductor L2 The cathode of the second diode D2 is connected, and the cathode of the second diode D2 leads to the output terminal K1 of the first switched inductance unit; The other end of the third inductor L3 is connected to the anode of the fourth diode D4 and the anode of the sixth diode D6 respectively, and the cathode of the sixth diode D6 is respectively connected to the cathode of the third diode D3 and the fourth inductor L4 one end of the fourth inductance L4, the other end of the fourth inductance L4 is connected to the cathode of the fourth diode D4, and the cathode of the fourth diode D4 leads to the output terminal K2 of the second switched inductance unit; The output terminals K1 and K2 are used to connect to the input terminals of the boosting unit respectively. 5. An interleaved parallel DC/DC converter according to any one of claims 1-4, wherein the boosting unit comprises MOS transistors S1, S2, a first capacitor C1, a second capacitor C2, a first capacitor Three capacitors C3, seventh diode D7, eighth diode D8, ninth diode D9; The gate of the MOS transistor S1 and the gate of the MOS transistor S2 are respectively input with control signals for controlling the conduction of the MOS transistors S1 and S2; The output terminal K1 is respectively connected to the source of the MOS transistor S2 and one end of the first capacitor C1, and the other end of the first capacitor C1 is respectively connected to the cathode of the ninth diode D9 and one end of the second capacitor C2. The other end is respectively connected to the cathode of the seventh diode D7 and the anode of the eighth diode D8; the output terminal K2 is respectively connected to the source of the MOS transistor S1 and the anode of the seventh diode D7, and one end of the third capacitor C3 is connected to The anode of the seventh diode D7, the other end is connected to the cathode of the eighth diode D8, and the cathode of D8 is connected to the anode of D9; The drain of the MOS transistor S1 and the drain of S2 are connected to the power ground; The cathode of the ninth diode D9 leads to the output terminal of the boosting unit. 6. An interleaved parallel DC/DC converter according to claim 1-4, wherein the output circuit comprises an output diode D0 and an output capacitor C0, and the output terminal of the booster unit is connected to the output The anode of the diode D0 and the cathode of D0 are grounded through the capacitor C0; the terminal between the cathode of D0 and the capacitor C0 is used as the positive output terminal of the DC/DC converter; the terminal between the output capacitor C0 and the power supply ground is used as DC/DC The negative output terminal of the inverter. 7. The interleaved parallel DC/DC converter according to any one of claims 1-6, wherein the duty cycle PWM signal is controlled to respectively control the conduction of the MOS transistors S1 and S2, thereby controlling the The output voltage. 8. The control method for an interleaved parallel DC/DC converter according to any one of claims 1-7, wherein the DC/DC converter is converted by a double closed-loop control structure composed of an outer voltage loop and an inner current loop. The output voltage of the device is controlled. 9. The control method of an interleaved parallel DC/DC converter according to claim 8, wherein the control method comprises: Voltage outer loop control and current inner loop control. The voltage outer loop control includes comparing the output voltage V0 of the collected converter with the set ideal reference voltage value Vr to obtain the error value Vw between the two, and sending Vw into the In the PI regulator, the output is adjusted to reach the current _ir corresponding to the required voltage, and the current _ir is used as the reference current of the current inner loop; The current inner loop control includes a first current inner loop corresponding to the first switched inductance unit and a second current inner loop corresponding to the second switched inductance unit; half of the reference current is used as the first current inner loop and the second current inner loop respectively. The current given value of the inner loop is compared with the current sampling value of the respective switching inductance unit respectively, and the current deviation value is obtained, which is respectively sent to the corresponding current PI regulator to output the corresponding duty cycle d; The obtained switching duty cycle d is controlled by the PWM control link G _PWM (s) to realize the control of the switching device, so that the switching duty cycle d outputs the inductor unit current of each phase from the G _id (s) regulator; the two-phase switch inductor unit The sum of the current passes through the total current of the converter inductor to the output voltage regulator G _vi (s), and the output voltage V0 is obtained, thereby realizing double closed-loop control.

Images