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CN111971792A - 具有偏移3d结构的多芯片封装 - Google Patents

具有偏移3d结构的多芯片封装 Download PDF

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Publication number
CN111971792A
CN111971792A CN201980025365.0A CN201980025365A CN111971792A CN 111971792 A CN111971792 A CN 111971792A CN 201980025365 A CN201980025365 A CN 201980025365A CN 111971792 A CN111971792 A CN 111971792A
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semiconductor chip
metallization stack
chip package
chips
package
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CN201980025365.0A
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CN111971792B (zh
Inventor
米林德·S·巴格瓦特
拉胡尔·阿加瓦尔
加布里埃尔·H·罗
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Abstract

公开各种半导体芯片装置及其制造方法。在一个方面，提供一种半导体芯片装置，所述半导体芯片装置具有重构半导体芯片封装(115)，所述重构半导体芯片封装(115)包括：具有第一侧和相反的第二侧的中介层(125)与位于所述第一侧上的金属化堆叠(145)；第一半导体芯片(25)，所述第一半导体芯片(25)位于所述金属化堆叠上并且至少部分地由所述金属化堆叠上的电介质层(165)包封；以及多个半导体或芯片(40、45)，所述多个半导体或芯片(40、45)定位在第一半导体芯片之上并且与所述第一半导体芯片至少部分地侧向重叠。

Description

具有偏移3D结构的多芯片封装
背景技术
常规类型的多芯片模块包括并排安装在中介层上的处理器芯片和四个存储器芯片(所谓的“2.5D”)，所述中介层继而安装在球栅阵列(BGA)封装衬底上。存储器芯片围绕处理器芯片的外围布置。处理器芯片和存储器芯片安装在中介层上，并通过相应多个焊料接头与其互连。中介层和封装衬底设置有多个电通路，以针对芯片间功率、接地和信号传播以及来自中介层本身的输入/输出两者为导体芯片提供输入/输出通路。半导体芯片包括相应的底部填充材料层，以减轻由于芯片、中介层和焊料接头的热膨胀系数不同而引起的热膨胀差异的影响。中介层被制造成具有众多穿硅通孔(TSV)，以在已安装芯片与上面安装有中介层的封装衬底之间提供通路。TSV和迹线是使用大量处理步骤制作的。
虽然常规BGA插槽具有许多形状和尺寸，但通常存在各种工业标准尺寸和引脚分配。一旦确定下来，这些标准尺寸就随着时间推移而使用，有时用于许多不同装置(诸如计算机、手持式装置和其他电子装置)中。常规BGA插槽的一个实例是Nvidia SMX2。
另一种常规多芯片模块技术是2D晶圆级扇出(或2D WLFO)。常规2D WLFO技术是基于将管芯嵌入模制晶圆中，也称为“晶圆重构”。通过标准晶圆级处理流程来处理模制晶圆，以产生最终集成电路组件结构。管芯的有效表面与模制化合物共面，从而允许使用常规重新分布层(RDL)处理将导电铜迹线和焊球焊盘“扇出”到模制区域中。常规3D WLFO将2D技术扩展到多芯片堆叠中，其中将第二封装衬底安装在2D WLFO上。
附图说明
在阅读以下详细描述并且参考附图后，本发明的前述和其他优点将变得明了，在附图中：
图1是安装在电路板上的常规插槽中的示例性常规半导体芯片封装的平面图；
图2是图1在截面2-2处截取的剖视图；
图3是安装在插槽中的半导体芯片封装的示例性新布置的平面图；
图4是图3在截面4-4处截取的剖视图；
图5是以更大放大倍数示出的图4的一部分；
图6是以更大放大倍数示出的图4的另一部分；
图7是描绘对中介层的某种处理和金属化堆叠在其上的制作的剖视图；
图8是类似于图7但描绘半导体芯片在金属化堆叠上的示例性安装的剖视图；
图9是类似于图8但描绘至少部分地包封半导体芯片的示例性电介质层制作的剖视图；
图10是类似于图9的描绘穿电介质通孔制作的剖视图；
图11是类似于图10但描绘电介质层上的示例性半导体芯片和虚设元件安装的剖视图；
图12是类似于图11但描绘示例性模制层制作的剖视图；
图13是类似于图12但描绘示例性临时载体晶圆附接和TSV暴露的剖视图；
图14是类似于图13但描绘中介层上的示例性UBM和互连件制作的剖视图；
图15是替代示例性半导体芯片封装的平面图；并且
图16是图15在截面16-16处截取的并且包括与芯片封装分解的散热器的剖视图。
具体实施方式
一种常规多芯片模块变体包括以2.5D布置位于硅中介层上的并排处理器和存储芯片，所述硅中介层继而安装在封装衬底上。常规封装衬底被制造成具有针对特定类型的BGA插槽定制的占用面积和引脚分配。换句话说，封装衬底的尺寸和形状在很大程度上取决于插槽的机械性质、尺寸等。给定多芯片模块的性能通常可通过将与一个或多个处理器或片上系统芯片协作的另外的存储器芯片并入到模块中来提高。然而，将另外的存储器芯片封装到针对标准插槽和随附封装衬底设计的多芯片模块中是一项技术挑战。一种常规解决方案是简单地增加中介层和封装两者的尺寸。当然，此技术几乎总是涉及插槽的重新设计，这将要求重新设计和配置使用最初采用的标准插槽的多种不同类型的电路板。
所公开的实施方案通过以下方式来解决将另外的芯片并入多芯片模块中的问题：将略小的芯片堆叠在较大的处理器或其他类型的集成电路上，并且使上部芯片与下部芯片至少部分地侧向重叠，而无需实质上改变底层中介层和封装衬底的物理占用面积。以这种方式，可在保持使用现有插槽尺寸和设计的能力的同时，将另外的存储器装置或其他类型的集成电路并入到多芯片模块中。
根据本发明的一个方面，提供一种半导体芯片装置，所述半导体芯片装置具有重构半导体芯片封装，所述重构半导体芯片封装包括：具有第一侧和相反的第二侧的中介层与位于所述第一侧上的金属化堆叠；第一半导体芯片，所述第一半导体芯片位于所述金属化堆叠上并且至少部分地由所述金属化堆叠上的电介质层包封；以及多个半导体或芯片，所述多个半导体或芯片定位在第一半导体芯片之上并且与所述第一半导体芯片至少部分地侧向重叠。
根据本发明的另一方面，提供一种半导体芯片封装，所述半导体芯片封装包括：半导体芯片封装衬底，所述半导体芯片封装衬底适于安装在电路板插槽中；以及重构半导体芯片封装，所述重构半导体芯片封装安装在所述半导体芯片封装衬底上。所述重构半导体芯片封装包括：具有第一侧和相反的第二侧的中介层与位于所述第一侧上的金属化堆叠；第一半导体芯片，所述第一半导体芯片位于所述金属化堆叠上并且至少部分地由所述金属化堆叠上的电介质层包封；以及多个半导体或芯片，所述多个半导体或芯片定位在第一半导体芯片之上并且与所述第一半导体芯片至少部分地侧向重叠。
根据本发明的另一方面，提供一种制造半导体芯片装置的方法。所述方法包括制作重构半导体芯片封装，所述重构半导体芯片封装具有：包括第一侧和相反的第二侧的中介层与位于所述第一侧上的金属化堆叠；第一半导体芯片，所述第一半导体芯片位于所述金属化堆叠上并且至少部分地由所述金属化堆叠上的电介质层包封；以及多个半导体或芯片，所述多个半导体或芯片定位在第一半导体芯片之上并且与所述第一半导体芯片至少部分地侧向重叠。
在以下描述的附图中，当相同元件出现在一个以上附图中时，附图标号通常重复。现在转向附图，并且具体地转向图1，图1是安装在系统板20的插槽15中的示例性常规半导体芯片封装10的平面图。应注意，仅描绘了系统板20的一部分。常规封装包括全部安装在底层中介层50上的处理器芯片25以及四个存储芯片30、35、40和45，所述底层中介层50继而安装在封装衬底55上。现在可通过参考图2来理解常规半导体芯片封装10和插槽15的另外的细节，图2是图1在截面2-2处截取的剖视图。应注意，由于截面2-2的位置，得以示出半导体芯片25以及半导体芯片35和45连同底层中介层50、封装衬底55、插槽15和系统板20的截面。在这种说明性常规布置中，插槽15可以是具有特定占用面积或面积的BGA插槽，并且封装衬底55被设定尺寸以装配在插槽15的占用面积内。常规封装10仅以2.5D布置利用四个存储芯片30、35、40和45，并且利用中介层50来提供芯片30、35、40和45与芯片25之间的电通路。中介层50由硅衬底构成，并且设置有多个互连件60(通常为焊料球或凸点)以及多个穿衬底导体或通孔65，所述多个穿衬底导体或通孔65被设计为从凸点60一直连接到芯片35和40的相应焊料凸点70以及半导体芯片25的另外的焊料凸点75。芯片25以及芯片30、35、40和45具有特定尺寸和占用面积，其可随时间推移进行改变，尽管需要大量精力和费用。封装衬底55还包括多个互连件80，其在此说明性常规布置中为焊料球。
现在可通过参考图3和图4来理解半导体芯片装置90的新示例性布置。图3是类似于图1但示出定位在上述的系统板20的插槽15中的示例性新半导体芯片装置90的平面图，并且图4是图3在截面4-4处截取的剖视图。应注意，由于截面4-4的位置，得以示出重构封装115的芯片40和45、虚设部件110以及芯片25的截面。此处，芯片装置90包括在重构封装115中耦接在一起的半导体芯片25(出于稍后解释的原因而以虚线示出)，以及半导体芯片30、35、40和45和两个或更多个另外的芯片95和100和任选的虚设部件105和110。重构封装115继而安装在底层电路板120上，所述底层电路板120可以是封装衬底120等。电路板120优选地被构造为具有与插槽15的占用面积相对应的占用面积。然而，通过使用重构封装115，多于仅四个存储器芯片30、35、40和45(即，芯片30、35、40和45加上芯片95和100)可与芯片25组在一起，但具有与图1和2所示的常规封装10相同的封装占用面积。如以上简要指出，芯片25以虚线示出，因为它在重构封装115中定位在芯片30、35、40、45、95和100下方，因此严格来说芯片25在图3中是不可见的，但是在图4的截面图中它当然是可见的。应注意，通过将芯片25定位在芯片30、35、40、45、95和100下方，并且通过使芯片30、35、40、45、95和100与芯片25至少部分地侧向重叠，另外的存储器芯片95和100可在封装的相同总占用面积中与芯片25组在一起。此处，芯片30、35、40、45、95和100的数目是六，并且围绕芯片25的周边对称地布置。然而，其他数目和对称或不对称布置也是可能的。
如图4所示，重构封装115包括由硅、锗、绝缘体上硅等中介材料构成的中介层125。中介层125通过多个I/O 130与电路板120电对接，所述多个I/O 130可以是焊料凸点、焊料球或其他类型的互连结构。为了提供应力消除，中介层125的下表面可包括聚合物层135，所述聚合物层135由聚苯并恶唑构成，但也可使用其他聚合物材料，诸如苯并环丁烯、高温或低温聚酰亚胺或其他聚合物。多个穿衬底通孔(TSV)140形成在中介层125中，并且电连接到I/O 130。凸点下金属化层(UBM)142优选地形成在TSV 140的下端上。UBM 142可由提供焊料粘附、阻挡层和电介质粘附特性的多种金属构成。一种布置包括Ti-W和铜的阻挡层/粘附层，之后是铜层、镍层和与焊料对接的另一铜层。金属化堆叠145形成在中介层125上，并且由导体迹线150和导电通孔155的一个或多个层组成。各种迹线150和通孔155散布在多个电介质层157内，所述多个电介质层157由在具有或不具有等离子体增强的情况下通过CVD沉积的氧化硅或其他类型的电介质材料构成。半导体芯片25安装在金属化堆叠145上，并且其互连部分160通过下文将更详细描述的氧化物混合结合工艺不仅结合到金属化堆叠145的电介质中的一些，而且还结合到导体迹线150中的一些。
半导体芯片25、30、35、40、45、95和100可以是多种集成电路中的任一种。实例的非详尽列表包括微处理器、图形处理单元、组合两者的各方面的应用处理单元、存储装置、专用集成电路等。在一种布置中，半导体芯片25可以是处理器，并且半导体芯片30、35、40、45、95和100可以是存储器芯片，诸如DRAM、SRAM等。电路板120可以是有机的或陶瓷的，并且可以是单层的或更常见的多层。变型包括封装衬底、系统板、子板、电路卡等。
半导体芯片25包封在电介质层165中，所述电介质层165优选地由通过低温PECVD或另一合适的工艺沉积的氧化硅构成。穿电介质通孔(TDV)170形成在电介质膜165中，并且与金属化堆叠145的迹线150中的一些电连接并且还电连接到芯片40和45的相应I/O 175和180。将结合后续附图来描述I/O 175和180与穿电介质通孔170之间的冶金连接的另外的细节。半导体芯片40和45与电介质膜165之间的间隙可填充有底部填充物185，所述底部填充物185可以是公知的聚合物底部填充材料。虚设部件110可以是硅、锗或其他类型的半导体或者甚至是电介质材料的衬底，并且用作用于将热量从芯片25和重构封装115的其他部件传走的传热途径。虚设部件110可通过粘合剂、氧化物间结合或其他类型的连结技术固定到电介质膜165。最后，芯片40和45以及虚设部件110至少部分地包封在模制层188中，所述模制层188与芯片40、45和虚设部件110的上表面大致竖直地毗连。在示例性布置中，用于模制层188的一种或多种材料可具有约165℃的模制温度。两种商业变体是Sumitomo EME-G750和G760。
电路板120可通过所示的焊料球190与插槽15电对接，任选地，可使用引脚栅格阵列或平面栅格阵列或甚至其他类型的板至插槽连接。实际上，在其他布置中，可使用无插槽连接。焊料球190、I/O 130以及I/O 175和180可以是焊料结构、导电柱或两者的组合。可使用公知的焊料组合物，诸如锡-银、锡-银-铜等。TSV 140、迹线150、通孔155和TDV 170(以及任何相关的所公开的导体，诸如柱和焊盘)可由各种导电材料(诸如铜、铝、银、金、铂、钯等)构成。
应注意图4中的虚线矩形195的位置。虚线矩形195的部分将在图5中以更大放大倍数示出。还应注意图4中的虚线矩形200的位置。图4的由虚线矩形200圈出的部分将在图6中以更大放大倍数示出。
现在将注意力转向图5，如刚刚所指出，图5是图4的由虚线矩形195圈出的部分。如以上所指出，半导体芯片25的互连部分160通过无凸点氧化物混合结合技术连结到金属化堆叠145。就此而言，半导体芯片25与金属化堆叠145之间的互连件202由金属化堆叠145的结合焊盘205与芯片25的结合焊盘210之间的冶金结合构成。互连件202是无凸点的并且是众多中的一个。结合焊盘150连接到迹线150或以其他方式是其一部分。此外，绝缘结合层215将芯片25连结到金属化堆叠145，并且由半导体芯片45的玻璃层217(诸如SiOx)和金属化堆叠145的另一玻璃层219(诸如氮氧化硅)组成。结合焊盘205定位在玻璃层219中，并且结合焊盘210定位在玻璃层217中。结合焊盘205和结合焊盘210通过退火工艺冶金地结合。就此而言，将半导体芯片25下放或以其他方式定位在金属化堆叠145上，使得玻璃层217在氧氮化硅玻璃层219上或与其紧密接近，并且结合焊盘210在结合焊盘205上或与其紧密接近。此后，执行退火工艺，这导致结合焊盘210和205的临时热膨胀，从而使这些结构物理接触，并且致使它们形成即使在芯片25和金属化堆叠145冷却并且结合焊盘210和205热收缩之后也存在的冶金结合。铜在此金属结合工艺中表现良好，但可使用其他导体。在玻璃层217与玻璃层219之间还形成氧化物/氮氧化物结合。
现在可通过参考图6来理解如以上所指出的TDV 170与芯片40和45之间的电连接的另外的细节，图6是图4的由虚线矩形200圈出的部分。应注意，描绘了TDV 170中的一个的一部分以及电介质层165的一部分。导电柱225形成在TDV 170中的一个上并且与其欧姆接触，并且竖直地向上突出超过由氧化硅或其他材料构成的电介质膜230。电介质膜230包括在其中形成以容纳导电柱225的合适的开口235。导电柱225有利地通过将材料通过合适的掩模(未示出)电镀到开口235中或根据需要通过材料沉积和光刻图案化来形成。芯片45的I/O 175优选地是焊料凸点或微凸点，并且通过接触和焊料回流冶金地连接到导电柱225。任选地，I/O 175可以是通过热结合或根据需要通过焊帽连结到导电柱225的另一根导电柱。如以上所指出，底部填充物185使用毛细管技术沉积在芯片45与电介质层165之间，并且用以减轻CTE失配的问题。任选地，可使用模制底部填充物。
现在可通过参考图7、图8、图9、图10、图11、图12、图13和图14以及首先参考图7来理解用于制作重构封装115的示例性工艺流程，图7是描绘在其上制作金属化堆叠145之后的中介层125。虽然不是必须的，但这优选地是晶圆级工艺，其中重构封装115是最终经历切单(singulation)的重构晶圆(未示出)的一部分。应注意，TSV140已制作出，但中介层125尚未在其背面240处经历薄化处理以暴露TSV 140。金属化堆叠145可通过使用公知的材料沉积和图案化工艺建立导电迹线150、通孔155和一个或多个层间电介质膜157来构造。TSV140可通过适当的掩膜和蚀刻形成于在中介层125中形成的对应开口245中。TSV 140可通过公知的电镀或溅射或其他材料沉积工艺形成，并且可由本文其他地方公开的导体材料构成。如果需要的话，可在沉积或以其他方式放置主体导体材料之前，在开口245中沉积一层或多层阻挡膜。可使用诸如氮化钛等的阻挡层。
接下来并且如图8所示，通过涉及芯片25的互连部分160的混合氧化物结合工艺和上文结合图5所述的工艺将半导体芯片25安装在金属化堆叠145上。中介层125此时仍然未薄化。接下来并且如图9所示，在金属化堆叠145上形成电介质层165，并且此时电介质层165包封半导体芯片25。在电介质膜165中形成多个开口250以预期随后制作TDV 170。如图10所示，使用合适的掩模和定向干法蚀刻在电介质膜165的开口250中形成TDV 170。TDV 170的形成可非常类似于上述TSV 140的形成。就此而言，在制作开口250之后，可在一个或多个阻挡层(诸如氮化钛、Ti-W等)之后进行两步电镀工艺，所述工艺涉及首先施加铜籽晶层，然后施加铜主体层。当然，如果使用其他导体材料，则应使用适于那些材料的对应工艺。如以上所指出，TDV 170被形成为与金属化堆叠145的迹线150中的一些欧姆接触。此时，中介层125尚未经历薄化处理以暴露TSV 140。
接下来并且如图11所示，将虚设部件110以及半导体芯片40和45安装在电介质层165上。如以上所指出，虚设部件110可通过粘合剂、氧化物结合或其他类型的连结技术来附接。芯片40和45与电介质膜165的连接需要形成上文描绘并且结合图6描述的冶金结合，使得芯片40和45的I/O 175和180冶金地连接到TDV 170中的对应TDV。芯片40和45(以及图3所示的芯片30、35、95和100)被定位成与底层芯片25具有期望的侧向重叠。底部填充物185可通过毛细作用分配或者可通过随后沉积的模制材料层来提供。接下来并且如图12所示，在电介质膜165上模制模制层188，并且模制层188至少部分地包封芯片40和45以及虚设部件110。当然，应理解，模制材料188不仅部分地包封在图12中可见的芯片40和45以及虚设部件110，而且还包封图3中所描绘的其他芯片30、35、95、100和其他虚设部件105。对模制层188进行随后的磨削处理，以便使芯片40和45以及虚设部件110的上表面暴露，以除其他原因之外使得能够将散热器(未示出)安装在芯片40、45以及虚拟部件110和图3所示的虚拟部件105上并且与其热接触。应注意，在此阶段，中介层125尚未经历薄化处理。
接下来并且如图13所示，将临时载体晶圆255安装到模制层188，以为暴露中介层125的TSV 140所需的中介层125薄化提供结构支撑。载体晶圆255可由硅、其他半导体、各种玻璃构成，并且可通过热或光活化粘合剂或甚至双面胶带(其可在之后除去)连接到模制层188。在中介层125薄化和TSV 140暴露之后，可使用公知的旋转沉积和烘焙技术来施加聚合物层135。聚合物层135可用光敏材料构造，使得可在其中光刻图案化合适的开口，以便促进后续的UBM 142制作和I/O 130与其的连接。此时，可通过将重构封装115放置在电路板120上以及I/O 130的冶金回流来将重构封装115安装到电路板120。
在前述说明性布置中，虚设部件105和110提供从底层半导体芯片25到任选散热器(未示出)的热通路。然而，虚设部件105和110可省略，并且热通路仍可由其他结构提供。就此而言，图15描绘类似于图3的平面图，并且图16描绘替代示例性半导体芯片装置90’的图15在截面16-16处截取的剖视图，所述截面16-16是与上文图4所示的截面4-4基本上相同的截面位置，替代示例性半导体芯片装置90’包括全部安装在重构封装115上的上述半导体芯片25以及芯片30、35、40、45、95和100，所述重构封装115继而安装在电路板120上，如上文大体描述的，但有一些明显不同。窗口260形成在重构封装115的最上部分中以暴露半导体芯片25的一部分。应注意，半导体芯片25的轮廓仍被遮蔽，因此以虚线示出。虚设部件110和115与上述模制层188一样被消除。为了与半导体芯片25建立热通路，可将盖子或散热器265安装在电路板120上，并且盖子或散热器265可设置有传热表面270，所述传热表面270在半导体芯片40与45之间向下突出穿过形成在重构封装115的电介质膜165中的窗口260，以与半导体芯片25的背面建立热接触。盖子265可由多种公知的散热器材料(诸如套镍铜、铜、铝或其他材料)构成。盖子265可根据需要通过合适的粘合剂或甚至焊料来在其外围唇部275处固定到封装衬底20。
虽然本发明可易于具有各种修改和替代形式，但是已经以举例方式在附图中示出并且已经在本文中详细描述具体实施方案。然而，应理解，本发明并不意图限于所公开的特定形式。相反，本发明涵盖落入如以下所附权利要求限定的本发明的精神和范围内的所有修改、等效物和替代方案。

Claims (20)

1.一种半导体芯片装置，其包括：
重构半导体芯片封装(115)，所述重构半导体芯片封装(115)包括：具有第一侧和相反的第二侧的中介层(125)与位于所述第一侧上的金属化堆叠(145)；第一半导体芯片(25)，所述第一半导体芯片(25)位于所述金属化堆叠上并且至少部分地由所述金属化堆叠上的电介质层(165)包封；以及多个半导体或芯片(40、45)，所述多个半导体或芯片(40、45)定位在第一半导体芯片之上并且与所述第一半导体芯片至少部分地侧向重叠。
2.如权利要求1所述的半导体芯片装置，其包括电路板(120)，所述重构半导体芯片封装安装在所述电路板上。
3.如权利要求2所述的半导体芯片装置，其中所述电路板包括半导体芯片封装衬底。
4.如权利要求1所述的半导体芯片装置，其包括至少部分地包封所述多个半导体芯片的模制层(188)。
5.如权利要求1所述的半导体芯片装置，其包括定位在所述模制层中的至少一个虚设部件(110)。
6.如权利要求1所述的半导体芯片装置，其中所述电介质层包括开口(260)，所述开口(260)适于使散热器(265)的一部分定位在其中以与所述第一半导体芯片热接触。
7.如权利要求1所述的半导体芯片装置，其包括将所述第一半导体芯片电连接到所述金属化堆叠的多个无凸点互连件(202)以及将所述第一半导体芯片物理地连接到所述金属化堆叠的绝缘结合层(215)。
8.如权利要求1所述的半导体芯片装置，其中所述中介层包括多个穿衬底通孔(140)，并且所述电介质层包括多个穿电介质通孔(170)。
9.一种半导体芯片封装，其包括：
半导体芯片封装衬底(120)，所述半导体芯片封装衬底(120)适于安装在电路板插槽(15)中；以及
重构半导体芯片封装(115)，所述重构半导体芯片封装(115)安装在半导体芯片封装衬底上，并且包括：具有第一侧和相反的第二侧的中介层(125)与位于所述第一侧上的金属化堆叠(145)；第一半导体芯片(25)，所述第一半导体芯片(25)位于所述金属化堆叠上并且至少部分地由所述金属化堆叠上的电介质层(165)包封；以及多个半导体芯片(40、45)，所述多个半导体芯片(40、45)定位在所述第一半导体芯片之上并且与所述第一半导体芯片至少部分地侧向重叠。
10.如权利要求9所述的半导体芯片封装，其中所述插槽是球栅阵列(BGA)插槽，并且所述半导体芯片封装包括BGA。
11.如权利要求9所述的半导体芯片封装，其包括至少部分地包封所述多个半导体芯片的模制层(188)。
12.如权利要求9所述的半导体芯片封装，其包括定位在所述模制层中的至少一个虚设部件(110)。
13.如权利要求9所述的半导体芯片封装，其中所述电介质层包括开口(260)，所述开口(260)适于使散热器(265)的一部分定位在其中以与所述第一半导体芯片热接触。
14.如权利要求9所述的半导体芯片封装，其包括将所述第一半导体芯片电连接到所述金属化堆叠的多个无凸点互连件(202)以及将所述第一半导体芯片物理地连接到所述金属化堆叠的绝缘结合层(215)。
15.如权利要求9所述的半导体芯片封装，其中所述中介层包括多个穿衬底通孔(140)，并且所述电介质层包括多个穿电介质通孔(170)。
16.一种制造半导体芯片装置的方法，其包括：
制作重构半导体芯片封装(115)，所述重构半导体芯片封装(115)包括：具有第一侧和相反的第二侧的中介层(125)与位于所述第一侧上的金属化堆叠(145)；第一半导体芯片(25)，所述第一半导体芯片(25)位于所述金属化堆叠上并且至少部分地由所述金属化堆叠上的电介质层(165)包封；以及多个半导体或芯片(40、45)，所述多个半导体或芯片(40、45)定位在第一半导体芯片之上并且与所述第一半导体芯片至少部分地侧向重叠。
17.如权利要求16所述的方法，将所述重构半导体芯片封装安装在电路板(120)上。
18.如权利要求16所述的方法，其包括：将至少一个虚设部件(110)安装在所述电介质层上。
19.如权利要求16所述的方法，其包括：形成至少部分地包封所述多个半导体芯片的模制层(188)。
20.如权利要求16所述的半导体芯片装置，其包括：用多个无凸点互连件(202)将所述第一半导体芯片电连接到所述金属化堆叠，以及用绝缘结合层(215)将所述第一半导体芯片物理地连接到所述金属化堆叠。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113206070A (zh) * 2021-03-09 2021-08-03 日月光半导体制造股份有限公司 半导体封装结构及其形成方法
CN113808961A (zh) * 2020-08-06 2021-12-17 台湾积体电路制造股份有限公司 封装结构及其形成方法

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016116499B4 (de) * 2016-09-02 2022-06-15 Infineon Technologies Ag Verfahren zum Bilden von Halbleiterbauelementen und Halbleiterbauelemente
US10978382B2 (en) * 2019-01-30 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US12183675B2 (en) * 2019-03-13 2024-12-31 Advanced Micro Devices, Inc. Fan-out packages with warpage resistance
US11127718B2 (en) * 2020-01-13 2021-09-21 Xilinx, Inc. Multi-chip stacked devices
US11004833B1 (en) * 2020-02-17 2021-05-11 Xilinx, Inc. Multi-chip stacked devices
US20210272885A1 (en) * 2020-02-27 2021-09-02 Intel Corporation Interposer heat spreader
US11239217B2 (en) * 2020-03-30 2022-02-01 Nanya Technology Corporation Semiconductor package including a first sub-package stacked atop a second sub-package
CN112234027A (zh) * 2020-10-14 2021-01-15 天津津航计算技术研究所 一种2.5d电子封装结构
CN112331635B (zh) * 2020-11-04 2022-06-07 中国科学院微电子研究所 一种基于转接板的垂直封装结构及封装方法
US11749632B2 (en) * 2021-03-31 2023-09-05 Toyota Motor Engineering & Manufacturing North America, Inc. Glass-based bonding structures for power electronics
US20230079607A1 (en) * 2021-09-13 2023-03-16 Intel Corporation Fine bump pitch die to die tiling incorporating an inverted glass interposer
TWI791342B (zh) * 2021-11-30 2023-02-01 財團法人工業技術研究院 異質整合半導體封裝結構
CN114843238A (zh) * 2022-04-28 2022-08-02 维沃移动通信有限公司 封装结构、电子设备及封装方法
US20230402340A1 (en) * 2022-05-18 2023-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device
US20240128211A1 (en) * 2022-10-14 2024-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die package and methods of manufacturing

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070296079A1 (en) * 2006-06-12 2007-12-27 Siliconware Precision Industries Co., Ltd. Heat dissipating structure and method for fabricating the same
US20100216410A1 (en) * 2009-02-20 2010-08-26 Aiconn Technology Corporation Radio transceiver module
US20150070863A1 (en) * 2013-09-06 2015-03-12 Qualcomm Incorporated Low package parasitic inductance using a thru-substrate interposer
US20160260695A1 (en) * 2015-03-03 2016-09-08 Apple Inc. Fan out system in package and method for forming the same
US20170194290A1 (en) * 2014-04-17 2017-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (sip) and the methods of making the same
US20170301650A1 (en) * 2016-04-15 2017-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Formation with Dies Bonded to Formed RDLs

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7872340B2 (en) 2007-08-31 2011-01-18 Stats Chippac Ltd. Integrated circuit package system employing an offset stacked configuration
IN2012DN00452A (zh) * 2009-07-30 2015-05-15 Megica Corp
KR102190382B1 (ko) * 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
KR102021077B1 (ko) 2013-01-24 2019-09-11 삼성전자주식회사 적층된 다이 패키지, 이를 포함하는 시스템 및 이의 제조 방법
TWI496270B (zh) * 2013-03-12 2015-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
KR102167599B1 (ko) 2014-03-04 2020-10-19 에스케이하이닉스 주식회사 칩 스택 임베디드 패키지
KR20150123420A (ko) 2014-04-24 2015-11-04 에스케이하이닉스 주식회사 반도체 패키지 및 그 제조 방법
US9859265B2 (en) * 2014-06-06 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming the same
EP3238250B1 (en) * 2014-12-24 2022-05-04 Intel Corporation Integrated passive components in a stacked integrated circuit package
US20160276308A1 (en) * 2015-03-17 2016-09-22 Samsung Electronics Co., Ltd. Thermally enhanced package-on-package structure
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
JP6478853B2 (ja) 2015-07-14 2019-03-06 新光電気工業株式会社 電子部品装置及びその製造方法
US9607967B1 (en) * 2015-11-04 2017-03-28 Inotera Memories, Inc. Multi-chip semiconductor package with via components and method for manufacturing the same
US9524959B1 (en) * 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
US9553071B1 (en) * 2016-01-11 2017-01-24 Invensas Corporation Multi-chip package with interconnects extending through logic chip
CN106558574A (zh) 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070296079A1 (en) * 2006-06-12 2007-12-27 Siliconware Precision Industries Co., Ltd. Heat dissipating structure and method for fabricating the same
US20100216410A1 (en) * 2009-02-20 2010-08-26 Aiconn Technology Corporation Radio transceiver module
US20150070863A1 (en) * 2013-09-06 2015-03-12 Qualcomm Incorporated Low package parasitic inductance using a thru-substrate interposer
US20170194290A1 (en) * 2014-04-17 2017-07-06 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (sip) and the methods of making the same
US20160260695A1 (en) * 2015-03-03 2016-09-08 Apple Inc. Fan out system in package and method for forming the same
US20170301650A1 (en) * 2016-04-15 2017-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Formation with Dies Bonded to Formed RDLs

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113808961A (zh) * 2020-08-06 2021-12-17 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN113808961B (zh) * 2020-08-06 2024-11-26 台湾积体电路制造股份有限公司 封装结构及其形成方法
CN113206070A (zh) * 2021-03-09 2021-08-03 日月光半导体制造股份有限公司 半导体封装结构及其形成方法

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CN111971792B (zh) 2022-12-06
JP7121137B2 (ja) 2022-08-17
WO2019209460A2 (en) 2019-10-31
US10714462B2 (en) 2020-07-14
US11018125B2 (en) 2021-05-25
JP2021514119A (ja) 2021-06-03
US20190326273A1 (en) 2019-10-24
KR102388697B1 (ko) 2022-04-20

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