CN111970008A - Turbo code decoder, soft input and soft output method, device and storage medium - Google Patents

Abstract

The present application discloses a turbo code decoder, a soft input and soft output method, an electronic device and a computer-readable storage medium. The turbo code decoder includes: a system buffer for receiving a system bit signal and a first address output by a bidirectional interleaver signal; the first parity check buffer is used for receiving the first error detection bit signal and the second address signal output by the bidirectional interleaver; the second parity check buffer is used for receiving the second error detection bit signal and the second address signal; the first The output signals of the first parity check buffer and the second parity check buffer are selected and output to the soft input and soft output unit through the data selector; the output signal of the system buffer and the decoded signal output by the bidirectional interleaver are added and respectively It is sent to the first shift register and the soft input and soft output unit; the output signal of the first shift register and the soft input soft output unit is sent to the threshold comparator after difference. The present application effectively reduces product cost and improves product economic benefit.

Description

A turbo code decoder and soft input soft output method, device and storage medium

technical field

The present application relates to the technical field of data encoding and decoding, and in particular, to a turbo code decoder, a soft input and soft output method, an electronic device, and a computer-readable storage medium.

Background technique

There are many methods for data transmission in general electronic products, and there are different communication protocols. Many encoding and decoding functions are used. Different encoding and decoding methods are realized by different algorithms. Therefore, the improvement and introduction of algorithm methods has become an important research direction.

Turbo code is a forward error correction coding technique in information theory. Turbo code is the first practical code that can approach the Shannon limit. It has excellent performance under low signal-to-noise ratio conditions and is widely used in 3G/4G mobile communications (such as UMTS and LTE), deep space satellite communications and other fields. The decoding process of the turbo code proceeds iteratively through a feedback loop, so named because it resembles the working process of a turbocharger in an internal combustion engine.

FIG. 1 is a structural frame diagram of a turbo decoder used in the related art. The turbo code decoder shown in FIG. 1 mainly includes two SISO units (Soft-In Soft-Out, soft input and soft output), an interleaver (interleave) and a de-interleaver (de-interleave). The decoding end uses the recursive idea to repeatedly decode the bit data decoded by the two SISO units, thereby reducing the error probability (BER) of the decoded bits.

Among them, the information decoded by SISO1 is the encoded information without the interleaver (systematic has been restored through the interleaver at the encoder end and the reverse interleaver at the decoder end), and the information decoded by SISO2 is the information processed by the interleaver. Thereby, it can be guaranteed that the order of the decoded information of the two SISO units is different. The soft output decoded by SISO2 is first processed by the reverse interleaver and then recursively processed to SISO1. When the number of recursion reaches the default upper limit, the output of SISO2 is the decoded output. However, due to the high cost of the SISO unit, the above-mentioned turbo code decoder will undoubtedly have a high product cost due to the need to use two SISO units.

In view of this, providing a solution to the above-mentioned technical problems is an urgent need for those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a turbo code decoder, a soft input and soft output method, an electronic device and a computer-readable storage medium, so as to effectively implement turbo code decoding and reduce product cost.

In order to solve the above technical problems, in the first aspect, the present application discloses a turbo code decoder, which includes a bidirectional interleaver, a system buffer, a first parity check buffer, a second parity check buffer, and soft input and soft output. a unit, a first shift register, a threshold comparator;

the system buffer is used for receiving the system bit signal and the first address signal output by the bidirectional interleaver;

the first parity check buffer is used for receiving the first error detection bit signal and the second address signal output by the bidirectional interleaver; the second parity check buffer is used for receiving the second error detection bit signal and the a second address signal; the output signals of the first parity check buffer and the second parity check buffer are selected and output to the soft input and soft output unit through a data selector;

The output signal of the system buffer and the decoded signal output by the bidirectional interleaver are added and sent to the first shift register and the soft input and soft output unit respectively; the first shift register and the The output signal of the soft input and soft output unit is sent to the threshold comparator after the error; the threshold comparator is used for outputting the input signal greater than the preset threshold to the bidirectional interleaver, so that the bidirectional interleaver can perform positive correction. The decoded signal is output interleaved in and in reverse.

Optionally, the bidirectional interleaver includes an address generator, a second shift register, a first memory, and a second memory;

The first output terminal of the address generator is connected to the system buffer for outputting the first address signal; the second output terminal of the address generator is respectively connected to the first parity buffer and the the second parity buffer is connected for outputting the second address signal;

The third output end of the address generator is connected to the second shift register for outputting a third address signal; after the third address signal and the output signal of the second shift register are passed through the data selector is selected and output to the first memory; the third address signal and the output signal of the second shift register are selected and output to the second memory after passing through a data selector; the first memory and the The input terminals of the second memory are all connected to the output terminal of the threshold comparator, and the output signals of the first memory and the second memory are selected and output through a data selector to be used as the decoded signal.

Optionally, the soft input and soft output unit is implemented based on a soft output maintenance ratio algorithm.

Optionally, the soft input and soft output unit includes a first branch path marking unit, a first addition, comparison and selection unit, and a survival path unit connected in sequence, and a first-in, first-out queue and a second branch path marking unit connected in sequence. , a second addition comparison selection unit and a path comparison unit, and a reliability value measurement unit;

Wherein, the first branch path value recording unit is connected in parallel with the input end of the FIFO queue as the data input end of the soft input and soft output unit; the maximum similar state point signal output by the surviving path unit and The decision bits output by the second addition, comparison and selection unit are all sent to the path comparison unit, so that the path comparison unit outputs a hard output signal;

The path measurement difference output by the second addition, comparison and selection unit is selected as a reliability value and output after a data selector; The associated bits of the output are used to calculate the output soft output signal.

In the second aspect, the present application also discloses a soft-input soft-output method, which is applied to the above-mentioned soft-input soft-output unit, including:

Determine the path value of each branch path;

Determine surviving paths and competing paths in branch paths;

Taking the path value of the surviving path as the current path value, and storing the decision bit of the current path value;

outputting a hard output signal based on the current path value and the decision bit;

determining the credibility value of the current path value based on the path difference between the surviving path and the contending path;

A soft output signal is output based on the confidence value.

Optionally, after the determining of the survival path and the contention path in the branch paths and before the outputting the soft output signal based on the reliability value, the method further includes:

comparing binary decoding results of the surviving path and the competing path;

If the results are different, the confidence value is updated.

In a third aspect, the present application also discloses an electronic device, comprising:

memory for storing computer programs;

The processor is configured to execute the computer program to implement the steps of any of the above-mentioned soft input and soft output methods.

In a fourth aspect, the present application also discloses a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, is used to implement any of the above software. Enter the steps of the soft output method.

The turbo code decoder provided by the present application includes a bidirectional interleaver, a system buffer, a first parity check buffer, a second parity check buffer, a soft input and soft output unit, a first shift register, and a threshold comparator; The system buffer is used for receiving the system bit signal and the first address signal output by the bidirectional interleaver; the first parity check buffer is used for receiving the first error detection bit signal and the second output signal from the bidirectional interleaver. address signal; the second parity check buffer is used for receiving the second error detection bit signal and the second address signal; the output signals of the first parity check buffer and the second parity check buffer After the data selector, it is selected and output to the soft input and soft output unit; the output signal of the system buffer is added with the decoded signal output by the bidirectional interleaver, and then sent to the first shift register and the first shift register respectively. the soft input soft output unit; the output signal of the first shift register and the soft input soft output unit is sent to the threshold comparator after difference; the threshold comparator is used to A signal is output to the bidirectional interleaver so that the bidirectional interleaver performs forward and reverse interleaving to output the decoded signal.

The turbo code decoder, the soft input and soft output method, the electronic device and the computer-readable storage medium provided by the present application have the beneficial effects that: based on the improved circuit structure and the use of other related devices, the present application effectively improves the performance of a single software The time usage rate of the input soft output unit can effectively reduce the number of soft input soft output units used in the turbo code decoder while ensuring the same decoding effect and decoding speed, thereby effectively reducing product costs and improving product economic benefits. .

Description of drawings

In order to more clearly illustrate the prior art and the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings to be used in the description of the prior art and the embodiments of the present application. Of course, the following drawings related to the embodiments of the present application describe only a part of the embodiments of the present application. For those of ordinary skill in the art, without any creative effort, they can also obtain other embodiments according to the provided drawings. The accompanying drawings and other drawings obtained also belong to the protection scope of the present application.

1 is a schematic structural diagram of a turbo code decoder in the related art;

FIG. 2 is a schematic structural diagram of a turbo code decoder disclosed in an embodiment of the present application;

3 is a schematic structural diagram of another turbo code decoder disclosed in an embodiment of the present application;

4 is a schematic structural diagram of a soft input and soft output unit disclosed in an embodiment of the application;

5 is a flowchart of a method for soft output and hard output disclosed in an embodiment of the present application;

FIG. 6 is a structural block diagram of an electronic device disclosed in an embodiment of the present application.

Detailed ways

The core of the present application is to provide a turbo code decoder, a soft input and soft output method, an electronic device and a computer-readable storage medium, so as to effectively realize turbo code decoding and reduce product cost.

In order to describe the technical solutions in the embodiments of the present application more clearly and completely, the technical solutions in the embodiments of the present application will be introduced below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

There are many methods for data transmission in general electronic products, and there are different communication protocols. Many encoding and decoding functions are used. Different encoding and decoding methods are realized by different algorithms. Therefore, the improvement and introduction of algorithm methods has become an important research direction.

Turbo code is a forward error correction coding technique in information theory. Turbo code is the first practical code that can approach the Shannon limit. It has excellent performance under low signal-to-noise ratio conditions and is widely used in 3G/4G mobile communications (such as UMTS and LTE), deep space satellite communications and other fields. The decoding process of the turbo code proceeds iteratively through a feedback loop, so named because it resembles the working process of a turbocharger in an internal combustion engine.

FIG. 1 is a structural frame diagram of a turbo decoder used in the related art. The turbo code decoder shown in FIG. 1 mainly includes two SISOs (Soft-In Soft-Out, soft input and soft output), an interleaver (interleave) and a de-interleaver (de-interleave). The decoding end uses the recursive idea to repeatedly decode the bit data decoded by the two SISO units, thereby reducing the error probability (BER) of the decoded bits.

Among them, the information decoded by SISO1 is the encoded information without the interleaver (systematic has been restored through the interleaver at the encoder end and the reverse interleaver at the decoder end), and the information decoded by SISO2 is the information processed by the interleaver. This ensures that the order of the decoded information of the two SISOs is different. The soft output decoded by SISO2 is first processed by the reverse interleaver and then recursively processed to SISO1. When the number of recursion reaches the default upper limit, the output of SISO2 is the decoded output. However, due to the high cost of SISO, the above-mentioned turbo code decoder undoubtedly has a high product cost due to the need to use two SISOs. In view of this, the present application provides a technical solution that can effectively solve the above problems.

Referring to FIG. 2 , an embodiment of the present application discloses a turbo code decoder, which mainly includes a bidirectional interleaver 100, a system buffer 200, a first parity check buffer 300, a second parity check buffer 400, a software input soft output unit 500, first shift register 600, threshold comparator 700;

The system buffer 200 is configured to receive the system bit signal ys and the first address signal addr_1 output by the bidirectional interleaver 100;

The first parity check buffer 300 is used for receiving the first error detection bit signal yp1 and the second address signal addr_2 output by the bidirectional interleaver 100; the second parity check buffer 400 is used for receiving the second error detection bit signal yp2 and The second address signal addr_2; the output signals of the first parity check buffer 300 and the second parity check buffer 400 are selected and output to the soft input and soft output unit 500 after passing through the data selector;

The output signal of the system buffer 200 is added with the decoded signal output by the bidirectional interleaver 100 and then sent to the first shift register 600 and the soft input soft output unit 500 respectively; The output signal is sent to the threshold comparator 700 after the difference; the threshold comparator 700 is used to output the input signal greater than the preset threshold to the bidirectional interleaver 100, so that the bidirectional interleaver 100 performs forward and reverse interleaving and outputs the decoded signal .

It should be noted that when using the soft input and soft output unit 500 to perform turbo code decoding, the turbo decoder of this structure provided by the present application only needs to use one SISO, and does not require excessive product cost consumption. According to the hybrid trace-back scheme, the SISO unit used in the present application can achieve faster path searching, and the memory capacity requirement for storing paths is also reduced by 70% compared with the traditional method.

Those skilled in the art can easily understand that, in the turbo code decoder with the structure shown in FIG. 1 in the prior art, before the interleaver or the reverse interleaver operates, it must wait for all the data to be interleaved to be ready. , that is, after the SISO decoding of the previous level is completed, the missed data can be sent to the next level SISO. Therefore, only one SISO is working at the same time, while another SISO is waiting for data, so that the time utilization rate of the SISO hardware is only 50%, which wastes hardware cost and hardware layout space. In the present application, by adjusting the circuit structure of the decoder and using some low-cost devices such as system buffers, parity check buffers, etc., the SISO can achieve a 100% time utilization rate, so that only one SISO can be used. Complete the turbo code decoding; and the decoding speed will not be affected in any way.

It can be seen that the turbo code decoder disclosed in the embodiment of the present application, based on the improved circuit structure and the use of other related devices, effectively improves the time usage rate of a single soft input and soft output unit, thereby ensuring the same decoding effect and decoding effect. In the case of high speed, the number of soft input and soft output units used in the turbo code decoder is effectively reduced, thereby effectively reducing the cost of the product and improving the economic benefit of the product.

Referring to FIG. 3 , FIG. 3 is another turbo code decoder disclosed by an embodiment of the present application.

On the basis of the above content, in the turbo code decoder disclosed in the embodiment of the present application, in a specific implementation manner, the bidirectional interleaver 100 includes an address generator 101, a second shift register 102, a first memory 103, a second two memory 104;

The first output terminal of the address generator 101 is connected to the system buffer 200 for outputting the first address signal addr_1; the second output terminal of the address generator 101 is connected to the first parity check buffer 300 and the second parity check buffer 300 respectively. The buffer 400 is connected for outputting the second address signal addr_2;

The third output terminal of the address generator 101 is connected to the second shift register 102 for outputting the third address signal addr_3; the third address signal addr_3 and the output signal of the second shift register 102 are selected and output after the data selector to the first memory 103; the third address signal addr_3 and the output signal of the second shift register 102 are selected and output to the second memory 104 through the data selector; the input terminals of the first memory 103 and the second memory 104 are both equal to the threshold The output end of the comparator 700 is connected, and the output signals of the first memory 103 and the second memory 104 are selected and outputted by the data selector to serve as the decoded signal.

On the basis of the above content, in a specific implementation manner of the turbo code decoder disclosed in the embodiment of the present application, the soft input and soft output unit used by it, namely SISO, is specifically based on the soft output maintenance ratio algorithm (Soft Output Viterbi DecodingAlgorithm) is implemented by SOVDA algorithm.

Specifically, in the SOVA architecture, in addition to using the Trace Back (TB) method to reconstruct the survival path (survivor path), it is also necessary to reconstruct all state points at each time point (Time step). Competing paths, and updating the credibility value of each state point on the competing paths.

That is, the process of outputting by SISO may roughly include two processes: the first process, calculating the maximum similarity path (Maximum Likelihood Path, MLP), and the maximum similarity state point (Maximum Likelihood Path, MLP) that exists in the maximum similarity path at each time point Likelihood State, MLS); the second process, calculate and update the credibility value.

Referring to FIG. 4 , FIG. 4 is a schematic structural diagram of a soft input and soft output unit 500 disclosed in an embodiment of the present application.

On the basis of the above content, in the turbo code decoder disclosed in the embodiment of the present application, in a specific implementation, the soft input and soft output unit 500 includes a first branch path value unit BMU1 connected in sequence, a first addition and comparison The selection unit ACSU1 and the surviving path unit SMU, and the first-in-first-out queue FIFO, the second branch path marking unit BMU2, the second addition comparison selection unit ACSU2, the path comparison unit PCU, and the reliability value measurement unit RMU connected in sequence;

Wherein, the first branch path value unit (Branch Metric Unit) BMU1 is connected in parallel with the input end of the FIFO queue, as the data input end of the soft input soft output unit 500; the surviving path memory unit (Surviving path Memory Unit) SMU output The maximum similar state point and the decision bits (Decision bits) output by the second addition, comparison and selection unit ACSU2 are all sent to the path comparison unit (Path Comparison Unit) PCU, so that the path comparison unit PCU outputs a hard output signal;

The path metric difference (Path metric difference) output by the second addition, comparison and selection unit ACSU2 is selected as the reliability value output after the data selector; Reliability Value) and the relative bits (Relevance bits) output by the path comparison unit PCU to determine and output the soft output signal.

Specifically, in the first process of the SOVDA algorithm, the surviving path unit SMU is used to calculate the maximum similarity path and generate the maximum similarity state point. In the second process, the path comparison unit PCU generates relevant bits (Relevance bits) according to the decision bits (Decision bits) provided by the addition, comparison and selection unit ACSU1, and sends them to the Reliability Measure Unit (RMU) for processing. , to calculate and generate the soft output value (Soft-Output). The reliability measurement unit will first store the initially calculated reliability value, then decide whether to update the reliability value according to the associated bits, and output the final reliability value as a soft output value.

Further, as a specific embodiment, this embodiment does not update the credibility value of all survival paths, but only calculates and updates the credibility value of the last updated survival path, so as to further Improve computational efficiency. In fact, for other survival paths not obtained by the last update, whether or not the reliability value of the updated reliability value does not affect the final output result. This embodiment excludes these redundant actions, which can improve the processing rate.

Correspondingly, the present application also discloses a method for performing soft output and hard output by a soft input and soft output unit. For details, please refer to Figure 5, which mainly includes:

S11: Determine the path value of each branch path.

S12: Determine the surviving path and the competing path in the branch path.

S13: Take the path value of the surviving path as the current path value, and store the decision bit of the current path value.

S14: Output a hard output signal based on the current path value and the decision bit.

S15: Determine the credibility value of the current path value based on the path difference between the surviving path and the competing path.

S16: Output a soft output signal based on the reliability value.

On the basis of the above content, in the method for soft output and hard output provided by the soft input and soft output unit provided by the embodiment of the present application, as a specific embodiment, after determining the survival path and the contention path in the branch path, based on the available Before the reliability value outputs the soft output signal, it also includes:

Compare the binary decoding results of the surviving path and the competing path;

If the results are different, update the confidence value.

For the specific content of the above-mentioned soft output and hard output method, reference may be made to the foregoing detailed introduction on the structure of the soft output and hard output in the turbo code decoder, which will not be repeated here.

Further, as shown in FIG. 5 , an embodiment of the present application discloses an electronic device, including:

memory 21 for storing computer programs;

The processor 22 is configured to execute the computer program to implement the steps of any of the above-mentioned soft input and soft output methods.

Further, an embodiment of the present application also discloses a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and the computer program is used to implement any of the above when executed by a processor. The steps of the soft input soft output method.

For the specific content of the electronic device and the computer-readable storage medium, reference may be made to the foregoing detailed introduction on the soft input and soft output method, which will not be repeated here.

The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

It should also be noted that, in this application document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require Or imply that there is any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion such that a process, method, article or device comprising a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The technical solutions provided by the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the present application.

Claims (8)

1. A turbo code decoder is characterized by comprising a bidirectional interleaver, a system buffer, a first parity check buffer, a second parity check buffer, a soft input soft output unit, a first shift register and a threshold comparator;

the system buffer is used for receiving a system bit signal and a first address signal output by the bidirectional interleaver;

the first parity check buffer is used for receiving a first error detection bit signal and a second address signal output by the bidirectional interleaver; the second parity check buffer is used for receiving a second error detection bit signal and the second address signal; the output signals of the first parity check buffer and the second parity check buffer are selected and output to the soft input soft output unit after passing through a data selector;

the output signal of the system buffer and the decoding signal output by the bidirectional interleaver are added and then are respectively sent to the first shift register and the soft input soft output unit; the output signals of the first shift register and the soft input and soft output unit are subjected to difference and then sent to the threshold comparator; the threshold comparator is used for outputting an input signal larger than a preset threshold to the bidirectional interleaver, so that the bidirectional interleaver performs forward and reverse interleaving and outputs the decoding signal.

2. The turbo decoder of claim 1, wherein the bidirectional interleaver comprises an address generator, a second shift register, a first memory, a second memory;

a first output end of the address generator is connected with the system buffer and used for outputting the first address signal; a second output terminal of the address generator is connected to the first parity buffer and the second parity buffer, respectively, for outputting the second address signal;

a third output end of the address generator is connected with the second shift register and used for outputting a third address signal; the third address signal and the output signal of the second shift register are selected and output to the first memory after passing through a data selector; the third address signal and the output signal of the second shift register are selected and output to the second memory after passing through a data selector; the input ends of the first memory and the second memory are both connected with the output end of the threshold comparator, and output signals of the first memory and the second memory are selected and output after passing through the data selector so as to serve as the decoding signals.

3. Turbo code decoder according to claim 1 or 2, wherein said soft input soft output unit is implemented based on a soft output maintenance ratio algorithm.

4. The turbo code decoder of claim 3, wherein the soft input soft output unit comprises a first branch path score unit, a first addition comparison selection unit and a survivor path unit which are connected in sequence, and a first-in-first-out queue, a second branch path score unit, a second addition comparison selection unit and a path comparison unit which are connected in sequence, and a confidence value measurement unit;

the first branch path value recording unit is connected in parallel with the input end of the first-in first-out queue and is used as the data input end of the soft input and soft output unit; the maximum similar state point signal output by the survivor path unit and the decision bit output by the second addition comparison selection unit are both sent to the path comparison unit, so that the path comparison unit outputs a hard output signal;

the path metering difference value output by the second addition comparison selection unit is selected as a reliability value to be output after passing through the data selector; so that the reliability value measuring unit calculates and outputs a soft output signal according to the reliability value and the associated bit output by the path comparing unit.

5. A soft-input soft-output method applied to the soft-input soft-output unit of claim 1, comprising:

determining a path value of each branch path;

determining a survival path and a competition path in the branch paths;

taking the path value of the survival path as a current path value, and storing a decision bit of the current path value;

outputting a hard output signal based on the current path value and the decision bit;

determining a confidence value of the current path value based on a path difference value of the surviving path and the competing path;

outputting a soft output signal based on the confidence value.

6. A soft-input soft-output method according to claim 5, further comprising, after determining surviving and competing ones of the branch paths and before outputting a soft-output signal based on the confidence value:

comparing the binary decoding results of the surviving path and the competing path;

and if the results are different, updating the reliability value.

7. An electronic device, comprising:

a memory for storing a computer program;

a processor for executing the computer program to implement the steps of the soft-input soft-output method as claimed in claim 5 or 6.

8. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the soft-input soft-output method according to claim 4 or 5.

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