CN111969044B - semiconductor device - Google Patents

Abstract

The invention discloses a semiconductor device, which comprises a substrate, an active structure and a shallow trench isolation. The active structure is arranged in the substrate and comprises a plurality of first active regions and a second active region, and the second active region is arranged outside the first active regions. The second active region further includes a plurality of corners, each of which has an angle greater than 90 degrees. The shallow trench isolation is arranged in the substrate and surrounds the active structure. The semiconductor device of the invention is provided with the reinforced corner structure, thereby improving the stress around the semiconductor device and avoiding the collapse or damage of the semiconductor structure.

Description

semiconductor device

technical field

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including an active structure and shallow trench isolation.

Background technique

With the miniaturization of semiconductor devices and the complication of integrated circuits, the size of the device is continuously reduced and the structure of the device is constantly changing. Therefore, maintaining the performance of the small-sized semiconductor device is currently the main goal of the industry. In the semiconductor fabrication process, a plurality of active regions are generally defined on a substrate as a basis, and then required components are formed on the active regions. Generally speaking, the active area is formed with multiple patterns on the substrate by photolithography and etching. However, under the requirement of size reduction, the width of the active area is gradually reduced, and the spacing between the active areas It is also gradually shrinking, so that its manufacturing process also faces many limitations and challenges, which together affect the structural stability of the active area, and are prone to structural collapse or damage, so that they cannot meet product requirements.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a semiconductor device with an active structure having reinforced corners and/or periphery, whereby the stress around the semiconductor device can be improved and the collapse or damage of the semiconductor structure can be avoided.

To achieve the above object, an embodiment of the present invention provides a semiconductor device including a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate, and includes a plurality of first active regions and a second active region, the second active region is disposed outside the first active regions, wherein the second active region is The source region also includes a plurality of corners, each of which has an angle greater than 90 degrees. The shallow trench isolation is disposed in the substrate and surrounds the active structure.

To achieve the above object, an embodiment of the present invention provides another semiconductor device including a substrate, an active structure, and a shallow trench isolation. The active structure is disposed in the substrate, the active structure includes a plurality of first active regions, a second active region and a plurality of third active regions, the first active regions and the third active regions The active regions are parallel to each other, separated from each other and alternately arranged along a first direction, the second active region is arranged between the first active regions and the third active regions, and surrounds the first active regions an active area. The shallow trench isolation is disposed in the substrate and surrounds the active structure.

In the semiconductor device of the present invention, a structure that can strengthen the corners is arranged around the device, such as corners larger than 90 degrees, thickened sides, or extensions extending to the inside or outside, so that the device can be more stable around the device. , Reinforced structure to protect the components inside the device from collapse or damage to the structure. Thereby, the stress around the semiconductor device can be improved, and the collapse or damage of the semiconductor structure can be avoided.

Description of drawings

1 to 2 are schematic diagrams of a semiconductor device according to a first preferred embodiment of the present invention; wherein

FIG. 1 is a schematic top view of a semiconductor device of the present invention; and

Fig. 2 is the sectional schematic diagram along tangent A-A' of Fig. 1;

3 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;

4 is a schematic diagram of a semiconductor device according to a second preferred embodiment of the present invention;

5 is a schematic diagram of a semiconductor device according to a third preferred embodiment of the present invention;

6 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;

7 is a schematic diagram of a semiconductor device according to another embodiment of the present invention;

8 is a schematic diagram of a semiconductor device according to a fourth preferred embodiment of the present invention;

FIG. 9 is a schematic diagram of a semiconductor device according to another embodiment of the present invention.

Among them, the reference numerals are described as follows:

100, substrate; 110, shallow trench isolation; 111, trench; 113, dielectric layer; 130, active structure; 131, first active region; 132, opening; 133, second active region; 133a, first side; 133b, second side; 133c, third side; 135, extension; 431, third active region; 435, extension; 531, third active region.

Detailed ways

In order to enable those skilled in the art to which the present invention pertains to further understand the present invention, several preferred embodiments of the present invention are listed below, together with the accompanying drawings, to describe in detail the composition of the present invention and what it wants to achieve effect.

Please refer to FIG. 1 to FIG. 2 , which are schematic diagrams of a semiconductor device according to a first preferred embodiment of the present invention. First, referring to FIG. 1 , a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (eg, SiC, SiGe) or a silicon-on-insulator (SOI) substrate, etc. The substrate 100 is provided with at least A shallow trench isolation (STI) 110 defines an active structure 130 on the substrate 100 , that is, the STI 110 is disposed around the active structure 130 . The active structure 130 further includes a plurality of first active regions 131 disposed in the first region (not shown), and a second active region 133 disposed in the second region (not shown), wherein the The first area is, for example, an area with a relatively high component accumulation degree, and the second area is an area with a relatively low component accumulation degree, and is disposed outside the first area to surround the first area. For example, when the semiconductor device is a storage device, the first region is, for example, a storage region, and the second region is, for example, a peripheral region, but not limited thereto.

In detail, the first active regions 131 extend along a first direction D1 in parallel and spaced apart from each other, and are alternately arranged along the first direction D1. In one embodiment, each of the first active regions 131 is sequentially arranged in a plurality of rows along a second direction D2 (for example, the x direction) in the first region, and can present a specific arrangement as a whole, as shown in FIG. The array arrangement shown in 1, etc., is not limited to this. The first active region 131 is formed by a patterning process of the substrate 100 . For example, a mask layer (not shown) is firstly formed on the substrate 100 , and the mask layer includes a mask layer for defining the first active region 131 . A plurality of patterns are formed and part of the substrate 100 is exposed, an etching process is performed using the mask layer, the part of the substrate 100 is removed to form a trench 111, and a dielectric layer 113, such as silicon oxide, nitride, is formed in the trench 111 Silicon or silicon oxynitride, etc., can form the shallow trench isolation 110 whose top surface is flush with the surface of the substrate 100 , and at the same time define the first active region 131 , as shown in FIG. 2 . In one embodiment, the first active region 131 can also be formed by a self-aligned double patterning (SADP) process, or a self-aligned reverse patterning (self-aligned reverse patterning) , SARP) manufacturing process, but not limited to this.

The second active region 133 is disposed outside the first active region 131 and completely surrounds the first active region 131 . In this embodiment, the second active region 133 further includes at least one first side 133a extending along the second direction D2, at least one second side 133b extending along the third direction D3, and at least one second side 133b extending along a third direction D3. At least one third side 133c extending in the four directions D4, each first side 133a, each third side 133c and each second side 133b are adjacent to each other and are arranged in sequence, so that the second active region 133 can be arranged around the first around an active region 131 . In other words, the second active region 133 surrounds the outside of the first region, and the second region is located outside the second active region 133 . The second direction D2 is, for example, perpendicular to the third direction D3, and the fourth direction D4 is not perpendicular to the first direction D1, the second direction D2, and the third direction D3. For example, the second direction D2 is, for example, x direction, and the third direction D3 is, for example, the y direction, as shown in FIG. 1 , but not limited thereto. In addition, the first side 133a, the second side 133b and the third side 133c may have the same width T1, and the width T1 may be equal to or not equal to the width W of the respective first active regions 131, but not limited to this.

It should be noted that the third side 133c of the second active region 133 is disposed between the first side 133a and the second side 133b, and thus, the first side 133a and the third side 133c of the second active region 133 A first edge angle θ1 can be further sandwiched therebetween, and a second edge angle θ2 can also be sandwiched between the second edge 133b and the third edge 133c of the second active region 133 . The first edge angle θ1, The second edge angle θ2 is preferably an obtuse angle greater than 90 degrees, for example, about 100 degrees to 140 degrees, so that the periphery of the second active region 133 can have a relatively stable structure and can avoid tipping. In one embodiment, the angle of the first side angle θ1 can be selected to be equal to the angle of the second side angle θ2 , as shown in FIG. 1 , but not limited thereto. In another embodiment, the angle of the first side angle θ1 can also be selected to be different from the angle of the second side angle θ2.

On the other hand, the arrangement of the second active region 133 can also choose to directly contact or not contact the first active region 131 surrounding it. That is, when the second active region 133 is disposed, a part of the first active region 131 can be further connected to the first side 133a, the second side 133b or the third side 133c of the second active region 133, and , so that another part of the first active region 131 is not connected to the first side 133 a , the second side 133 b or the third side 133 c of the second active region 133 , but is spaced therefrom. For example, in one embodiment, the second side 133b of the second active region 133 directly contacts an adjacent part of the first active region 131, and does not contact another adjacent part of the first active region 131, and the first active region 131 The first sides 133a of the two active regions 133 do not contact any adjacent first active regions 131 at all, as shown in FIG. 1 . In addition, in the first active region 131, a portion of the first active region 131 that contacts the second side 133b and a portion of the first active region 131 that does not contact the second side 133b may be alternately arranged, as shown in FIG. 1 . Show. The number of the part of the first active regions 131 that do not contact the second side 133b is, for example, an even number, but not limited thereto. Under this arrangement, the second side 133b of the second active region 133 can bear the stress from the first active region 131 and the shallow trench isolation 110 relatively uniformly, so as to obtain a more stable structure. However, those skilled in the art should easily understand that although the second side 133b of the second active region 133 is partially in contact with a portion of the adjacent first active region 131 in the foregoing embodiment, the second side 133b of the second active region 133 The one side 133a does not contact the adjacent first active region 131 at all as an embodiment, but the specific arrangement is not limited to this. In another embodiment, the reverse setting can also be selected according to actual product requirements, that is, the first side portion of the second active region can be made to contact a part of the adjacent first active region, and the first active region can be The second sides of the two active regions do not contact the adjacent first active regions at all; alternatively, the first or second sides of the second active regions can also contact all the adjacent first active regions, to obtain a more stable structure. In another embodiment, the third side 133c located between the first edge angle θ1 and the first edge angle θ2 can also choose to directly contact an adjacent part of the first active region 131 and not contact another adjacent part The first active region 131 is shown in FIG. 1 . In addition, the number of the first active regions 131 directly contacting the third side 133c is preferably five or more, but not limited. Under this arrangement, the third side 133c of the second active region 133 can also bear the stress from the first active region 131 and the shallow trench isolation 110 relatively uniformly, so as to obtain a more stable structure.

In addition, it should be noted that in this embodiment, the formation of the second active region 133 can also be performed by the patterning process of the substrate 100 , and the patterning process of the first active region 131 can be selected. and proceed. That is to say, in this embodiment, the same or different mask layers can be used to define the patterns of the first active region 131 and the second active region 133 at the same time or separately, and then the substrate 100 can be etched to form a dielectric. Layer 113. Here, the first active region 131 and the second active region 133 may include the same material (the material of the substrate 100 ), and the first active region 131 is connected to the first side 133 a of the second active region 133 , Parts of the second side 133b or the third side 133c can be integrally formed, as shown in FIG. 1 . In this case, the portion of the first active region 131 connected to the first side 133a, the second side 133b or the third side 133c of the second active region 133 can be regarded as the first side of the second active region 133 An extension of the side 133a, the second side 133b or the third side 133c extending into the first area, so that the second active area 133 can have a relatively stable and strengthened structure, so as to protect the first active area disposed on the inner side thereof. The source region 131 avoids structural collapse or damage. However, those skilled in the art should understand that the formation of the second active region is not limited to the foregoing method, and may be formed by other methods, for example, it may be performed separately from the fabrication process of the first active region. For example, in another embodiment, the fabrication process of the second active region can also be selected to be performed before the fabrication process of the first active region, and the second active region is first formed by using the patterning fabrication process of the substrate , and then form the first active region by means of an epitaxial growth process (not shown), where the top surfaces of the second active region and the first active region may not be coplanar ( (not shown); or, in another embodiment, the fabrication process of the second active region can also be selected to be performed after the fabrication process of the first active region, and the patterned fabrication process of the substrate is used to form the first active region. A first active area, and then a deposition process is used to form the second active area (for example, including polysilicon, dielectric material, etc. different from the material of the substrate), here, the second active area and the first active area Zones can contain different materials.

Therefore, in the semiconductor device according to the first preferred embodiment of the present invention, the first side 133a, the second side 133b and the third side 133c extending in different directions are provided in the second active region 133. The side 133b and the third side 133c sandwich a first side angle θ1 and a second side angle θ2 with an angle greater than 90 degrees, or are connected to the first active The region 131 enables the second active region 133 to have a relatively stable and strengthened structure, so as to improve the stress around the semiconductor device and avoid the collapse or damage of the structure.

Those skilled in the art to which the present invention pertains should readily understand that, on the premise of meeting actual product requirements, the semiconductor device of the present invention may also have other aspects, which are not limited to the foregoing. For example, in one embodiment, it is also possible to adjust the etching conditions during the patterning process of the second active region 133 so that the third edge angle θ1 ′ and the fourth edge angle θ2 are formed. ' Partially rounded corners, as shown in Figure 3, but not limited thereto. In another embodiment, a plurality of openings 132 may also be formed on the first side 133a and/or the second side 133b of the second active region 133 , as shown in FIG. 3 , but not limited thereto. The number or size of the openings 132 (for example, the width or length in the second direction D2 or the third direction D3) can be adjusted according to the actual component requirements, not limited to the one shown in FIG. The structural strength of the second active region 133 on the first side 133a and/or the second side 133b is enhanced. In addition, other embodiments or variations of the semiconductor device will be further described below. In order to simplify the description, the following description mainly focuses on the differences between the embodiments, and does not repeat the same points. In addition, the same components in the various embodiments of the present invention are marked with the same reference numerals, so as to facilitate the mutual comparison of the various embodiments.

Please refer to FIG. 4 , which is a schematic diagram of a semiconductor device in a second preferred embodiment of the present invention. The semiconductor device of this embodiment is substantially the same as the semiconductor device of the first preferred embodiment, and also includes a substrate 100 , a shallow trench isolation 110 and an active structure 130 , and the similarities will not be repeated. The main difference between this embodiment and the previous embodiments is that the third side 133c of the second active region 133 may have a relatively large width T2, that is, the width T2 of the third side 133c may be greater than that of the first side 133a or The width T1 of the second side 133b is not limited. Moreover, in one embodiment, the width T2 of the third side 133c is, for example, about twice or more than the width W of each of the first active regions 131, but not limited thereto.

Therefore, the semiconductor device according to the second preferred embodiment of the present invention can further strengthen the structural strength of the second active region 133 by virtue of the arrangement of the third side 133c, especially in the areas adjacent to the first side angle θ1 and the second side angle θ2 position to improve stress around the semiconductor device and avoid structural collapse or damage.

Please refer to FIG. 5 , which is a schematic diagram of a semiconductor device in a third preferred embodiment of the present invention. The semiconductor device of this embodiment is substantially the same as the semiconductor device of the first preferred embodiment, and also includes a substrate 100 , a shallow trench isolation 110 and an active structure 130 , and the similarities will not be repeated. The main difference between this embodiment and the previous embodiment is that an extension portion 135 is additionally provided on the third side 133 c of the second active region 133 . For example, the extension portion 135 is integrally formed with the third side 133c of the second active region 133, and is disposed on the side of the third side 133c away from the first active region 131, that is, the extension portion 135 extends outward to the side of the third side 133c. The second region is used to further strengthen the structural strength of the second active region 133 outside the positions adjacent to the first edge angle θ1 and the second edge angle θ2.

Therefore, the semiconductor device according to the third preferred embodiment of the present invention can further strengthen the structural strength of the second active region 133 by means of the arrangement of the third side 133 c and the extension portion 135 , so as to improve the stress around the semiconductor device and avoid structural collapse. or damaged. In addition, those skilled in the art should understand that, in the foregoing embodiment, the number, shape or size of the extending portion can be adjusted according to actual component requirements, and is not limited to what is shown in FIG. 5 . For example, in another embodiment, extending portions 135 with different widths may also be provided on the third side 133 c of the second active region 133 , as shown in FIG. 6 . In one embodiment, the extension portion 135 is, for example, a generally triangular shape, and is integrally formed with the third side 133c to further strengthen the structural strength of the second active region 133 adjacent to the first corner θ1 and the second corner θ2 , but not limited to this. Alternatively, in another embodiment, a plurality of extension parts 135 can also be optionally provided, as shown in FIG. 7 . Each extension 135 has, for example, the same size and shape, and is arranged at equal intervals on the side of the third side 133c away from the first active region 131 to further strengthen the second active region 133 adjacent to the first corner θ1 , the structural strength at the position of the second edge angle θ2, but not limited thereto.

Please refer to FIG. 8 , which is a schematic diagram of a semiconductor device in a fourth preferred embodiment of the present invention. The semiconductor device of this embodiment is substantially the same as the semiconductor device in the foregoing preferred embodiment, and also includes a substrate 100 , a shallow trench isolation 110 and an active structure 130 , and the similarities will not be repeated. The main difference between the present embodiment and the foregoing embodiments is that the extension portion on the third side 133 c extending outward to the second region can also be formed by the first active region 131 .

Specifically, in the embodiment in which the first active region 131 and the second active region 133 are formed together through the same patterning process, the first side connected to the second active region 133 can also be selected. 133a, the second side 133b or a part of the first active region 131 of the third side 133c further extends outward into the second region to form a plurality of extension parts 435, so that the extension parts 435 can interact with the first active region 131 have the same extension direction (ie, the first direction D1). In other words, in the aforementioned preferred embodiment, the part of the first active region 131 connected to the first side 133a, the second side 133b or the third side 133c can be regarded as not only the first side 133a, the second side 133b or the third side An extension of the side 133c extending into the first region, the part of the first active region 131 protruding from the second active region 133 can be further reserved and regarded as the first side 133a and the second side 133b Or the extension 435 of the third side 133c extending toward the second area, as shown in FIG. 8 . In this way, both the inner side (ie, the first region) and the outer side (ie, the second region) of the second active region 133 have relatively stable and strengthened structures, so as to further protect the first region disposed in the first region. In the active region 131, structure collapse or damage is avoided.

It should be noted that, depending on the degree of connection between each of the first active regions 131 and the first side 133a, the second side 133b or the third side 133c, each of the extending portions 435 may have the same or different lengths, respectively, as shown in FIG. 8 . shown. For example, the plurality of extension portions 435 connected to the third side 133c may have different lengths in the first direction D1 respectively; the plurality of extension portions 435 connected to the second side 133b all have different lengths in the first direction D1 The same length, but not limited. In another embodiment, the actual manufacturing process can also be adjusted so that the extension parts connected to the third side 133c all have the same length, or the extension parts connected to the second side 133b have different lengths respectively .

In addition, in one embodiment, a plurality of third active regions 431 can be optionally added in the second region. The third active regions 431 also extend along the first direction D1 in parallel and spaced apart from each other. Furthermore, the third active regions 431 are preferably arranged in the same manner as the first active regions 131 in the first region. For example, the third active regions 431 are also arranged in sequence along the second direction D2. plural lines. Therefore, the third active region 431 and the first active region 131 can be in a specific arrangement as a whole, such as the array arrangement shown in FIG. 8 , but not limited thereto. In one embodiment, the third active region 431 can be selected to directly surround the outer side of the second active region 133, and then the first active regions 131 in the first region continue to be sequentially arranged outwards. The active region 133 may be located between the first active region 131 and the third active region 431, but does not directly contact the first active region 131 and the third active region 431, as shown in FIG. This is the limit. In this way, the structure in the second region can be further stabilized to avoid collapse or damage of the structure.

Therefore, the semiconductor device according to the fourth preferred embodiment of the present invention can further strengthen the structural strength of the second active region 133 by means of the extension portion 435 and the third active region 431 disposed in the second region, so as to improve the semiconductor device surrounding stress to avoid collapse or damage to the structure. In addition, those skilled in the art should understand that the number of the third active regions 431 and their relative relationship with the second active regions 133 in the foregoing embodiments can be adjusted according to actual device requirements, and the number of the third active regions 431 in the foregoing embodiments can be adjusted according to actual device requirements. Display is limited. For example, in another embodiment, the plurality of third active regions 531 added in the second region can also be selected from the first side 133 a , the second side 133 b or the third side of the second active region 133 . The sides 133c can be separated from each other by a distance G, instead of directly surrounding the outer side of the second active region 133, in other words, the first side 133a, the second A shallow trench isolation 110 may also be provided between the side 133b or the third side 133c to further separate the third active region 531 and the second active region 133, as shown in FIG. 9 . Under this arrangement, the third active region 531 can still be used to further stabilize the structure in the second region to avoid collapse or damage of the structure. In addition, those skilled in the art to which the present invention pertains should be able to replace, reorganize, and mix features of several different embodiments to complete other embodiments without departing from the spirit of the present invention with reference to the aforementioned embodiments.

In the semiconductor device of the present invention, a structure that can strengthen the corners is arranged around the device, such as corners larger than 90 degrees, thickened sides, or extensions extending to the inside or outside, so that the device can be more stable around the device. , Reinforced structure to protect the components inside the device from collapse or damage to the structure. Thereby, the stress around the semiconductor device can be improved, and the collapse or damage of the semiconductor structure can be avoided.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (18)

1. A semiconductor device, characterized in that it comprises: a base; an active structure disposed in the substrate, the active structure includes a plurality of first active regions and a second active region, the plurality of the first active regions are parallel to each other, separated from each other and alternately Arranged along a first direction, the second active region is disposed outside the plurality of first active regions, wherein the second active region further includes a plurality of corners, and the corners of each of the corners are the angle is greater than 90 degrees; and a shallow trench isolation disposed in the substrate, the shallow trench isolation surrounding the active structure; The second active region surrounds a plurality of the first active regions, and the second active region further includes: at least one first side and at least one second side, the first side extends along a second direction, the second side extends along a third direction, and the third direction is perpendicular to the second direction; as well as at least one third side, the third side is disposed between the first side and the second side, and the third side extends along a fourth direction; The semiconductor device, wherein another part of the plurality of first active regions contacts the third side, and the number of the plurality of first active regions contacting the third side is at least five. 2 . The semiconductor device of claim 1 , wherein a portion of the plurality of first active regions contacts the first side or the second side, and a plurality of the first active regions contact the first side or the second side. 3 . The other part does not contact the first side or the second side, wherein the plurality of first active regions that contact the first side or the second side do not contact the first side Or a plurality of the first active regions on the second side are alternately arranged with each other. 3 . The semiconductor device of claim 1 , wherein the width of the third side is greater than the width of the first side or the second side. 4 . 4. The semiconductor device of claim 1, wherein the width of the third side is greater than twice the width of the first active region. 5 . The semiconductor device of claim 1 , wherein the second active region further comprises at least one extension portion disposed on the first side, the second side or the third side. 6 . . 6. The semiconductor device of claim 5, wherein the extension portion extends along the first direction. 7 . The semiconductor device of claim 6 , wherein the lengths of the extending portions in the first direction are not uniform. 8 . 8 . The semiconductor device of claim 1 , wherein the second active region further comprises at least one opening, and the opening is disposed on the first side or the second side. 9 . 9 . The semiconductor device of claim 1 , wherein the second active region further comprises a plurality of openings, and the plurality of openings are respectively disposed on the first side and the second side. 10 . 10. The semiconductor device of claim 9, wherein the openings have different sizes. 11. The semiconductor device of claim 1, wherein each of the corners has a different angle. 12. The semiconductor device of claim 1, wherein each of the corners is rounded. 13. The semiconductor device of claim 1, wherein the active structure further comprises a plurality of third active regions, the second active regions are disposed on the plurality of the third active regions and Between a plurality of the first active regions, a plurality of the third active regions are parallel to each other, separated from each other, and alternately arranged along the first direction. 14 . The semiconductor device of claim 13 , wherein a plurality of the third active regions and the second active regions are spaced apart from each other by a distance, and a part of the shallow trenches are disposed in the plurality of all the regions. 15 . between the third active region and the second active region. 15. The semiconductor device of claim 13, wherein a plurality of the third active regions are disposed adjacent to the outside of the second active regions. 16. A semiconductor device comprising: a base; an active structure disposed in the substrate, the active structure includes a plurality of first active regions, a second active region and a plurality of third active regions, a plurality of the first active regions and a plurality of the third active regions are parallel to each other, separated from each other and alternately arranged along a first direction, the second active regions are arranged in the plurality of the first active regions and the plurality of the first active regions between the three active regions and surrounding a plurality of the first active regions; and A shallow trench isolation is disposed in the substrate, and the shallow trench isolation surrounds the active structure. 17. The semiconductor device of claim 16, wherein the plurality of first active regions and the plurality of third active regions do not contact the second active region. 18 . The semiconductor device of claim 16 , wherein a plurality of the third active regions and the second active regions are spaced apart from each other by a distance, and a part of the shallow trenches are disposed in the plurality of all the between the third active region and the second active region.

Images