CN111953321A - A kind of delay circuit and delay method based on FPGA phase-locked loop - Google Patents

Abstract

The invention relates to the field of signal delay, in particular to a delay circuit and a delay method based on an FPGA phase-locked loop. The delay circuit includes a first delay unit and a second delay unit, the output end of the first delay unit is electrically connected with the input end of the second delay unit; the first delay unit is used to generate The delay signal is an integer multiple of the clock pulse period; the second delay unit is used for further delaying the delay signal output by the first delay unit to a delay signal smaller than the clock pulse period. The integer delay of the clock pulse period and the delay that is accurate to within the clock pulse period can improve the accuracy of the delay and are suitable for various high-precision trigger systems.

Description

A kind of delay circuit and delay method based on FPGA phase-locked loop

technical field

The invention relates to the field of signal delay, in particular to a delay circuit and a delay method based on an FPGA phase-locked loop.

Background technique

The multi-channel synchronous trigger device is widely used, which is mainly used in a series of scientific research work such as laser system, detonation physical parameter measurement, high-speed photography, medical equipment and so on. Taking the laser system as an example, in the laser system, it is usually necessary to control the multi-channel equipment to make it work synchronously, including synchronous triggering of the laser, optical system, detection equipment, etc. Accuracy delay adjustable trigger signal. Among them, the precision and jitter of the synchronization trigger time can affect the operational performance and efficiency of these devices.

The delay time precision of the existing delay circuit is low, which affects the synchronous work between devices.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, one of the purposes of the present invention is to provide a delay circuit, which can improve the accuracy of the delay.

To achieve the above object, the present invention has adopted the following technical solutions:

A delay circuit, the delay circuit comprises a first delay unit and a second delay unit, the output end of the first delay unit is electrically connected with the input end of the second delay unit;

The first delay unit is used to generate a delay signal that is an integer multiple of the clock pulse period; the second delay unit is used to further delay the delay signal output by the first delay unit by a delay smaller than the clock pulse period Signal.

Further, the first delay unit includes a first D flip-flop and a first counter, the clock terminal of the first D flip-flop is a signal input terminal, and the output terminal of the first D flip-flop is the same as the output terminal of the first counter. The reset terminal is electrically connected, and the output terminal of the first counter is electrically connected to the input terminal of the second delay unit;

The clock terminal of the first counter is electrically connected with the clock pulse generator.

Further, the second delay unit includes a second D flip-flop and a third D flip-flop, the output terminal of the first counter is electrically connected to the input terminal of the second D flip-flop, and the output terminal of the second D flip-flop is electrically connected to the input terminal of the second D flip-flop. The output terminal is electrically connected to the clock terminal of the third D flip-flop;

The clock terminal of the second D flip-flop is electrically connected with the clock pulse generator;

The output end of the third D flip-flop is used for outputting a delay signal.

Further, the delay circuit further includes a pulse width adjustment unit for adjusting the pulse width of the delay signal, the output end of the third D flip-flop is electrically connected with the input end of the pulse width adjustment unit, and the pulse width adjustment unit The output terminal of the D flip-flop is electrically connected to the reset terminal of the first D flip-flop and the reset terminal of the third D flip-flop.

Further preferably, the pulse width adjustment unit includes a fourth D flip-flop, a second counter and an inverter, the output end of the third D flip-flop is electrically connected to the input end of the fourth D flip-flop, and the first The output terminal of the four-D flip-flop is electrically connected to the reset terminal of the second counter, the output terminal of the second counter is electrically connected to the input terminal of the inverter, and the output terminal of the inverter is electrically connected to the output terminal of the first D flip-flop. The reset terminal, the reset terminal of the third D flip-flop, and the reset terminal of the fourth D flip-flop are electrically connected;

The clock terminal of the fourth D flip-flop and the clock terminal of the second counter are both electrically connected to the clock pulse generator.

Further preferably, the second D flip-flop is a monostable flip-flop.

The second purpose of the present invention is to provide a delay method based on an fpga phase-locked loop, comprising the following steps:

S1, the fpga inputs the signal trig_N to the delay circuit, and obtains the signal after the delay time T _D , and the time T _D is obtained after the clock pulse period T and the clock pulse phase-shifting in T;

S2, adjust the pulse width of the signal after the delay time TD in step S1 by fpga, and obtain the signal _{trig_N} +1 with the pulse width _TW .

Further, the specific steps of step S1 are as follows:

S11, the input end and the setting end of the first D flip-flop are all set to high level, and the phase-locked loop of the fpga inputs the number of counts _PD to the first counter;

S12, the fpga inputs the signal trig_N to the clock terminal of the first D flip-flop, the fpga simultaneously inputs the clock pulse clk_0 to the clock terminal of the first counter, and the fpga simultaneously inputs the clock pulse clk_1 to the clock terminal of the second D flip-flop, the clock pulses clk_0 and The clock period T of the clock pulse clk_1 is equal, and the clock pulse clk_1 is obtained by shifting the phase Q' of the clock pulse clk_0, and Q' is less than T;

The output end of the first D flip-flop outputs the same signal trig1 as the signal trig_N, and transmits the signal trig1 to the reset end of the first counter;

S13, the first counter starts to count, when the number of cycles of the clock pulse clk_0 obtained by the first counter reaches _PD , the output terminal of the first counter pulse signal trig2, the pulse width of the pulse signal trig2 is greater than the clock period T, and then the pulse signal trig2 is input to the input terminal of the second D flip-flop, and the output terminal of the second D flip-flop outputs the signal trig3 after the pulse signal trig2 is shifted by the phase Q', and the signal trig3 is the signal after the delay time TD of the signal _{trig_N} in step S1. :

T _D =P _D ×T+Q′

N is the total number of phase shifts of the clock cycle T, and Q _D is the number of phase shifts of the clock pulse clk_1 relative to the clock pulse clk_0.

Further, the specific steps of step S2 are as follows:

S21, both the input terminal and the set terminal of the third D flip-flop are set to a high level, and the clock pulse clk_2 is input to the clock terminal of the fourth D flip-flop and the clock terminal of the second counter through the fpga, and the clock pulse clk_2 is The clock pulse clk_0 is obtained by moving the phase Q", Q" is greater than Q', and Q" is less than T; and the number of counts P _W is input to the second counter through the phase-locked loop of the fpga;

S22, input the signal trig3 to the clock terminal of the third D flip-flop, and through the output terminal of the third D flip-flop, the input terminal of the fourth flip-flop and the clock pulse clk_2, the output terminal of the fourth flip-flop outputs the signal trig3 phase-shifted Signal trig4 after Q", and input the signal trig4 to the reset terminal of the second counter;

S23, the second counter starts counting, and when the number of cycles of the clock pulse clk_2 obtained by the second counter reaches P _W , the output end of the second counter outputs a pulse signal trig5;

S24, the pulse signal trig5 passes through the inverter to reset the first D flip-flop, the third D flip-flop, and the fourth D flip-flop, and then the output terminal of the fourth D flip-flop outputs the signal trig_N after the delay time T _D and the pulse width is Signal trig_N+1 of _{TW, TW =P W × T} +Q″

Q _W is the phase shift amount of the clock pulse clk_2 relative to the clock pulse clk_0.

Further preferably, the value of T is 3ns˜5ns.

The beneficial effects of the present invention are as follows:

(1) The present invention includes two delay units, which respectively carry out the delay of an integer multiple of the clock pulse period and the delay accurate to the clock pulse period, which can improve the accuracy of the delay, and is suitable for various high-precision trigger systems. .

(2) The present invention designs a simple high-precision adjustable delay generation circuit based on FPGA phase-locked loop multi-output phase shifting, and adopts the principle of fpga main frequency counting combined with phase-locked loop multi-output phase shifting, without adding special The chip can easily realize sub-high precision adjustable delay, which is suitable for various high-precision synchronous triggering application requirements.

(3) The present invention only needs the second flip-flop to output a rising edge to trigger the third flip-flop to output a high level, so the second flip-flop of the present invention is set as a monostable flip-flop, which can automatically recover to low level, without the need to set an additional reset circuit to reset it to a low level, which simplifies the delay circuit.

(4) The present invention can adjust the precision of the signal after the delay and the pulse width of the signal after the delay according to actual needs by adjusting the total number N of phase shifts of the clock period T, so that the pulse width of the signal after the delay can be adjusted, which is convenient and fast .

Description of drawings

1 is a circuit diagram of the present invention;

FIG. 2 is a schematic diagram of timing signals of the present invention.

The meanings of the symbols in the figure are as follows:

1-First delay unit 2-Second delay unit 3-Pulse width adjustment unit

C1-first counter C2-second counter

D1～D4-first D flip-flop～fourth D flip-flop 31-inverter

Detailed ways

The technical solutions in the present invention will be clearly and completely described below with reference to the embodiments and the accompanying drawings. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Example 1

A delay circuit, as shown in Figure 1, the delay circuit includes a first delay unit 1, a second delay unit 2 and a pulse width adjustment unit 3, the output end of the first delay unit 1 and the second delay unit The input terminal of the unit 2 is electrically connected, the output terminal of the second delay unit 2 is electrically connected to the input terminal of the pulse width adjustment unit 3, and the output terminal of the pulse width adjustment unit 3 is electrically connected to the reset terminal of the first delay unit 1 and the second The reset terminal of the delay unit 2 is electrically connected.

As shown in FIG. 1 , the first delay unit 1 includes a first D flip-flop D1 and a first counter C1. The clock terminal of the first D flip-flop D1 is a signal input terminal, and the output terminal of the first D flip-flop D1 is connected to the first D flip-flop D1. A reset terminal of a counter C1 is electrically connected. The input terminal of the first D flip-flop D1 is used to connect the signal trig_N to be delayed, and the clock terminal of the first counter C1 is connected to the clock pulse clk_0.

The second delay unit 2 includes a second D flip-flop D2 and a third D flip-flop D3. The output terminal of the first counter C1 is electrically connected to the input terminal of the second D flip-flop D2, and the output terminal of the second D flip-flop D2 is electrically connected. It is electrically connected to the clock terminal of the third D flip-flop D3. The clock terminal of the second D flip-flop D2 is connected to the clock pulse clk_1, the output terminal of the second D flip-flop D2 is used to output the delay signal trig_N+1, and the second D flip-flop D2 is a monostable flip-flop.

The pulse width adjusting unit 3 includes a fourth D flip-flop D4, a second counter C2 and an inverter 31. The output terminal of the third D flip-flop D3 is electrically connected to the input terminal of the fourth D flip-flop D4. The output terminal of D4 is electrically connected to the reset terminal of the second counter C2, the output terminal of the second counter C2 is electrically connected to the input terminal of the inverter 31, and the output terminal of the inverter 31 is electrically connected to the reset terminal of the first D flip-flop D1. , the reset terminal of the third D flip-flop D3 and the reset terminal of the fourth D flip-flop D4 are electrically connected.

The clock terminal of the fourth D flip-flop D4 and the clock terminal of the second counter C2 are both connected to the clock pulse clk_2.

The delay circuit of this embodiment is implemented through the first D flip-flop D1, the second D flip-flop D2, the third D flip-flop D3, the fourth D flip-flop D4, the first counter C1, the second counter C2, The inverter 31, the clock pulse clk_0, the clock pulse clk_1, and the clock pulse clk_2 are formed, and the fpga is the EP4CGX110 chip of the Cyclone IV GX series of ALTERA Company.

Example 2

On the basis of Embodiment 1, a time delay method based on an fpga phase-locked loop, comprising the following steps:

S1, the fpga inputs the signal _{trig_N} to the delay circuit, and obtains the signal after the delay time TD, which is obtained after the clock pulse period _T and the clock pulse phase shift within T. Specific steps are as follows:

S11, the input end and the setting end of the first D flip-flop D1 are all set to high level (that is, the potential is 1), and the phase-locked loop of the fpga inputs the number of counts _PD to the first counter C1;

S12, the fpga inputs the signal trig_N to the clock terminal (clk terminal) of the first D flip-flop D1, the fpga simultaneously inputs the clock pulse clk_0 to the clock terminal (clk terminal) of the first counter C1, and the fpga simultaneously transmits the clock pulse clk_0 to the second D flip-flop D2 The clock terminal (clk terminal) inputs the clock pulse clk_1, the clock period T of the clock pulse clk_0 and the clock pulse clk_1 is equal, the clock pulse clk_1 is obtained by the clock pulse clk_0 moving the phase Q', and Q' is less than T;

The output terminal (q terminal) of the first D flip-flop D1 outputs the same signal trig1 as the signal trig_N, and transmits the signal trig1 to the reset terminal (rst_n terminal) of the first counter C1. As shown in FIG. 2 , when the first D flip-flop D1 receives the rising edge of the signal trig_N, the output terminal (q terminal) of the first D flip-flop D1 outputs the same edge change as the signal trig_N, and the first D flip-flop D1 The output terminal (q terminal) of is connected to the reset terminal (rst_n terminal) of the first counter C1. When the reset terminal (rst_n terminal) of the first counter C1 is at a low level (ie, the potential is 0), it is in a reset state, as shown in Figure 2, when there is a rising edge, the reset terminal (rst_n terminal) of the first counter C1 It is high level (that is, the potential is 1), that is, it starts to count, and the number of counts is the number of counts P _D required for the delay T _D

S13, the first counter C1 starts counting, and when the clock terminal (clk terminal) of the first counter C1 obtains the number of cycles of the clock pulse clk_0 reaches _PD , the output terminal (q-tc terminal) of the first counter C1 outputs a pulse signal trig2, the pulse width of the pulse signal trig2 is greater than the clock period T, that is, the rising edge of clk_1 will definitely be in the high level of the output pulse of the first counter C1 (that is, the potential is 1), so that the D flip-flop 2 constitutes a In this way, a pulse signal trig2 is output at the first rising edge of clk_1 among the high level (ie, the potential is 1) of the output pulse of the first counter C1. Then input the pulse signal trig2 to the input terminal (D terminal) of the second D flip-flop D2, and the output terminal (q terminal) of the second D flip-flop D2 outputs the signal trig3 after the pulse signal trig2 moves the phase Q', and the signal trig3 is the step Signal _{trig_N} in step S1 after delay time TD:

T _D =P _D ×T+Q′

N is the total number of phase shifts of the clock cycle T, and Q _D is the number of phase shifts of the clock pulse clk_1 relative to the clock pulse clk_0. For example: the clock cycle T (assume 5ns) is divided into N (assume 5) parts, if the value of Q _D is 1, the value of Q' is 1ns; if the value of Q' is 2ns

S2, adjust the pulse width of the signal after the delay time TD in step S1 by fpga, and obtain the signal _{trig_N} +1 with the pulse width _TW . Specific steps are as follows:

S21, both the input terminal and the set terminal of the third D flip-flop D3 are set to a high level (that is, the potential is 1), and the clock terminal (clk terminal) of the fourth D flip-flop D4 and the second counter are sent to the clock terminal (clk terminal) of the fourth D flip-flop D4 through fpga. The clock terminal (clk terminal) of C2 inputs the clock pulse clk_2, the clock pulse clk_2 is obtained by the clock pulse clk_0 moving the phase Q", Q" is greater than Q', and Q" is less than T; Input count times P _W ;

S22, input the signal trig3 to the clock terminal (clk terminal) of the third D flip-flop D3, through the output terminal (q terminal) of the third D flip-flop D3 and the input terminal (D terminal) of the fourth flip-flop D4 and the clock Pulse clk_2, the output terminal (q) of the fourth flip-flop D4 outputs the signal trig4 after the signal trig3 is phase-shifted by Q", and inputs the signal trig4 to the reset terminal (rst_n terminal) of the second counter C2;

S23, as shown in FIG. 2, when the output terminal (q) of the fourth flip-flop D4 outputs a high level (potential is 1), the second counter C2 starts counting, and when the second counter C2 obtains the period of the clock pulse clk_2 When the number reaches P _W , the output terminal of the second counter C2 outputs a pulse signal trig5, that is, a high level (potential is 1);

S24, the pulse signal trig5 changes to a low level through the inverter 31 (that is, the potential is 0), and the low level resets the first D flip-flop D1, the third D flip-flop D3, and the fourth D flip-flop D4, and then the first D flip-flop D1, the third D flip-flop D3, and the fourth D flip-flop D4 are reset. The output terminal of the four-D flip-flop D4 outputs the signal trig_N after the delay time T _D , the signal trig_N+1 with the pulse width of T _W , T _W =P _W ×T+Q″

Q _W is the phase shift amount of the clock pulse clk_2 relative to the clock pulse clk_0.

The value of T is 3ns˜5ns, and in this embodiment, the value of T is 4ns.

The circuit required by the delay method of this embodiment is simple and the cost is reduced. The control is simple, and the FPGA can be built inside. The sub-ns-level high-precision adjustable delay can be simply realized without adding a special chip, which is suitable for various high-precision synchronous triggering applications. The achievable adjustment step accuracy is ≤1ns, and the error range is ≤±0.5ns.

Claims (10)

1. A delay circuit, characterized in that: the delay circuit comprises a first delay unit (1) and a second delay unit (2), and the output end of the first delay unit (1) is The input end of the second delay unit (2) is electrically connected; The first delay unit (1) is used for generating a delay signal that is an integer multiple of the clock pulse period; the second delay unit (2) is used for reproducing the delay signal output by the first delay unit (1). Delayed signal with a delay less than the period of the clock pulse. 2. The delay circuit according to claim 1, characterized in that: the first delay unit (1) comprises a first D flip-flop (D1) and a first counter (C1), the first D flip-flop The clock terminal of the device (D1) is a signal input terminal, the output terminal of the first D flip-flop (D1) is electrically connected to the reset terminal of the first counter (C1), and the output terminal of the first counter (C1) is electrically connected to the reset terminal of the first counter (C1). The input end of the second delay unit (2) is electrically connected; The clock terminal of the first counter (C1) is electrically connected with the clock pulse generator. 3. The delay circuit according to claim 2, characterized in that: the second delay unit (2) comprises a second D flip-flop (D2) and a third D flip-flop (D3), the first The output terminal of the counter (C1) is electrically connected to the input terminal of the second D flip-flop (D2), and the output terminal of the second D flip-flop (D2) is electrically connected to the clock terminal of the third D flip-flop (D3); The clock terminal of the second D flip-flop (D2) is electrically connected to the clock pulse generator; The output end of the third D flip-flop (D3) is used for outputting a delay signal. 4. The delay circuit according to claim 3, characterized in that: the delay circuit further comprises a pulse width adjustment unit (3) for adjusting the pulse width of the delay signal, the third D flip-flop (D3) ) is electrically connected to the input end of the pulse width adjustment unit (3), and the output end of the pulse width adjustment unit (3) is connected to the reset end of the first D flip-flop (D1), the third D flip-flop (D3) ) is electrically connected to the reset terminal. 5. The delay circuit according to claim 4, characterized in that: the pulse width adjustment unit (3) comprises a fourth D flip-flop (D4), a second counter (C2) and an inverter (31), The output terminal of the third D flip-flop (D3) is electrically connected to the input terminal of the fourth D flip-flop (D4), and the output terminal of the fourth D flip-flop (D4) is connected to the reset of the second counter (C2). The output terminal of the second counter (C2) is electrically connected to the input terminal of the inverter (31), and the output terminal of the inverter (31) is electrically connected to the reset terminal of the first D flip-flop (D1). terminal, the reset terminal of the third D flip-flop (D3), and the reset terminal of the fourth D flip-flop (D4) are electrically connected; The clock terminal of the fourth D flip-flop (D4) and the clock terminal of the second counter (C2) are both electrically connected to the clock pulse generator. 6. The delay circuit according to claim 3, 4 or 5, wherein the second D flip-flop (D2) is a monostable flip-flop. 7. the delay method based on fpga phase-locked loop of the delay circuit as claimed in claim 1, is characterized in that, comprises the steps: S1, the fpga inputs the signal trig_N to the delay circuit, and obtains the signal after the delay time T _D , and the time T _D is obtained after the clock pulse period T and the clock pulse phase-shifting in T; S2, adjust the pulse width of the signal after the delay time TD in step S1 by fpga, and obtain the signal _{trig_N} +1 with the pulse width _TW . 8. the time delay method based on fpga phase-locked loop as claimed in claim 7 is characterized in that, the concrete steps of step S1 are as follows: S11, the input end and the setting end of the first D flip-flop (D1) are all set to high level, and the phase-locked loop of the fpga inputs the number of counts _PD to the first counter (C1); S12, the fpga inputs the signal trig_N to the clock terminal of the first D flip-flop (D1), the fpga simultaneously inputs the clock pulse clk_0 to the clock terminal of the first counter (C1), and the fpga simultaneously supplies the clock terminal of the second D flip-flop (D2) Input the clock pulse clk_1, the clock period T of the clock pulse clk_0 and the clock pulse clk_1 are equal, the clock pulse clk_1 is obtained by shifting the phase Q' of the clock pulse clk_0, and Q' is less than T; The output terminal of the first D flip-flop (D1) outputs the same signal trig1 as the signal trig_N, and transmits the signal trig1 to the reset terminal of the first counter (C1); S13, the first counter (C1) starts counting, and when the first counter (C1) obtains that the number of cycles of the clock pulse clk_0 reaches _PD , the output end of the first counter (C1) outputs a pulse signal trig2, the pulse of the pulse signal trig2 The width is greater than the clock period T; then the pulse signal trig2 is input to the input terminal of the second D flip-flop (D2), and the output terminal of the second D flip-flop (D2) outputs the signal trig3 after the pulse signal trig2 moves the phase Q', the signal trig3 That is, the signal after the delay time TD of the signal _{trig_N} in step S1: T _D =P _D ×T+Q′

N is the total number of phase shifts of the clock cycle T, and Q _D is the number of phase shifts of the clock pulse clk_1 relative to the clock pulse clk_0. 9. the time delay method based on fpga phase-locked loop as claimed in claim 8, is characterized in that, the concrete steps of step S2 are as follows: S21, both the input terminal and the set terminal of the third D flip-flop (D3) are set to a high level, and the clock terminal of the fourth D flip-flop (D4) and the clock terminal of the second counter (C2) are sent to the clock terminal of the fourth D flip-flop (D4) through fpga. Input clock pulse clk_2, clock pulse clk_2 is obtained by clock pulse clk_0 moving phase Q ", Q " is greater than Q ', Q " is less than T; And input count times P _W to the second counter (C2) through the phase-locked loop of fpga; S22, input the signal trig3 to the clock terminal of the third D flip-flop (D3), through the output terminal of the third D flip-flop (D3) and the input terminal of the fourth flip-flop (D4) and the clock pulse clk_2, the fourth trigger The output terminal of the device (D4) outputs the signal trig4 after the phase shift of the signal trig3 by Q", and inputs the signal trig4 to the reset terminal of the second counter (C2); S23, the second counter (C2) starts counting, and when the second counter (C2) obtains that the number of cycles of the clock pulse clk_2 reaches P _W , the output end of the second counter (C2) outputs the pulse signal trig5; S24, the pulse signal trig5 passes through the inverter (31) to reset the first D flip-flop (D1), the third D flip-flop (D3), and the fourth D flip-flop (D4), and then the fourth D flip-flop (D4) The output terminal outputs the signal _{trig_N} after the delay time TD, the signal trig_N+1 with the pulse width of _{TW, TW =P W × T} +Q″

Q _W is the phase shift amount of the clock pulse clk_2 relative to the clock pulse clk_0. 10 . The time delay method based on an FPGA phase-locked loop according to claim 7 , wherein the value of T is 3ns˜5ns. 11 .

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