[go: up one dir, main page]

CN111952357B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

Info

Publication number
CN111952357B
CN111952357B CN201910407216.2A CN201910407216A CN111952357B CN 111952357 B CN111952357 B CN 111952357B CN 201910407216 A CN201910407216 A CN 201910407216A CN 111952357 B CN111952357 B CN 111952357B
Authority
CN
China
Prior art keywords
dielectric layer
layer
forming
semiconductor device
gate structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910407216.2A
Other languages
Chinese (zh)
Other versions
CN111952357A (en
Inventor
王楠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201910407216.2A priority Critical patent/CN111952357B/en
Publication of CN111952357A publication Critical patent/CN111952357A/en
Application granted granted Critical
Publication of CN111952357B publication Critical patent/CN111952357B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6215—Fin field-effect transistors [FinFET] having multiple independently-addressable gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供一种半导体器件及其形成方法，包括：提供衬底，衬底上形成有若干分立排布鳍部；在衬底上形成横跨所述鳍部的伪栅结构；在伪栅结构上形成至少一个分立排布的硬掩膜层；在硬掩膜层的侧壁上形成牺牲侧墙；在相邻的牺牲侧墙之间形成牺牲层；去除牺牲侧墙以及牺牲侧墙覆盖的伪栅结构，形成开口；在开口内填充满介质层，介质层的顶部与硬掩膜层的顶部齐平；这种形成方法将形成的介质层作为伪栅结构的侧墙，不会在鳍部上形成有介质层，保证了形成的鳍部的表面质量，从而使得形成的半导体器件的性能波动小，良率得到提高，在形成源漏时，能够形成形貌质量好的外延层，保证形成的半导体器件的使用性能的稳定性。

The present invention provides a semiconductor device and a method for forming the same, comprising: providing a substrate, on which a plurality of discretely arranged fins are formed; forming a pseudo gate structure across the fins on the substrate; forming at least one discretely arranged hard mask layer on the pseudo gate structure; forming a sacrificial sidewall on the sidewall of the hard mask layer; forming a sacrificial layer between adjacent sacrificial sidewalls; removing the sacrificial sidewall and the pseudo gate structure covered by the sacrificial sidewall to form an opening; filling the opening with a dielectric layer, wherein the top of the dielectric layer is flush with the top of the hard mask layer; in this forming method, the formed dielectric layer is used as the sidewall of the pseudo gate structure, and no dielectric layer is formed on the fin, thereby ensuring the surface quality of the formed fin, so that the performance fluctuation of the formed semiconductor device is small and the yield is improved. When forming a source and a drain, an epitaxial layer with good morphology quality can be formed, thereby ensuring the stability of the use performance of the formed semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. The device is used as the most basic semiconductor device, is widely applied at present, the control capability of the traditional planar device on channel current is weakened, short channel effect is generated to cause leakage current, and the electrical property of the semiconductor device is finally affected.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin field effect transistor includes: the isolation structure covers part of the side wall of the fin part and is positioned on the substrate and spans the gate structure; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as semiconductor devices shrink in size, device density increases, resulting fin field effect transistors do not perform as stably.
Disclosure of Invention
The invention solves the problem of providing a semiconductor device and a forming method thereof, so that the performance of the formed semiconductor device is stable.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate, wherein a plurality of discrete arrangement fin parts are formed on the substrate; forming a pseudo gate structure crossing the fin part on the substrate; forming at least one hard mask layer which is arranged separately on the pseudo gate structure; forming a sacrificial side wall on the side wall of the hard mask layer; forming a sacrificial layer between the adjacent sacrificial side walls; removing the sacrificial side wall and the pseudo gate structure covered by the sacrificial side wall to form an opening; and filling a dielectric layer in the opening, wherein the top of the dielectric layer is flush with the top of the hard mask layer.
Optionally, the dielectric layer includes a single layer structure or a stacked layer structure.
Optionally, when the dielectric layer is in a single-layer structure, the material of the dielectric layer includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
Optionally, when the dielectric layer is in a laminated structure, the dielectric layer includes a first dielectric layer and a second dielectric layer, and the second dielectric layer is located on the first dielectric layer.
Optionally, the material of the first dielectric layer is different from the material of the second dielectric layer.
Optionally, the material of the first dielectric layer includes one or more of silicon oxynitride or silicon oxycarbonitride.
Optionally, the material of the second dielectric layer is silicon nitride.
Optionally, the material of the hard mask layer includes one or more of silicon nitride or silicon oxide or silicon carbide or silicon oxycarbide.
Optionally, the material of the sacrificial sidewall includes one or more of silicon oxide, silicon nitride or silicon carbide.
Optionally, after filling the dielectric layer in the opening, the top of the dielectric layer is flush with the top of the hard mask layer, and then the sacrificial layer and the dummy gate structure covered by the sacrificial layer are removed.
A semiconductor device formed by the above method includes a substrate; the fin parts are separately positioned on the substrate; a dummy gate structure located on the substrate across the fin; the hard mask layers are separately positioned on the pseudo gate structure; openings located between adjacent hard mask layers and between adjacent dummy gate structures under the hard mask layers; the dielectric layer is positioned in the opening, and the top of the dielectric layer is flush with the top of the hard mask layer; and the sacrificial layer is positioned between the adjacent dielectric layers and is positioned on the dummy gate structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the method comprises the steps of forming a plurality of hard mask layers which are arranged separately on a pseudo gate structure, forming a sacrificial side wall on the side wall of the hard mask layer, removing the sacrificial side wall and the pseudo gate structure covered by the bottom of the sacrificial side wall, forming an opening in the pseudo gate structure, filling a dielectric layer in the opening, wherein the formed dielectric layer is used as the side wall of the pseudo gate structure, and the dielectric layer is not formed on a fin part because the dielectric layer is only filled in the opening and is used as the side wall of the pseudo gate structure, so that the surface quality of the formed fin part is ensured, the performance fluctuation of a formed semiconductor device is small, the yield is improved, an epitaxial layer with good appearance quality can be formed when a source drain is formed, and the stability of the service performance of the formed semiconductor device is ensured.
Drawings
Fig. 1 to 5 are schematic structural views of a semiconductor device forming process in one embodiment;
Fig. 6 to 14 are schematic structural views of a semiconductor device forming process in the first embodiment of the present invention;
Fig. 15 to 16 are schematic structural views of a semiconductor device forming process in the second embodiment of the present invention.
Detailed Description
The method for forming the side wall on the side wall of the pseudo gate structure is generally adopted, namely, a side wall material layer is formed on the substrate, the fin part and the pseudo gate structure, the side wall material layer is etched back until the top surface of the fin part is exposed, and the side wall covering the side wall of the pseudo gate structure is formed on the fin part, but at the moment, part of side wall material is remained on the side wall of the fin part, so that the fluctuation of the performance of the formed semiconductor device is large, the yield of the semiconductor device is influenced, and meanwhile, when a source and a drain are formed, the growth morphology of an epitaxial layer is strange, and the performance of the semiconductor device is influenced.
The specific semiconductor device is formed as follows:
Referring to fig. 1, a substrate 1 is provided, and a fin 2 is formed on the substrate 1.
Referring to fig. 2 to 3, a dummy gate structure 3 is formed on the substrate 1 across the fin 2.
Fig. 3 is a cross-sectional view of fig. 2 along section line A-A.
Referring to fig. 4, a sidewall material 4 is formed on the substrate 1, the fin 2, and the dummy gate structure 3.
Referring to fig. 5, the sidewall material 4 is etched back, and a sidewall 401 is formed on the sidewall of the dummy gate structure 3.
The inventor finds that after the side wall material is formed on the substrate, the fin part and the pseudo gate structure, the side wall material is etched back, a side wall is formed on the side wall of the pseudo gate structure, and part of the side wall material is also formed on the side wall of the fin part, so that the performance fluctuation of the formed semiconductor device is too large, and meanwhile, part of the side wall material is remained on the fin part, so that when source and drain are formed later, the epitaxial layer formed by epitaxial layer growth is abnormal in morphology, and the yield and performance of the formed semiconductor device are affected.
The inventor researches and discovers that a hard mask layer which is arranged separately is formed on a pseudo gate structure, a sacrificial side wall is formed on the side wall of the hard mask layer, and a sacrificial layer is formed between the adjacent sacrificial side walls; removing the sacrificial side wall and the dummy gate structure covered by the bottom of the sacrificial side wall to form an opening; filling the opening with a dielectric layer, wherein the top of the dielectric layer is flush with the top of the hard mask layer; the formed dielectric layer is used as the side wall of the pseudo gate structure, and the dielectric layer material is not deposited first, so that the dielectric layer material is not left on the fin part, the surface quality of the formed fin part is ensured, the performance of the formed semiconductor device is stable, the yield is improved, and meanwhile, when the source and the drain are formed, an epitaxial layer with good appearance can be formed, and the service performance of the formed semiconductor device is improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
First embodiment
Fig. 6 to 14 are schematic structural views of a semiconductor device forming process in the first embodiment of the present invention.
Referring first to fig. 6, a substrate 200 is provided, the substrate 200 having a plurality of discrete arrangement fins 300 formed thereon.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; in other embodiments, the substrate 200 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like.
In this embodiment, the step of forming the fin 300 includes: forming a fin material film on the substrate 200, and forming a patterned layer on the fin material film; and etching the fin material film by taking the patterned layer as a mask to form the fin 300.
In this embodiment, the fin 300 is made of monocrystalline silicon or monocrystalline germanium silicon.
Referring to fig. 7-8, a dummy gate structure 400 is formed on the substrate 200 across the fin 300.
Fig. 8 is a cross-sectional view taken along line A-A of fig. 7.
In this embodiment, the material of the dummy gate structure 400 is polysilicon; in other embodiments, the material of the dummy gate structure 400 may also be amorphous carbon or silicon nitride.
The method of forming the dummy gate structure 400 includes: forming a gate oxide layer (not shown in the figure) on the surfaces of the substrate 200 and the fin 300, forming a gate layer on the gate oxide layer, and forming a patterned layer on the gate layer, wherein the patterned layer covers a corresponding region where the dummy gate structure 400 needs to be formed; and etching the gate layer and the gate oxide layer by taking the patterned layer as a mask until the substrate 200 is exposed, wherein the formed dummy gate structure 400 spans across the fin 300.
Referring to fig. 9, at least one hard mask layer 500 is formed on the dummy gate structure 400 in a discrete arrangement.
In this embodiment, the material of the hard mask layer 500 is silicon oxide; in other embodiments, the hard mask layer 500 may also be one or more of silicon nitride or silicon carbide or silicon oxycarbide.
In this embodiment, the step of forming the hard mask layer 500 includes: including first forming the material of the mask layer 500 on top of the dummy gate structure 400, and then etching back the material of the mask layer 500 using a self-aligned double patterning process (SADP), thereby forming at least one hard mask layer 500 in a discrete arrangement on the dummy gate structure 400.
In other embodiments, at least one hard mask layer 500 may be formed separately on the dummy gate structure 400 without etching back the mask layer 500 material using a self-aligned double patterning process (SADP).
In this embodiment, the material of the hard mask layer 500 is formed on top of the dummy gate structure 400 by using an atomic layer deposition method; in other embodiments, the material of the hard mask layer 500 may be formed on top of the dummy gate structure 400 by chemical vapor deposition or physical vapor deposition.
In this embodiment, the reason for forming the hard mask layer 500 by using the atomic layer deposition method is that the atomic layer deposition method can form the hard mask layer 500 with higher density, so as to improve the protection effect of the hard mask layer 500 on the dummy gate structure 400 in the subsequent process, and ensure the performance of the formed semiconductor device.
Referring to fig. 10, sacrificial sidewall 501 is formed on the sidewall of the hard mask layer 500.
In this embodiment, by forming the sacrificial sidewall 501 on the sidewall of the hard mask layer 500, the position of forming the sidewall on the sidewall of the dummy gate structure 400 is predefined, so that it is not necessary to deposit the sidewall material first and then etch back the sidewall material.
In this embodiment, the material of the sacrificial sidewall 501 is silicon carbide; in other embodiments, the material of the sacrificial sidewall 501 may further include one or more of silicon oxide or silicon nitride.
Referring to fig. 11, a sacrificial layer 502 is formed between adjacent sacrificial side walls 501.
In this embodiment, the material of the sacrificial layer 502 is silicon nitride; in other embodiments, the material of the sacrificial layer 502 may also be silicon carbide, silicon oxide, or the like.
In this embodiment, the purpose of forming the sacrificial layer 502 protects the dummy gate structure 400 covered by the sacrificial layer 502, so as to ensure that the covered dummy gate structure 400 is not removed simultaneously in the process of removing the sacrificial sidewall 501.
Referring to fig. 12, the sacrificial sidewall 501 and the dummy gate structure 400 at the bottom of the sacrificial sidewall 501 are removed to form an opening 401.
In this embodiment, the sacrificial sidewall 501 and the dummy gate structure 400 at the bottom of the sacrificial sidewall 501 are removed by dry etching, so as to form the opening 401.
In this embodiment, the process parameters for removing the sacrificial sidewall 501 include: and removing the sacrificial side wall 501 by adopting anisotropic dry etching, wherein the technological parameters of the dry etching are as follows: fluorine-containing gas (such as CH 3F、CH2F2 or CHF 3), argon and oxygen are adopted, the etching power is 200W-400W, the pressure of an etching cavity is 30-200 mtorr, and the etching temperature is 40-60 ℃.
In other embodiments, a wet etching process or an ashing process may be used to remove the sacrificial sidewall 501.
In this embodiment, the purpose of removing the dummy gate structure 400 at the bottom of the sacrificial sidewall 501 by dry etching is to ensure the quality of the remaining dummy gate structure; meanwhile, a relatively high etching solution is required to be selected for etching, so that less damage is caused to the gate oxide layer at the bottom of the pseudo gate structure.
In this embodiment, HBr gas is used as etching gas; in other embodiments, SF6 gas may also be used as the etching gas.
Referring to fig. 13, the opening 401 is filled with a dielectric layer 600, and the top of the dielectric layer 600 is flush with the top of the hard mask layer 500.
In this embodiment, the dielectric layer 600 has a single-layer structure; in other embodiments, the dielectric layer 600 may also have a stacked structure.
In this embodiment, the material of the dielectric layer 600 is silicon nitride; in other embodiments, the material of the dielectric layer 600 may be one of silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
In this embodiment, the dielectric layer 600 is filled in the opening 401, and the dielectric layer 600 is used as a sidewall of the dummy gate structure 400, so that when the sidewall of the dummy gate structure 400 is formed, the material of the sidewall is not remained on the fin portion 300, the surface quality of the fin portion 300 is ensured, the performance stability of the formed semiconductor device is enhanced, and the yield of the semiconductor device is improved; meanwhile, as the surface quality of the fin part 300 is good, an epitaxial layer with good appearance can be formed when source and drain are formed later, and the quality of a formed semiconductor device can be guaranteed.
A semiconductor device formed by the above method, comprising, a substrate 200; a plurality of fins 300, separately located on the substrate 200; a dummy gate structure 400 located on the substrate 200 across the fin 300; a plurality of hard mask layers 500 separately located on the dummy gate structure 400; openings 401 between adjacent ones of the hard mask layers 500 and between adjacent ones of the dummy gate structures 400 under the hard mask layers 500; a dielectric layer 600 located within the opening 401 with the top level with the top of the hard mask layer 500; and a sacrificial layer 502 located between adjacent dielectric layers 600 and on the dummy gate structure 400.
Referring to fig. 14, the sacrificial layer 502 and the dummy gate structure 400 covered by the sacrificial layer 502 are removed.
In this embodiment, an isotropic wet etching process is used to remove the sacrificial layer 502, where parameters of the wet etching process include: an aqueous solution of HNO 3 and HF, wherein the volume ratio of HNO3, HF and H2O is 1:3: (10 to 800) and the temperature is 40 to 90 ℃.
In this embodiment, after the sacrificial layer 502 is removed, a wet etching process is used to remove the dummy gate structure 400 covered by the sacrificial layer 502, where tetramethylammonium hydroxide (TMAH) is used as an etching solution in the wet etching process.
Second embodiment
The present embodiment differs from the first embodiment only in the structure of the dielectric layer.
In this embodiment, the dielectric layer adopts a stacked structure.
Fig. 15 to 16 are schematic structural views of a semiconductor device forming process in the second embodiment of the present invention.
Referring to fig. 15, the opening 401 is filled with a first dielectric layer 700, and the top of the first dielectric layer 700 is level with the top of the dummy gate structure 400.
In this embodiment, the top of the first dielectric layer 700 is flush with the top of the dummy gate structure 400; in other embodiments, the top of the first dielectric layer 700 may also be lower than the top of the dummy gate structure 400.
In this embodiment, the material of the first dielectric layer 700 is a material with a low dielectric constant, such as silicon oxynitride; in other embodiments, the material of the first dielectric layer 700 may be silicon oxynitride.
In this embodiment, the first dielectric layer 700 uses a material with a low dielectric constant as a part of the sidewall material, so that parasitic capacitance between the gate structure and the conductive plug can be reduced, thereby improving ac characteristics of the semiconductor device.
Referring to fig. 16, a second dielectric layer 800 is formed on the first dielectric layer 700, and the top of the second dielectric layer 800 is flush with the top of the hard mask 500.
In this embodiment, the second dielectric layer 800 uses pure silicon nitride as a part of the sidewall material, and since the pure silicon nitride has a slower etching rate, the second dielectric layer 800 is not easily etched when the conductive plug is formed later, so that the gate structure is better separated from the conductive plug, and the distance between the gate structure and the conductive plug is ensured.
A semiconductor device formed by the above method includes a substrate 200; the fin parts 300 are separately positioned on the substrate 200, and the pseudo gate structure 400 is positioned on the substrate 200 and spans across the fin parts 300; a plurality of hard mask layers 500 separately located on the dummy gate structure 400; openings 401 between adjacent ones of the hard mask layers 500 and between adjacent ones of the dummy gate structures 400 under the hard mask layers 500; a first dielectric layer 700 located within the opening 401; a second dielectric layer 800 located on the first dielectric layer 700; and a sacrificial layer 502, which is located between the adjacent second dielectric layers 800 and is located on the dummy gate structure 400.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (11)

1.一种半导体器件的形成方法，其特征在于，包括：1. A method for forming a semiconductor device, comprising: 提供衬底，所述衬底上形成有若干分立排布鳍部；Providing a substrate, on which a plurality of discretely arranged fins are formed; 在所述衬底上形成横跨所述鳍部的伪栅结构；forming a dummy gate structure across the fin on the substrate; 在所述伪栅结构上形成至少一个分立排布的硬掩膜层；forming at least one discretely arranged hard mask layer on the dummy gate structure; 在所述硬掩膜层的侧壁上形成牺牲侧墙；forming a sacrificial spacer on the sidewall of the hard mask layer; 在相邻的所述牺牲侧墙之间形成牺牲层；forming a sacrificial layer between adjacent sacrificial sidewalls; 去除所述牺牲侧墙以及所述牺牲侧墙覆盖的所述伪栅结构，形成开口；removing the sacrificial spacer and the dummy gate structure covered by the sacrificial spacer to form an opening; 在所述开口内填充满介质层，所述介质层的顶部与所述硬掩膜层的顶部齐平。The opening is filled with a dielectric layer, and the top of the dielectric layer is flush with the top of the hard mask layer. 2.如权利要求1所述半导体器件的形成方法，其特征在于，所述介质层包括单层结构或叠层结构。2 . The method for forming a semiconductor device according to claim 1 , wherein the dielectric layer comprises a single-layer structure or a stacked-layer structure. 3 . 3.如权利要求2所述半导体器件的形成方法，其特征在于，所述介质层为单层结构时，所述介质层的材料包括氧化硅或氮化硅或氮氧化硅或碳氧化硅或碳氮化硅或碳氮氧化硅中的一种。3. The method for forming a semiconductor device as claimed in claim 2, characterized in that when the dielectric layer is a single-layer structure, the material of the dielectric layer includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon carbon oxynitride. 4.如权利要求2所述半导体器件的形成方法，其特征在于，所述介质层为叠层结构时，所述介质层包括第一介质层和第二介质层，所述第二介质层位于所述第一介质层上。4 . The method for forming a semiconductor device according to claim 2 , wherein when the dielectric layer is a stacked structure, the dielectric layer comprises a first dielectric layer and a second dielectric layer, and the second dielectric layer is located on the first dielectric layer. 5.如权利要求4所述半导体器件的形成方法，其特征在于，所述第一介质层的材料与所述第二介质层的材料不同。5 . The method for forming a semiconductor device according to claim 4 , wherein a material of the first dielectric layer is different from a material of the second dielectric layer. 6.如权利要求5所述半导体器件的形成方法，其特征在于，所述第一介质层的材料包括氮氧化硅或者碳氮氧化硅中的一种或者多种。6 . The method for forming a semiconductor device according to claim 5 , wherein the material of the first dielectric layer comprises one or more of silicon oxynitride or silicon oxycarbonitride. 7.如权利要求6所述半导体器件的形成方法，其特征在于，所述第二介质层的材料为氮化硅。7 . The method for forming a semiconductor device according to claim 6 , wherein the material of the second dielectric layer is silicon nitride. 8.如权利要求1所述半导体器件的形成方法，其特征在于，所述硬掩膜层的材料包括氮化硅或氧化硅或碳化硅或碳氧化硅中的一种或者多种。8 . The method for forming a semiconductor device according to claim 1 , wherein the material of the hard mask layer comprises one or more of silicon nitride, silicon oxide, silicon carbide, or silicon oxycarbide. 9.如权利要求1所述半导体器件的形成方法，其特征在于，所述牺牲侧墙的材料包括氧化硅或氮化硅或碳化硅中的一种或多种。9 . The method for forming a semiconductor device according to claim 1 , wherein the material of the sacrificial spacer comprises one or more of silicon oxide, silicon nitride or silicon carbide. 10.如权利要求1所述半导体器件的形成方法，其特征在于，在所述开口内填充介质层，所述介质层的顶部与所述硬掩膜层的顶部齐平之后，还包括，去除所述牺牲层以及所述牺牲层覆盖的所述伪栅结构。10. The method for forming a semiconductor device according to claim 1, characterized in that after a dielectric layer is filled in the opening and a top of the dielectric layer is flush with a top of the hard mask layer, the method further comprises removing the sacrificial layer and the dummy gate structure covered by the sacrificial layer. 11.一种采用权利要求1至10任一项方法所形成的半导体器件，其特征在于，包括：11. A semiconductor device formed by the method according to any one of claims 1 to 10, characterized in that it comprises: 衬底；substrate; 若干鳍部，分立位于所述衬底上；A plurality of fins are separately located on the substrate; 伪栅结构，位于所述衬底上且横跨所述鳍部；a dummy gate structure, located on the substrate and spanning the fin; 硬掩膜层，分立位于所述伪栅结构上；A hard mask layer is discretely located on the dummy gate structure; 开口，位于相邻的所述硬掩膜层之间以及所述硬掩膜层下的相邻的所述伪栅结构之间；An opening is located between adjacent hard mask layers and between adjacent dummy gate structures under the hard mask layer; 介质层，位于所述开口内，且顶部与所述硬掩膜层的顶部齐平；a dielectric layer, located in the opening, and having a top flush with a top of the hard mask layer; 牺牲层，位于相邻的所述介质层之间，且位于所述伪栅结构上。The sacrificial layer is located between the adjacent dielectric layers and on the dummy gate structure.
CN201910407216.2A 2019-05-15 2019-05-15 Semiconductor device and method of forming the same Active CN111952357B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910407216.2A CN111952357B (en) 2019-05-15 2019-05-15 Semiconductor device and method of forming the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910407216.2A CN111952357B (en) 2019-05-15 2019-05-15 Semiconductor device and method of forming the same

Publications (2)

Publication Number Publication Date
CN111952357A CN111952357A (en) 2020-11-17
CN111952357B true CN111952357B (en) 2024-04-19

Family

ID=73335534

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910407216.2A Active CN111952357B (en) 2019-05-15 2019-05-15 Semiconductor device and method of forming the same

Country Status (1)

Country Link
CN (1) CN111952357B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113078117A (en) * 2021-03-30 2021-07-06 长鑫存储技术有限公司 Mask pattern, semiconductor structure and preparation method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579084A (en) * 2012-07-20 2014-02-12 中芯国际集成电路制造(上海)有限公司 Method for forming parallel metal interconnection structures
CN103681270A (en) * 2012-09-03 2014-03-26 中芯国际集成电路制造(上海)有限公司 Metal grid forming method
CN106158637A (en) * 2015-03-31 2016-11-23 中芯国际集成电路制造(上海)有限公司 Fin formula field effect transistor and forming method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171927B2 (en) * 2013-03-26 2015-10-27 GlobalFoundries, Inc. Spacer replacement for replacement metal gate semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579084A (en) * 2012-07-20 2014-02-12 中芯国际集成电路制造(上海)有限公司 Method for forming parallel metal interconnection structures
CN103681270A (en) * 2012-09-03 2014-03-26 中芯国际集成电路制造(上海)有限公司 Metal grid forming method
CN106158637A (en) * 2015-03-31 2016-11-23 中芯国际集成电路制造(上海)有限公司 Fin formula field effect transistor and forming method thereof

Also Published As

Publication number Publication date
CN111952357A (en) 2020-11-17

Similar Documents

Publication Publication Date Title
CN111180513B (en) Semiconductor device and method of forming the same
CN107799462B (en) Method of forming a semiconductor structure
CN109979986B (en) Semiconductor device and method of forming the same
CN110648915B (en) Semiconductor device and method of forming the same
CN110797262B (en) Semiconductor device and method of forming the same
CN111508897A (en) Semiconductor device and method of forming the same
US20230387249A1 (en) Method for fabricating gate-all-around (gaa) structure
CN106558608B (en) Semiconductor devices and forming method thereof
CN107564859A (en) Semiconductor device and its manufacture method
CN111952357B (en) Semiconductor device and method of forming the same
CN111986995A (en) Semiconductor device and method of forming the same
US9660058B2 (en) Method of FinFET formation
CN107452680A (en) Semiconductor device and its manufacture method
CN104078363A (en) Semiconductor device manufacturing method
CN108122762B (en) Semiconductor structures and methods of forming them
CN111384172A (en) Semiconductor device and method of forming the same
CN112928024B (en) Semiconductor structures and methods of forming them
CN112086356B (en) Semiconductor device and method of forming the same
CN111863730B (en) Semiconductor device and method of forming the same
CN111446286B (en) Semiconductor structures and methods of forming them
CN114864691A (en) Semiconductor structure and method of forming the same
CN107516674B (en) Method for forming fin field effect transistor
CN113113485B (en) Semiconductor device and method of forming the same
CN114068709B (en) Semiconductor device and method of forming the same
CN113937163B (en) Semiconductor device and method of forming the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant