CN111952313A

CN111952313A - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN111952313A
Application number: CN202010864997.0A
Authority: CN
Inventors: 周颖; 李明
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-08-25
Filing date: 2020-08-25
Publication date: 2020-11-17

Abstract

The present invention relates to a three-dimensional memory and a method for manufacturing the same, the three-dimensional memory including: a substrate; a core storage region and a step region formed on the substrate, the core storage region including a stacked structure formed on the substrate, the step region including a step structure formed by the stacked structure; a gate line extending through the core storage region and the step region; and the groove is positioned between two adjacent grid lines, and the length of the groove is smaller than that of the grid lines. The three-dimensional memory comprises a support structure formed by a plurality of grooves, so that the problems of insufficient support, collapse and the like caused by the defects of a deep hole structure can be avoided. The manufacturing method of the three-dimensional memory has simple process, greatly reduces the etching difficulty of higher depth-to-width ratio in the three-dimensional memory, and increases the process window of the subsequent process.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The invention relates to the field of integrated circuit manufacturing, in particular to a three-dimensional memory with a groove supporting structure and a manufacturing method thereof.

Background

In order to overcome the limitation of the two-dimensional memory device, a memory device having a three-dimensional (3D) structure, which increases integration density by arranging memory cells three-dimensionally over a substrate, has been developed and mass-produced in the industry. With the increasing number of layers of 3D NAND, in order to prevent deformation or collapse of the stacked structure, some dummy channel holes may be formed as support structures in some regions in the semiconductor device without affecting the device performance. However, with the continuous progress of semiconductor technology, after the three-dimensional memory device passes through various process environments, such as high temperature, high pressure, etc., the formed support structure is deformed or even collapsed, and thus cannot effectively support.

Disclosure of Invention

The invention provides a three-dimensional memory with a groove supporting structure and a manufacturing method thereof.

The present invention adopts a technical solution to solve the above technical problems, and is a three-dimensional memory, including: a substrate; a core storage region and a step region formed on the substrate, the core storage region including a stacked structure formed on the substrate, the step region including a step structure formed by the stacked structure; a gate line extending through the core storage region and the step region; and the groove is positioned between two adjacent grid lines, and the length of the groove is smaller than that of the grid lines.

In an embodiment of the present invention, the method further includes: and the top selection gate region is formed on the substrate, is positioned between the core storage region and the step region, and penetrates through the top selection gate region.

In an embodiment of the invention, the width of the trench varies with the step height.

In an embodiment of the invention, a width of the trench near a first end of the step is smaller than a width of the trench far from a second end of the step.

In an embodiment of the invention, two ends of the groove are circular arcs.

In one embodiment of the present invention, a dummy trench hole is included through the stacked structure.

In an embodiment of the invention, the groove is formed by a plurality of discontinuous grooves.

In an embodiment of the invention, at least two of the plurality of grooves cross each other.

In an embodiment of the invention, the mutually crossed grooves form a Chinese character feng structure or a Chinese character jing structure.

In an embodiment of the invention, the trench is filled with an insulating material.

In an embodiment of the invention, the three-dimensional memory is a 3D NAND flash memory.

The present invention further provides a method for manufacturing a three-dimensional memory to solve the above technical problems, comprising: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, and a core storage area and a step area which are formed on the substrate, the core storage area comprises a stacked structure formed on the substrate, and the step area comprises a step structure formed by the stacked structure; forming a gate line penetrating the core storage region and the step region; and forming a groove between two adjacent grid lines, wherein the length of the groove is smaller than that of the grid line.

In an embodiment of the present invention, the method further includes: the semiconductor structure further comprises a top selection gate region formed on the substrate, the top selection gate region is located between the core storage region and the step region, and the gate line penetrates through the top selection gate region.

In an embodiment of the invention, two ends of the groove are circular arcs.

In an embodiment of the present invention, the method further includes: forming a dummy trench hole through the stacked structure.

In an embodiment of the present invention, the method further includes: and filling an insulating material in the groove.

In an embodiment of the invention, the trench is formed by dry etching.

The three-dimensional memory comprises a supporting structure formed by a plurality of grooves, and at least two grooves are intersected with each other, so that compared with a deep-hole supporting structure, the supporting effect of the groove supporting structure is better, and the problems of insufficient support, collapse and the like caused by the defects of the deep-hole structure can be avoided. The manufacturing method of the three-dimensional memory has simple process, greatly reduces the etching difficulty of higher depth-to-width ratio in the three-dimensional memory, and increases the process window of the subsequent process.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1 is a schematic cross-sectional view of a three-dimensional memory;

FIGS. 2A-2D are schematic diagrams of a support structure in a semiconductor structure;

FIGS. 3A and 3B are cross-sectional views of holes and trenches in the semiconductor structure shown in FIGS. 2A and 2B;

FIGS. 3C and 3D are cross-sectional views of holes and trenches in the semiconductor structure shown in FIGS. 2C and 2D;

FIG. 4 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the invention;

fig. 5A-5C are top views of the three-dimensional memory of the embodiment shown in fig. 4.

FIGS. 6A-6C are schematic views of a trench structure of a three-dimensional memory according to an embodiment of the invention;

FIG. 7 is an exemplary flow chart of a method of fabricating a three-dimensional memory according to one embodiment of the invention;

fig. 8A-8D are schematic views illustrating a process for forming a trench in a three-dimensional memory according to an embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

As used herein, the term "substrate" refers to a material upon which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

The term "layer" as used in this application refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Fig. 1 is a schematic cross-sectional view of a three-dimensional memory. Referring to fig. 1, the three-dimensional memory 100 includes a substrate 101 and a stacked structure 102 formed on the substrate 101. The substrate 101 extends along a first direction D1, and the stacked structure 102 is formed by stacking a first material layer and a second material layer along a second direction D2 perpendicular to the first direction D1.

As shown in fig. 1, the three-dimensional memory 100 may be divided into a first area 110 and a second area 120 along a first direction D1. The first area 110 includes a core memory region in the three-dimensional memory 100, and the second area 120 includes a top select gate region 121 and a step region 122 adjacent to the core memory region. In some examples, a bottom select gate region is also included in the second region 120 away from the first region 110. The three-dimensional memory can be formed with some hole-like structures or groove-like structures for supporting, which are collectively called support structures. The support structure may be formed in the first region 110 and the second region 120.

Fig. 2A-2D are schematic diagrams of a support structure in a semiconductor structure. Fig. 2A and 2B are top and bottom views, respectively, of a semiconductor structure. Fig. 2A shows the top surface 210 of the semiconductor structure, including some holes 220 and trenches 230. In the top surface 210 shown in fig. 2A, two mutually parallel grooves 230 and a substantially uniform distribution of a plurality of holes 220 are included. Both the holes 220 and the trenches 230 serve as supports in the semiconductor structure. These holes 220 and trenches 230 may be filled with an insulating material to form support posts and support wall structures, respectively. These holes 220 and trenches 230 extend through the stack structure in the three-dimensional memory. The Critical Dimension (CD) of the hole 220 is represented by Ht1 in FIG. 2A. In semiconductor structures, critical dimensions are used to describe structural features. For the holes 220, the critical dimension refers to the spacing between two adjacent holes 220, as shown in FIG. 2A. In other embodiments, the distance between two holes 220 may be measured from the center of the adjacent two holes 220 as a measurement point. In fig. 2A, the critical dimension of the trench 230, which refers to the width of the trench 230, is denoted by Ct 1. In the example of fig. 2A, let Ht1 be 275nm and Ct1 be 145 nm.

The hole in the present invention refers to a hole-like structure having a small aspect ratio of the cross section and a deep depth along the second direction D2, and the cross section may be circular, square, oval, etc. The groove refers to a water channel-shaped structure with a large length and width of the cross section and a deep depth along the second direction D2, and the cross section of the water channel-shaped structure may be an elongated shape.

Fig. 2B illustrates a bottom surface 211 of the semiconductor structure shown in fig. 2A. As shown in fig. 2B, both the hole 220 and the trench 230 penetrate the semiconductor structure, forming a corresponding hole 221 and trench 231 on the bottom surface 211. Dry etching is typically used to form the hole and trench structures, and the critical dimensions of the formed holes and trenches do not remain completely consistent from top surface 210 to bottom surface 211. As the number of layers of the three-dimensional memory increases, the critical dimensions of the holes 221 and trenches 231 at the bottom surface 211 of the semiconductor structure vary significantly from the critical dimensions of the holes 220 and trenches 230 at the top surface 210 of the semiconductor structure. As shown in fig. 2B, the critical dimensions of the holes 221 and the trenches 231 on the bottom surface 211 are significantly reduced. Severely, the closing of the hole 221 may occur. Also, the smaller the critical dimensions of the hole 220 and the trench 230 at the top surface 210 of the semiconductor structure, the smaller the critical dimensions of the hole 221 and the trench 231 at the bottom surface 211 of the semiconductor structure.

For the semiconductor structure shown in fig. 2A and 2B, the critical dimensions of the holes and trenches at the bottom of the stacked structure are too small to facilitate the subsequent filling of the supporting material, so that the effective supporting function cannot be achieved.

The critical dimensions of the hole 222 and the trench 232 formed on the top surface 212 of the semiconductor structure in fig. 2C are larger than the critical dimensions of the hole 220 and the trench 230 shown in fig. 2A. In the example of fig. 2C, the critical dimension Ht2 of hole 222 is 300nm and the critical dimension Ct2 of trench 232 is 160nm at top surface 212.

Fig. 2D illustrates a bottom surface 213 of the semiconductor structure shown in fig. 2C. Since the critical dimensions of the hole 222 and the trench 232 in fig. 2C are larger, the critical dimensions of the hole 223 and the trench 233 on the bottom surface 213 of the semiconductor structure are also larger.

Although larger critical dimensions are beneficial for obtaining holes and trenches through the three-dimensional memory stack structure, too large a critical dimension also results in a smaller Landing Window (Contact bonding Window) of the Contact region during subsequent processes. For example, in the embodiment shown in fig. 2A and 2B, the landing window size of the contact region is 482 nm; whereas in the embodiment shown in fig. 2C and 2D the landing window size of the contact area is 429 nm. Therefore, for the semiconductor structures shown in fig. 2C and 2D, the landing window left for the contact region in the subsequent semiconductor process is small, which is not favorable for the subsequent process.

Fig. 3A and 3B are cross-sectional views of holes and trenches in the semiconductor structure shown in fig. 2A and 2B. It should be noted that fig. 3A and 3B only show the holes and trenches from the top surface 210 of the semiconductor structure to the middle of the semiconductor structure, and do not show the portion from the middle to the bottom surface 211. As the number of layers of the stacked structure in the three-dimensional memory increases, the aspect ratio of the hole becomes larger. The deep hole structure formed in the laminated structure is deformed to some extent, for example, bent.

Fig. 3A shows a cross-sectional view of hole 220, where Ht1 represents the critical dimension of hole 220 at top surface 210, as previously described, Ht1 ═ 275 nm. Hm1 represents the critical dimension of the hole 220 in the middle of the stack, and Hm1 is 300nm in fig. 3A.

Fig. 3B shows a cross-sectional view of trench 230, where Ct1 represents the critical dimension of trench 230 at top surface 210, as described above, Ct1 ═ 145 nm. Cm1 represents the critical dimension of trench 230 in the middle of the stack, and in fig. 3B, Cm1 is 163 nm.

Fig. 3C and 3D are cross-sectional views of holes and trenches in the semiconductor structure shown in fig. 2C and 2D. As shown in fig. 3C, the critical dimension Ht2 of the hole 222 at the top surface 212 is 300nm, and the critical dimension Hm2 at the middle of the stacked structure is 350 nm. As shown in fig. 3D, the critical dimension Ct2 of trench 232 at top surface 212 is 160nm, and the critical dimension Cm2 in the middle of the stack is 183 nm.

Fig. 3A-3D are merely examples. A large amount of measurement data indicates that the deformation of the porous support structure, especially the porous support structure with a high aspect ratio, is larger in the semiconductor structure than in the trench structure. The trench structure has better conformality than the hole structure. The porous support structure described above is also referred to as a virtual channel hole. In order to perform a supporting function, a supporting material is filled in the dummy channel hole and the trench in a subsequent process. For the virtual channel hole with large deformation, some unfilled voids may be formed in the virtual channel hole, which is not favorable for filling the supporting material, thereby affecting the supporting effect of the virtual channel hole.

FIG. 4 is a cross-sectional view of a three-dimensional memory according to an embodiment of the invention. Referring to fig. 4, the three-dimensional memory 400 includes a substrate 401, a core storage region 410 and a step region 420 formed on the substrate 401. Wherein the core storage region 410 includes a stacked structure 402 formed on a substrate 401, and the stepped region 420 includes a stepped structure formed by the stacked structure 402. Gate lines (not shown) penetrating the core storage region 410 and the step region 420, and a trench 440 between two adjacent gate lines, wherein the length of the trench 440 is smaller than that of the gate lines. The number of trenches 440 is not limited by the present invention. As shown in fig. 4, a plurality of trenches 441 are included in the core memory region 410, and a plurality of

trenches

442, 444, 445, 446 are included in the step region 420.

Referring to fig. 4, the substrate 401 extends in a first direction D1, and the stacked structures 401 are stacked in a second direction D2 perpendicular to the first direction D1. A dielectric layer 403 is included over the step structure. A number of channel holes 404 are included in the core memory region 410 through the stacked structure 401.

The substrate 401 may be a Silicon substrate (Si), a Germanium substrate (Ge), a Silicon Germanium substrate (SiGe), a Silicon On Insulator (SOI), a Germanium On Insulator (GOI), or the like. In some embodiments, the substrate 401 may also be a substrate comprising other elemental or compound semiconductors, such as GaAs, InP, or SiC. But also a stacked structure such as Si/SiGe or the like. Other epitaxial structures may also be included, such as Silicon Germanium On Insulator (SGOI) and the like. In some embodiments, the substrate 401 may be made of a non-conductive material, such as glass, plastic, or sapphire wafers, among others. The substrate 401 shown in fig. 4 may have undergone some necessary processing, such as having formed a common active region and having undergone necessary cleaning, etc.

The stacked structure 402 may be a stack in which first material layers and second material layers are alternately stacked. The first material layer and the second material layer may be selected from materials and include at least one insulating dielectric such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer and the second material layer have different etching selectivity. For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like may be used. The deposition method of the first material layer and the second material layer of the stack structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or a physical vapor deposition method such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, among various methods thereof. The first material layer can be a gate layer or a dummy gate layer, and the second material layer is a dielectric layer. The material for the gate sacrificial layer may be, for example, a silicon nitride layer. The material for the gate layer may be a conductive material such as tungsten, cobalt, copper, nickel, etc., or may be polysilicon, doped silicon, or any combination thereof. The material for the dielectric layer may be, for example, silicon oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like.

In an embodiment of the present invention, the material of the substrate 401 is, for example, silicon. The first material layer and the second material layer are, for example, a combination of silicon nitride and silicon oxide. Taking the combination of silicon nitride and silicon oxide as an example, the stacked structure 402 may be formed by alternately depositing silicon nitride and silicon oxide on the substrate 401 in sequence by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or other suitable deposition methods.

Although exemplary configurations of the initial semiconductor structure are described herein, it will be appreciated that one or more features may be omitted, substituted, or added to the semiconductor structure. For example, various well regions may be formed in the substrate as desired. In addition, the materials of the various layers illustrated are merely exemplary, and for example, substrate 401 may also be other silicon-containing substrates, such as SOI (silicon on insulator), SiGe, Si: C, and the like. The gate layer may also be other conductive layers such as tungsten, cobalt, nickel, etc. The second material layer may also be other dielectric materials such as aluminum oxide, hafnium oxide, tantalum oxide, and the like.

The channel hole 404 includes a vertical channel structure therein. In the overall view, the memory layer and the channel layer are arranged in this order from the outside to the inside in the radial direction of the channel hole 404. The memory layer may include a blocking layer, a charge trapping layer, and a tunneling layer sequentially disposed from an outside to an inside in a radial direction of the channel hole. A filling layer can be arranged in the channel layer. The filler layer may function as a support. The material of the fill layer may be silicon oxide. The filling layer can be solid or hollow without affecting the reliability of the device. The formation of the vertical channel structure may be accomplished using one or more thin film deposition processes, such as ALD, CVD, PVD, the like, or any combination thereof.

Referring to fig. 4, in some embodiments, the three-dimensional memory of the present invention further includes a top select gate region 430, and the top select gate region 430 is located between the core memory region 410 and the step region 420, and may be a part of the core memory region 410. The gate line runs through the core storage region 410, the top select gate region 430 and the stepped region 420 at the same time.

In the core memory region 410, a trench 441 extends through the stacked structure 402 and to the substrate 401, and a plurality of trenches are inserted between memory strings in the memory array without affecting the performance of the memory array. At the top select gate region 430, a trench 443 extends through the stacked structure 402 and to the substrate 401. In the step region 420,

trenches

442, 444, 445, 446 extend through the step structure and the dielectric layer 403 above it and reach the substrate 401.

It should be noted that the trench in the present invention refers to a trench-like structure with a length obviously greater than a width, and the hole or the virtual trench hole refers to a circular hole, an elliptical hole or a rectangular hole with a similar length and width, including square holes with equal length and width.

The method of forming the trench may be exposing, photolithography, and etching using a patterned mask to form the trench. In an embodiment of the present invention, the insulating material filling the trench may be silicon oxide. Depending on the flatness of the wafer surface caused by different formation methods (e.g., Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), spin-coating, etc.), when the flatness is not sufficient, a chemical mechanical polishing step may be added subsequently.

The depth of the trench can be controlled by the etching process parameters (such as etching time, gas flow, mixture ratio, pressure, temperature, etc.), and under the condition of a certain etching rate, the longer the etching time is, the deeper the trench is. The etching method may be dry etching. The dry etching may be, for example, plasma etching.

In some embodiments, the plurality of trenches are formed only in the top select gate regions 430.

In some embodiments, a plurality of trenches are formed only in the stepped region 420.

In some embodiments, the virtual channel hole is not included in the top select gate region 430 and/or the step region 420.

In an embodiment of the present invention, the width of the trench may be determined by the requirements of the process window of the subsequent process. For example, the size of the landing window of the contact area to be formed later.

In some embodiments, the trenches of the three-dimensional memory of the present invention are filled with an insulating material. The filled insulating material can function to support the stacked structure 402 to enhance the robustness of the three-dimensional memory structure.

Fig. 4 shows the distribution of trenches in the three-dimensional memory 400 from a side view of the three-dimensional memory 400 only. To illustrate the specific structure of the trenches of the present invention in the three-dimensional memory 400, fig. 5A-5C show the structure of the trenches from a top view.

Fig. 5A-5C are top views of the three-dimensional memory of the embodiment shown in fig. 4. Fig. 5A-5C are diagrams illustrating the structure of a plurality of trenches in a three-dimensional memory according to the present invention, and do not show the entire structure of the three-dimensional memory shown in fig. 4.

Referring to fig. 5A, a plurality of gate lines 510 are included in the three-dimensional memory in parallel with each other. The gate line 510 extends through the core storage region 410, the step region 420, and/or the top select gate region 430, both in the first direction D1 shown in fig. 4, and in the second direction D2 through the stacked structure 402. The present invention does not limit the number of the gate lines 510.

Referring to fig. 5A, a trench 520 is included between two adjacent gate lines 510, and the length of the trench 520 is smaller than that of the gate line 510. As shown in fig. 5A, a trench 520 is included between two adjacent gate lines 510, and the trench 520 extends in a direction parallel to the gate lines 510. In other embodiments, a plurality of trenches 520 may be included between two adjacent gate lines 510.

In some embodiments, the trenches in the three-dimensional memory of the present invention are comprised of a plurality of discontinuous trenches. Referring to fig. 5B, 2 trenches 521 are respectively included between two adjacent gate lines 510. The 2 grooves 521 are distributed in a straight line along the first direction D1 and have a certain distance therebetween.

In other embodiments, the plurality of grooves 521 may not be distributed along a straight line. For example, the grooves 521 may be staggered, and the extending direction of the grooves 521 may not be parallel to the first direction D1.

In some embodiments, the width of the trench varies with the step height. The step height refers to the height of the step from the substrate. Referring to fig. 4, the step height at the step region 420 is gradually decreased as the step is farther from the core storage region 410, and the step height is highest adjacent to the core storage region 410. A plurality of trenches are included in the stepped region 420, wherein the trench 442 closest to the core memory region 410 has the widest width, and the

trenches

444, 445, 446 have sequentially increasing distances from the core memory region 410 and sequentially decreasing widths. Since the etching rate for the step structure and the dielectric layer 403 is different when the trench is formed, in order to form a plurality of trenches at different positions in the same step, the etching time can be adjusted by setting the width of the trench to improve the etching efficiency, thereby forming the three-dimensional memory of the embodiments.

In other embodiments, the rule of the variation of the width of the trench with the step height is not limited by fig. 4. The width of the trenches distributed at different locations in the core storage region 410, the step region 420, and/or the top select gate region 430 may all be different.

Fig. 4 is not intended to limit the distribution of the trenches 440 at different locations. In the structure of the three-dimensional memory, the higher the step structure height of the step region 420, the better the supporting effect of the supporting structure is required. Thus, more trenches can be formed closer to the core storage region 410 and fewer trenches can be formed farther from the core storage region 410 in the plateau region 420.

In some embodiments, the length of the groove extends in a first direction D1 shown in fig. 4. Referring to fig. 5B, trenches are included in both the core storage region 410 and the stepped region 420 of the three-dimensional memory, and the step height in the stepped region 420 decreases with distance from the core storage region 410. In the step region 420, the width of the groove 523 near the first end 523a of the step is greater than the width of the second end 523b remote from the step.

In some embodiments, the ends of the trench are rounded as shown in FIG. 5B. In other embodiments, the ends of the channel can have other shapes, such as the straight line shown in FIG. 5A, making the channel 520 rectangular.

In some embodiments, a virtual channel hole is also included in the three-dimensional memory of the present invention through the stacked structure. Referring to fig. 4, virtual channel holes 451, 452 extend through the stack structure 402 in the core storage region 410 and the stack structure in the step region 420, respectively. Referring to fig. 5A and 5B, a plurality of virtual channel holes 530 are shown from a top view. The plurality of dummy channel holes 530 are distributed between two adjacent gate lines 510. The cross-section of the dummy trench hole 530 shown in fig. 5A and 5B is square. In other embodiments, the cross-section of the dummy trench hole 530 may also be circular, elliptical, etc.

According to the embodiment shown in fig. 5A and 5B, both trenches and dummy channel holes are included between adjacent gate lines of the three-dimensional memory, and both the trenches and the dummy channel holes serve as supports.

Referring to fig. 5C, at least two trenches of the plurality of trenches of this embodiment cross each other. For example, as shown in fig. 5C, the first trenches 524 are interdigitated with the second trenches 525. In the embodiment shown in fig. 5C, the first trench 524 extends in a direction parallel to the gate line 510, and the first trench 524 and the second trench 525 cross each other perpendicularly, that is, the second trench 525 extends in a direction perpendicular to the gate line 510.

In the embodiment shown in fig. 5C, the first trench 524 and the plurality of second trenches 525 form a "fogged" like structure. It is apparent that the length of the second trench 525 is less than the length of the first trench 524.

In some embodiments, at least two of the plurality of grooves are parallel to each other. In the embodiment shown in fig. 5C, the plurality of second trenches 525 are parallel to each other. The second trenches 525 may or may not be equally spaced from each other.

In the embodiment shown in fig. 5C, the virtual channel hole is not included in the three-dimensional memory.

Fig. 6A-6C are schematic views of a trench structure in a three-dimensional memory according to an embodiment of the invention. Only the structure of the trench is shown which may be used in the three-dimensional memory described above.

Referring to fig. 6A, the first trench 611 and the second trench 612 cross each other. The angle between the second groove 612 and the first groove 611 is not 90 degrees.

In the embodiment shown in fig. 6A, the plurality of grooves includes two first grooves 611 parallel to each other and two second grooves 612 parallel to each other. The first trench 611 and the second trench 612 form a structure like a "well".

Fig. 6B shows a trench structure in another embodiment of the present invention. In this embodiment, the length of the first trench 613 is shorter than the first trench 611 in fig. 6A. Therefore, the first trench 613 includes a plurality of first trenches 613 in a length extending direction of the first trench 613. The second trench 614 perpendicularly crosses the first trench 613. A plurality of second grooves 614 may also be included in the length extension direction of the second grooves 614.

Fig. 6C shows a trench structure in another embodiment of the present invention. In this embodiment, the length of the second trench 616 is shorter compared to the second trench 614 in fig. 6B. A plurality of second trenches 616 may thus be included in the direction of the length extension of the second trenches 616, thereby forming a plurality of "cross" structures as shown in fig. 6C together with the first trenches 615. The first groove 615 may also include a plurality of first grooves 615 in a direction in which the first groove 615 extends in length.

Fig. 6A-6C are not intended to limit the number of first and second grooves and the amount of included angle between the first and second grooves. For example, the included angle between the first trench 615 and the second trench 616 in fig. 6C may not be equal to 90 degrees.

According to the three-dimensional memory structure shown in fig. 5A-6C, at least two of the plurality of trenches can be in communication with each other, facilitating the entry of ions and the exit of polymer during the dry etching process that forms the trench structure. For the three-dimensional memory with more layers in the future, the etching difficulty of the high-aspect-ratio structure is greatly reduced.

In some embodiments, the three-dimensional memory is a 3D NAND flash memory.

The invention does not limit the first and second grooves to be linear grooves. In other embodiments, the first groove and the second groove may have other shapes such as a curved line shape, a broken line shape, and the like.

Fig. 5A to 6C only show the trench structure in the three-dimensional memory of the present invention, and the other structures of the three-dimensional memory can refer to fig. 4 and the description thereof.

According to the three-dimensional memory, the supporting structure formed by the grooves is included, compared with a deep-hole supporting structure, the supporting effect of the groove supporting structure is better, and the problems of insufficient support, collapse and the like caused by the defects of the deep-hole structure can be avoided. Moreover, the groove supporting structure can provide a larger landing window for a contact area to be formed in a subsequent process.

Fig. 7 is an exemplary flowchart of a method of manufacturing a three-dimensional memory according to an embodiment of the present invention. The three-dimensional memory described above in the present invention can be manufactured by using the method for manufacturing the three-dimensional memory, and therefore, the description of the three-dimensional memory can be used to describe the method for manufacturing the three-dimensional memory of the present invention. Referring to fig. 7, the manufacturing method of this embodiment includes the steps of:

step 710: a semiconductor structure is provided, the semiconductor structure comprises a substrate, and a core storage area and a step area which are formed on the substrate, the core storage area comprises a stacked structure formed on the substrate, and the step area comprises a step structure formed by the stacked structure.

Step 720: and forming a grid line penetrating through the core storage region and the step region.

Step 730: and forming a groove between two adjacent grid lines, wherein the length of the groove is less than that of the grid lines.

In one embodiment, the method for manufacturing a three-dimensional memory of the present invention further includes the steps of:

step 740: the semiconductor structure further comprises a top selection gate region formed on the substrate, the top selection gate region is located between the core storage region and the step region, and the gate line penetrates through the top selection gate region.

step 750: a dummy trench hole is formed through the stacked structure.

In some embodiments, the width of the trench formed varies with the step height.

In some embodiments, the trench is formed to have a width proximate a first end of the step that is less than a width distal a second end of the step.

In some embodiments, the trench is formed to have a circular arc shape at both ends.

In some embodiments, the formed groove is comprised of a plurality of discontinuous grooves.

In some embodiments, at least two of the plurality of trenches formed intersect each other.

In some embodiments, the plurality of first and second trenches that intersect each other form a "well" or "torx" structure. Reference is made to fig. 5C and 6A-6C and the accompanying description.

In some embodiments, filling the trench with an insulating material is further included.

In some embodiments, the plurality of trenches are formed using a dry etch.

Fig. 8A-8D are schematic views illustrating a process for forming a trench in a three-dimensional memory according to an embodiment of the invention. A plurality of trenches in the three-dimensional memory of the present invention can be formed according to this process.

Fig. 8A is a schematic diagram of a three-dimensional memory before forming a trench. Shown in fig. 8A may be a core storage region 410, a staircase region 420, and/or a top select gate region 430 in the three-dimensional memory 400 shown in fig. 4. In which the substrate 801 corresponds to the substrate 401 shown in fig. 4 and the stacked structure 802 corresponds to the stacked structure 402 shown in fig. 4. To form a trench, at least a hard mask layer 820 and a photoresist layer 810 are formed over the stacked structure 802. Some layers, such as oxide layers, may also be included between the stacked structure 802 and the hard mask layer 820.

As shown in fig. 8B, the photoresist layer 810 is developed using a trench pattern corresponding to the trench at this step, thereby forming a first pattern 830 at a position where the trench is to be formed. The first pattern 830 transfers the trench pattern to the hard mask layer 820.

As shown in fig. 8C, a second pattern 831 is formed at the hard mask layer 820 using a hard mask dry etching at this step, and the trench pattern is transferred to a film layer under the hard mask layer 820.

As shown in fig. 8D, the film layer under the hard mask layer 820 is etched using dry etching at this step, thereby forming a trench 832. The trench 832 passes through the stacked structure 802 to the substrate 801.

According to the manufacturing method of the three-dimensional memory, the plurality of grooves are formed between two adjacent grid lines of the three-dimensional memory to form the groove supporting structure, so that the three-dimensional memory can be more effectively supported. The manufacturing method has simple process, greatly reduces the etching difficulty of higher depth-to-width ratio in the three-dimensional memory, and increases the process window of the subsequent process.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A three-dimensional memory, comprising:

a substrate;

a core storage region and a step region formed on the substrate, the core storage region including a stacked structure formed on the substrate, the step region including a step structure formed by the stacked structure;

a gate line extending through the core storage region and the step region; and

and the length of the groove is smaller than that of the grid line.

2. The three-dimensional memory according to claim 1, further comprising:

and the top selection gate region is formed on the substrate, is positioned between the core storage region and the step region, and penetrates through the top selection gate region.

3. The three-dimensional memory of claim 1 or 2, wherein a width of the trench varies with step height.

4. The three-dimensional memory according to claim 1 or 2, wherein a width of the trench near a first end of the step is smaller than a width of the trench far from a second end of the step.

5. The three-dimensional memory according to claim 1 or 2, wherein both ends of the trench are rounded.

6. The three-dimensional memory according to claim 1 or 2, comprising a dummy trench hole through the stacked structure.

7. The three-dimensional memory according to claim 1 or 2, wherein the trench is composed of a plurality of discontinuous trenches.

8. The three-dimensional memory according to claim 7, wherein at least two of the plurality of trenches intersect each other.

9. The three-dimensional memory according to claim 8, wherein the intersecting trenches form a "fogged" or a "well" structure.

10. The three-dimensional memory according to claim 1 or 2, wherein the trench is filled with an insulating material.

11. The three-dimensional memory according to claim 1 or 2, wherein the three-dimensional memory is a 3D NAND flash memory.

12. A method of fabricating a three-dimensional memory, comprising:

providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, and a core storage area and a step area which are formed on the substrate, the core storage area comprises a stacked structure formed on the substrate, and the step area comprises a step structure formed by the stacked structure;

forming a gate line penetrating the core storage region and the step region; and

and forming a groove between two adjacent grid lines, wherein the length of the groove is smaller than that of the grid line.

13. The method of manufacturing of claim 12, further comprising:

the semiconductor structure further comprises a top selection gate region formed on the substrate, the top selection gate region is located between the core storage region and the step region, and the gate line penetrates through the top selection gate region.

14. The manufacturing method according to claim 12 or 13, wherein the width of the trench varies with the step height.

15. The method of manufacturing of claim 12 or 13, wherein a width of the trench proximate a first end of the step is less than a width of the trench distal a second end of the step.

16. The manufacturing method according to claim 12 or 13, wherein both ends of the groove are rounded.

17. The manufacturing method according to claim 12 or 13, further comprising: forming a dummy trench hole through the stacked structure.

18. The method of manufacturing of claim 12 or 13, wherein the grooves are formed by a plurality of discontinuous grooves.

19. The method of manufacturing of claim 18, wherein at least two of the plurality of grooves intersect one another.

20. The method of claim 19, wherein the interdigitated trenches form a "well" or a "well" type structure.

21. The manufacturing method according to claim 12 or 13, further comprising: and filling an insulating material in the groove.

22. The manufacturing method according to claim 12 or 13, wherein the trench is formed by dry etching.