CN111952263A - A micron-scale single crystal copper interconnect structure and preparation method thereof - Google Patents

Abstract

The invention discloses a micron-level single crystal copper interconnection structure and a preparation method thereof, belonging to the field of electronic packaging. The structure mainly includes a base, a barrier layer, a phosphorous-containing copper seed layer, and a copper needle; the base is a dielectric layer with through holes and grooves, a silicon wafer with blind holes, and a semiconductor substrate with copper pillar windows. A kind of; the barrier layer is arranged on the inner sidewall and bottom of the through hole and the trench of the dielectric layer, the inner sidewall and bottom of the blind hole of the silicon wafer, or the bottom of the copper column window on the semiconductor substrate; A phosphorous copper seed layer is disposed over the barrier layer parallel to the substrate; the copper needles are deposited on the phosphorous copper seed layer. In the structure, phosphorus element is doped into the copper seed layer, and the micron-scale single crystal copper needle can be formed as a copper interconnection structure without the assistance of additives during electroplating. The copper interconnection structure obtained by the invention is a complete single crystal structure, and there is no lateral grain boundary, so that the transmission performance of the copper interconnection is significantly improved.

Description

A micron-scale single crystal copper interconnect structure and preparation method thereof

technical field

The invention relates to the technical field of copper interconnection in electronic packaging, in particular to a micron-scale single crystal copper interconnection structure and a preparation method thereof. A micron-scale single crystal copper interconnect structure is prepared on the seed layer. The method can be applied to Damascus technology, TSV (through silicon via) technology, copper pillar bump technology, etc. in three-dimensional system-in-package.

Background technique

In deep submicron integrated circuits, three-dimensional system-in-package can effectively utilize the three-dimensional space, improve the packaging density, reduce the package volume, shorten the lead length, and improve the transmission speed. Among them, Damascus technology for interconnection between chips, TSV technology for interconnection between silicon wafers, copper pillar bump technology for interconnection between chips and substrates, etc., have become research hotspots of high-density packaging structures. The dimensions applicable to these three technologies are different, but they are all at the micron level. Generally, the width is 1-100um and the depth is 10-300um.

The Damascus technology can be roughly summarized as: deposition of dielectric layer → photolithography and etching to form vias and trenches → successive deposition of tantalum barrier layers and copper seed layers in vias and trenches → electroplating of copper to fill vias and trenches → chemical Mechanical polishing removes excess metal → bonding. The TSV technology can be roughly summarized as follows: etching silicon vias → sequentially depositing insulating layers, barrier layers, and copper seed layers in silicon vias → electroplating copper to fill silicon vias → wafer thinning → bonding. The copper pillar bump technology can be roughly summarized as follows: etching the insulating layer on the semiconductor substrate to expose the metal pad → depositing the adhesion layer, barrier layer and copper seed layer in sequence → using photoresist to lithography the copper pillar window → electroplating copper Pillar → form solder bump on copper pillar → remove photoresist on both sides of copper pillar → bond → underfill. It can be found that these three widely used copper interconnect technologies basically have the similar steps of "hole formation", then depositing a copper seed layer in the hole, and finally "electroplating copper to fill the hole". The present invention mainly combines these similar steps. steps to optimize. Conventional "electroplating copper to fill holes" often requires the action of multiple additives to achieve bottom-up void-free filling, and the additive behavior is complex and the dosage is difficult to control.

In addition, with the increasing integration of electronic products, the transmission reliability of narrow-pitch and fine-width interconnect structures is also challenged, and as electronic products, electrical conductivity is extremely important. Some studies have shown that as the size of the interconnect becomes smaller, the resistivity caused by the grain boundary accounts for an increasing proportion of the bulk resistivity of the material, and will become the largest contributing factor. How to continue to reduce the chip size while ensuring the transmission performance has become a major problem in today's electronics industry.

In the existing studies, there are attempts to increase the grain size, thereby reducing the number of grain boundaries to improve the electrical conductivity. Basically, the method of thermal annealing after electroplating is used, which can reduce the resistivity by about 8%, but these studies do not The influence of grain boundaries on electrical conductivity cannot be completely eliminated, and the electroplating process is not improved, and the help of additives is still needed, but the steps of thermal annealing after electroplating are increased. There are also studies on the use of electroless plating or electroplating to directly obtain nano-single crystal copper cones, but the method of electroless plating has low repeatability and is not compatible with the preparation process of copper interconnect structures. The key to obtaining single crystal copper cones by electroplating is Additives, and nanometer size is also not suitable for copper interconnect structures. However, it can be seen that single crystal copper is bound to be a development direction of the copper interconnect structure in the future due to the elimination of the lateral grain boundaries as the source of resistance generation and signal attenuation.

Combining the shortcomings of the existing copper interconnect technology and the advantages of single crystal copper mentioned above, the electroplating method with good stability, repeatability and controllability is used to prepare micron-sized single crystals with matching dimensions without the aid of additives. Crystal copper needles to achieve interconnection have significant application value.

SUMMARY OF THE INVENTION

Aiming at the deficiencies of the prior art, the present invention provides a micron-level single crystal copper interconnection structure, and by using electroplating means and a simple plating solution without additives, a micron-level single crystal copper interconnection can be obtained on the phosphorus-containing seed layer structure. The method optimizes the prior art, has simple steps and low cost, and the obtained single crystal copper has no lateral grain boundaries and has outstanding electrical conductivity.

The purpose of this invention is to realize through the following technical solutions:

The invention provides a micron-scale single crystal copper interconnection structure, which mainly includes a substrate, a barrier layer, a phosphorous-containing copper seed layer, and a copper needle; the substrate is a dielectric layer with through holes and trenches, and silicon with blind holes. One of a wafer and a semiconductor substrate with a copper pillar window;

The barrier layer is arranged on the inner sidewall and bottom of the through hole and trench of the dielectric layer, the inner sidewall and bottom of the blind hole of the silicon wafer, or the bottom of the copper pillar window on the semiconductor substrate; the phosphorus-containing copper seed layer Disposed over the barrier layer parallel to the substrate; the copper pins are deposited on the phosphorous containing copper seed layer.

Preferably, the copper needles have a width ranging from 2 to 70 μm and a length ranging from 5 to 700 μm.

Preferably, in the phosphor copper seed layer, the phosphorus content is 0.02-0.075 wt %. If the phosphorus content is too high, it is easy to form an uneven black phosphorus film on the surface in the subsequent activation process, which is not conducive to the production of copper needles.

Preferably, the barrier layer is deposited by chemical vapor deposition; the phosphorus-containing copper seed layer is deposited by vacuum evaporation; and the copper needles are deposited by electroplating.

Preferably, before the copper needles are deposited on the phosphorous-containing copper seed layer, the phosphorous-containing copper seed layer needs to be pickled and activated.

Preferably, the pickling adopts dilute sulfuric acid with a volume fraction of 15-30% for 5-15 s; the activation step is specifically: according to the thickness of the deposited phosphorous-containing copper seed layer, applying a current of less than 0.08 A for 100 s ~3000s, the surface of the seed layer is slightly dissolved, but it is necessary to avoid the obvious black phosphorus film on the surface, so as to achieve the purpose of activation. If a black phosphorous film is produced, it can be washed with pure water before continuing to electroplating.

Preferably, the step of depositing the copper needles by the electroplating method specifically includes: electroplating with the phosphorous-containing copper seed layer as the cathode, the platinum electrode or the copper-phosphorus plate as the anode, and the electroplating solution adopted is the most each component including the following concentrations: Copper sulfate 0.5～1.5mol/L, sulfuric acid 0.1～1mol/L, potassium chloride 0.0005～0.008mol/L. The electroplating solution of the present invention does not need to add additives (such as accelerators, inhibitors, levelers, etc. commonly used in electroplating and filling holes), wherein copper sulfate is the main salt that provides copper ions, and sulfuric acid is mainly used to improve the conductivity of the electroplating solution and Dispersing ability, potassium chloride is also very important for the appearance of copper needles. If it is not added or the concentration is too low, no copper needles will appear. If the concentration is too high, the copper needles will gradually disappear. In severe cases, the coating is rough and burnt.

More preferably, the electroplating method adopts linear voltammetry scanning method, constant current, and constant potential, but from the aspect of effect, linear voltammetry scanning method is more preferable, and the value of electroplating parameters will affect the size of the obtained copper needle, and the specific parameter range. for:

The scanning speed of linear voltammetry scanning method is 0.05mV/s~1.5mV/s, and the scanning range is 0.1~-0.5V (vs.SCE). Generally, the slower the scanning speed and the larger the scanning range, the larger the size of the copper needle.

The current value of the constant current method is 0.01~0.1A. Generally, the larger the current, the larger the size of the copper needle.

The voltage of the potentiostatic method is 0.03~-0.15V (vs.SCE). Generally, the larger the potential, the larger the size of the copper needle.

Preferably, the dielectric layer is a four-layer structure of silicon nitride-silicon oxide-silicon nitride-silicon oxide, the dielectric layer is located on the lower copper layer, and acts as an insulation between the two layers of copper metal wiring.

An insulating layer is also provided between the sidewall and bottom of the blind hole of the silicon wafer and the blocking layer; the insulating layer material is selected from silicon oxide, silicon nitride, and polymer;

The semiconductor substrate is one of a silicon substrate, a silicon-on-insulator, and a silicon-germanium compound. The semiconductor substrate is provided with an insulating layer, and a metal pad is arranged on the insulating layer. The copper pillar window is a through hole formed at the position of the metal pad by photoresist through photolithography.

Preferably, the material of the barrier layer is selected from titanium, tantalum or its nitride, mainly to prevent the diffusion of copper and to improve the adhesion strength of the phosphorous copper seed layer; the phosphorous copper seed layer is mainly to promote copper electroplating Nucleation and growth of needles; the copper needles are micron-sized needle-like single crystal copper.

The invention also provides a preparation method of a micron-level single crystal copper interconnect structure, comprising the following steps:

A. Use chemical vapor deposition with good step coverage on the inner sidewalls and bottoms of through holes and trenches in the dielectric layer, the inner sidewalls and bottoms of blind holes in silicon wafers, or the bottom of copper pillar windows on semiconductor substrates barrier layer;

B. The phosphorus-containing copper seed layer is deposited by vacuum evaporation on the barrier layer parallel to the substrate;

C. The copper needles are deposited by electroplating on the phosphorous-containing copper seed layer.

Preferably, the method further includes the step of shortening the copper needle by chemical mechanical polishing.

Compared with the prior art, the present invention has the following beneficial effects:

1. The present invention mainly optimizes the similar steps of "electroplating copper to fill holes" in the Damascus process, the TSV process, and the copper pillar bump process after hole formation. The invention does not need to deposit the seed layer on both walls of the hole, but only deposits the seed layer at the bottom of the hole, and can grow copper on the seed layer by using phosphorus introduced into the seed layer and an acidic copper sulfate plating solution with simple composition and no additives. needle to complete bottom-up void-free copper filling.

2. The copper needle obtained by the present invention has a micron-level single crystal structure. The size is matched to the copper interconnect structure, and the size can be changed by changing the plating parameters. The single crystal structure has no lateral grain boundaries, which eliminates the contribution of grain boundaries to the resistivity, and has better electrical conductivity. In the increasingly miniaturized interconnect structure, the transmission performance can be better guaranteed.

Description of drawings

Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings:

Fig. 1 is the SEM image of the copper needle obtained in Example 1, imaged from obliquely above under the ion beam;

Fig. 2 is the SEM image of the copper needle obtained in Example 1, imaged from right above under backscattered electrons;

Fig. 3 is the electron selective area diffraction speckle diagram of the copper needle gained in Example 1;

Fig. 4 is the topography of the copper needle obtained in Example 2 after longitudinal sectioning with FIB;

5 is a schematic diagram of a copper interconnect structure obtained by an improved Damascus process;

6 is a schematic diagram of a copper interconnect structure obtained by an improved TSV process;

7 is a schematic diagram of a copper interconnect structure obtained by an improved copper pillar bump process;

FIG. 8 is an SEM image of the copper coating prepared in Comparative Example 1, which is imaged from right above under backscattered electrons, and the imaging conditions are the same as those of FIG. 2 .

Detailed ways

The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the inventive concept. These all belong to the protection scope of the present invention.

Example 1

To simplify the preparation of the copper interconnect structure, the most critical technology is to grow micron-scale single crystal copper needles from the phosphorous-containing copper seed layer, and other technologies are Damascus process, TSV process, copper pillar bump process. normal operation. Therefore, the specific preparation operations are as follows:

(1) Use phosphorus-containing copper sheet instead of phosphorus-containing copper seed layer as the electroplating base. The phosphorous-containing copper sheet used is a commercial copper sheet produced by Kobelco Corporation of Japan, and contains 0.03 wt % of phosphorous.

(2) In the degreasing solution, the phosphorous copper sheet was cathode degreasing at a current density of 3ASD for 20 seconds, and rinsed with deionized water. The formula of degreasing liquid is 40g/L sodium hydroxide, 20g/L sodium carbonate, 1g/L sodium lauryl sulfate.

(3) The phosphor-containing copper sheet is acid-washed for 5 seconds with sulfuric acid with a volume fraction of 20%, rinsed with deionized water, and dried.

(4) The device used for electroplating is Huachen CHI660D electrochemical workstation, which is a three-electrode two-circuit system device, in which the working electrode (ie the electroplating cathode) is a phosphorus-containing copper sheet sealed by epoxy resin, and the effective electroplating area is about 1.3 cm ² , the auxiliary electrode (ie, the electroplating anode) is a platinum electrode, the reference electrode is a CHI150 saturated calomel electrode (SCE), and the reference electrode and the working electrode are directly connected through a Lukin capillary.

(5) The plating solution used for electroplating is an acid sulfate plating solution, and the formula is 1 mol/L copper sulfate, 0.5 mol/L sulfuric acid, and 0.001 mol/L potassium chloride.

(6) The linear voltammetry scanning method is adopted, the scanning speed is 0.1mV/s, and the scanning range is 0.2～-0.2V. In this negative scanning interval, the electroplating process is actually divided into two parts. The first is the dissolution process of the phosphorous copper sheet at 0.2V to 0.06V, which completes the activation work similar to the seed layer. The dissolution current of the dissolution process is always lower than 0.07A, and it varies with the change of the potential. The dissolution time is 1400s, and no obvious black phosphorous film can be seen on the activated copper sheet. Next is the electrodeposition process of 0.06V～-0.2V, and the copper needles nucleate and grow on the activated copper sheet.

(7) After electroplating, take out the phosphorous copper sheet and rinse with deionized water and absolute ethanol. After drying, it was imaged under the GAIA3 ion beam, and the SEM morphology was photographed from the oblique top, as shown in Figure 1. The copper needles appeared in the figure were 12-32 μm in width and 50-130 μm in length. Imaged under TM3000 backscattered electrons, the SEM morphology taken from directly above is shown in Figure 2. The spots obtained by electron selective area diffraction on the copper needle are shown in Fig. 3, which are obvious single crystal diffraction spots.

Example 2

The difference between this embodiment and Embodiment 1 is that the sweep speed and interval are different, and the others are the same.

The specific differences are as follows: the scanning speed used in this embodiment is 1mV/s, and the scanning interval is 0.2-0.4V.

The obtained copper needle was longitudinally sectioned with FIB and imaged under FIB, as shown in Fig. 4 . It can be seen that the width of the copper needle is 2-6 μm and the length is 5-25 μm. The color of the cross-section of a single copper needle is uniform and consistent, not as messy as the copper layer at the bottom, which can also indicate that the copper needle is a complete single crystal structure.

Example 3

The present embodiment provides a method for preparing a micron-scale single crystal copper interconnect structure using Damascus technology, including the following steps:

(1) Depositing a dielectric layer, the dielectric layer is a four-layer structure of silicon nitride-silicon oxide-silicon nitride-silicon oxide, located on the lower copper layer; A barrier layer is deposited by chemical vapor deposition on the inner sidewalls and bottoms of the through holes and trenches of the layer;

(2) The phosphorus-containing copper seed layer is deposited by the vacuum evaporation method with good deposition direction above the barrier layer parallel to the dielectric layer; the phosphorus content is about 0.03wt%;

(3) Pickling the phosphorous copper seed layer with dilute sulfuric acid with a volume fraction of 20% for 10s, and then applying a reverse current of 0.05A for 2000s to slightly dissolve the surface of the seed layer to ensure that the phosphorus in the seed layer is exposed. A clear black phosphorous film completes the activation of the seed layer.

(4) Using the phosphorus-containing copper seed layer as the cathode, depositing copper on the seed layer by electroplating to obtain micron-scale single crystal copper needles; The plating solution used for electroplating is: copper sulfate 0.5 mol/L, sulfuric acid 0.1 mol/L, and potassium chloride 0.008 mol/L. The anode used for electroplating is an insoluble anode platinum electrode or a copper phosphor plate. Using constant current electroplating, the constant current is 0.035A, and the electroplating is 2600s.

(5) The obtained copper needles are appropriately shortened according to the required length of the copper needles by means of chemical mechanical polishing. The schematic diagram of the Damascus interconnection structure obtained so far is shown in FIG. 5 .

Example 4

The present embodiment provides a method for preparing a micron-scale single crystal copper interconnect structure using TSV technology, including the following steps:

(1) etching blind holes on the silicon wafer substrate, depositing insulating layers and barrier layers on the inner sidewall and bottom of the blind holes in turn;

(2) The phosphorus-containing copper seed layer is deposited by a vacuum evaporation method with good deposition direction above the barrier layer at the bottom of the blind hole; the phosphorus content is about 0.07wt%;

(3) Pickling the phosphorous copper seed layer with dilute sulfuric acid with a volume fraction of 15% for 30s, and then applying a reverse current of 0.03A for 3000s to slightly dissolve the surface of the seed layer to ensure that the phosphorus in the seed layer is exposed. A clear black phosphorous film completes the activation of the seed layer.

(4) Using the phosphorus-containing copper seed layer as the cathode, depositing copper on the seed layer by electroplating to obtain micron-scale single crystal copper needles; the side walls of the obtained copper needles are in direct contact with the walls of the blind holes. The plating solution used in electroplating is: copper sulfate 1.5mol/L, sulfuric acid 1mol/L, potassium chloride 0.0005mol/L. The anode used for electroplating is an insoluble anode platinum electrode or a copper phosphor plate. Using constant potential electroplating, the constant potential is -0.04V, and the electroplating is 2600s.

(5) The obtained copper needles are appropriately shortened according to the required length of the copper needles by means of chemical mechanical polishing. The TSV interconnection structure obtained so far is shown in FIG. 6 .

Example 5

The present embodiment provides a method for preparing a micron-scale single crystal copper interconnect structure using a copper pillar bump technology, including the following steps:

(1) Disposing metal pads on the insulating layer on the semiconductor substrate, coating photoresist on the semiconductor substrate, and patterning the photoresist to expose the metal pads and form copper pillar windows.

(2) A barrier layer and a copper seed layer containing 0.06 wt % of phosphorus are sequentially deposited on the bottom of the copper pillar window.

(3) The phosphorus-containing copper seed layer was acid washed with dilute sulfuric acid with a volume fraction of 30% for 5s, and then a reverse current of 0.08A was applied for 100s to slightly dissolve the surface of the seed layer to ensure that the phosphorus in the seed layer was exposed. A clear black phosphorous film completes the activation of the seed layer.

(4) Using the phosphorus-containing copper seed layer at the copper pillar window as the cathode, and depositing copper on the seed layer by electroplating, a micron-sized single crystal copper needle capable of filling the copper pillar window is obtained. The plating solution used in electroplating is: copper sulfate 1 mol/L, sulfuric acid 1 mol/L, and potassium chloride 0.001 mol/L. The anode used for electroplating is an insoluble anode platinum electrode or a copper phosphor plate. The electroplating method adopts the linear voltammetry scanning method, the scanning speed is 0.1mV/s, and the scanning interval is 0.1～-0.3V (vs.SCE).

(5) The obtained copper needles are appropriately shortened according to the required length of the copper needles by means of chemical mechanical polishing.

(6) electroplating solder on the top of the copper column;

(7) remove the photoresist;

(8) Reflow the solder on the top of the copper pillar to form a solder bump. The copper pillar bump interconnection structure obtained so far is shown in Figure 7. Although the photoresist is finally removed, the photoresist is still drawn in order to indicate the position of the photoresist during the preparation process.

Comparative Example 1

Compared with Example 1, the present comparative example differs only in that the step of activation is not performed in this comparative example.

The obtained copper coating did not have copper needles, and was imaged under TM3000 backscattered electrons, and the SEM morphology photographed from right above is shown in Figure 8. Compared with the SEM of the sample obtained in Example 1 (FIG. 2), the necessity of activation can be seen.

In summary, the present invention provides a micron-scale single crystal copper interconnect structure and a preparation method thereof, which are suitable for optimizing Damascus process, TSV process, and copper pillar bump process flow without additives, only in the copper seed layer. Phosphorus is introduced, and a simple plating solution and electroplating method are used to obtain micron-sized single crystal copper needles to realize interconnection, thereby improving the conductivity of the copper interconnection structure.

Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above-mentioned specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essential content of the present invention. The embodiments of the present application and features in the embodiments may be arbitrarily combined with each other without conflict.

Claims (10)

1. A micron-scale single crystal copper interconnection structure is characterized by mainly comprising a substrate, a barrier layer, a phosphorus-containing copper seed layer and copper needles; the substrate is one of a dielectric layer with a through hole and a groove, a silicon wafer with a blind hole and a semiconductor substrate with a copper cylinder window;

the barrier layer is arranged on the inner side walls and the bottoms of the through holes and the grooves of the dielectric layer, the inner side walls and the bottoms of the blind holes of the silicon wafer or the bottoms of the copper cylinder windows on the semiconductor substrate; the phosphorus-containing copper seed layer is arranged above the barrier layer parallel to the substrate; the copper needle is deposited on the phosphorus-containing copper seed layer.

2. The micron-sized single crystal copper interconnect structure of claim 1, wherein the copper needle has a width in the range of 2 to 70 μm and a length in the range of 5 to 700 μm.

3. The micron-sized single crystal copper interconnect structure of claim 1, wherein the phosphorous content in the phosphorous copper seed layer is 0.02 wt% to 0.075 wt%.

4. The micron-sized single crystal copper interconnect structure of claim 1 wherein said barrier layer is deposited by chemical vapor deposition; the phosphorus-containing copper seed layer is obtained by deposition through a vacuum evaporation method; the copper needle is obtained by deposition by adopting an electroplating method.

5. The micron-sized single crystal copper interconnect structure of claim 1 or 4, wherein the step of acid cleaning and activating the phosphorus-containing copper seed layer is required before depositing the copper pin on the phosphorus-containing copper seed layer.

6. The micron-sized single crystal copper interconnection structure according to claim 5, wherein dilute sulfuric acid with a volume fraction of 15-30% is adopted for acid washing, and the acid washing time is 5-15 s; the activating step specifically comprises: and applying a current less than 0.08A for 100-3000 s according to the thickness of the deposited phosphorus-containing copper seed layer, so that the surface of the seed layer is slightly dissolved, and an obvious black phosphorus film is prevented from being formed on the surface, thereby achieving the purpose of activation.

7. The micron-sized single crystal copper interconnect structure of claim 4, wherein the step of depositing copper needles by electroplating specifically comprises: electroplating by taking a phosphorus-containing copper seed layer as a cathode and a platinum electrode or a copper phosphor plate as an anode, wherein the adopted electroplating solution comprises the following components in concentration: 0.5-1.5 mol/L copper sulfate, 0.1-1 mol/L sulfuric acid, and 0.0005-0.008 mol/L potassium chloride.

8. The micron-scale single crystal copper interconnect structure of claim 1, wherein the dielectric layer is a four-layer structure of silicon nitride-silicon oxide-silicon nitride-silicon oxide;

an insulating layer is further arranged between the side wall and the bottom of the blind hole of the silicon wafer and the barrier layer, and the insulating layer is made of materials selected from silicon oxide, silicon nitride and polymers;

the semiconductor substrate is one of a silicon substrate, silicon on an insulator and a silicon germanium compound, the semiconductor substrate is provided with an insulating layer, a metal bonding pad is arranged on the insulating layer, and a copper column window of the semiconductor substrate is a through hole formed at the position of the metal bonding pad through photoetching by photoresist.

9. A method for preparing a micron-sized single crystal copper interconnect structure according to claim 1, comprising the steps of:

A. depositing a barrier layer on the inner side wall and the bottom of the through hole and the groove of the dielectric layer, the inner side wall and the bottom of the blind hole of the silicon wafer, or the bottom of the copper column window on the semiconductor substrate by adopting a chemical vapor deposition method;

B. depositing a phosphorus-containing copper seed layer above the barrier layer parallel to the substrate by a vacuum evaporation method;

C. and depositing copper needles on the phosphorus-containing copper seed layer by adopting an electroplating method.

10. The method of claim 9, further comprising the step of shortening the copper pins by chemical mechanical polishing.

Images