CN111950222B - Method for generating circuit layout by using simulation software - Google Patents

Abstract

A method for generating a circuit layout using simulation software, comprising the steps of: (A) Programming a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space; (B) Determining the size of the reserved space in the block according to at least one specific condition; (C) Determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one judging condition; and (D) when the step (C) judges that adjustment is not needed, generating the circuit layout according to the size of the reserved space in the block determined in the step (B).

Description

Method for generating circuit layout using simulation software

Technical Field

The present disclosure relates to the application of power integrity (PI), and more particularly to a method for properly determining a circuit layout to improve the problem that the circuit cannot operate normally.

Background technique

Circuit layout, such as printed circuit board layout (PCB layout), takes into account the problem of voltage decay (also known as IR Drop). Space is usually reserved between components to place capacitors (this operation is also called DCAP) as a solution to abnormal circuit operation. The above voltage decay is divided into static voltage decay and dynamic voltage decay. Among them, static voltage decay is mainly related to the structure and connection details of the power supply network. Therefore, static voltage decay mainly considers the resistance effect and analyzes the influence of resistance. Dynamic voltage decay is the voltage drop caused by current fluctuations when the power supply switches the circuit. This phenomenon occurs at the trigger edge of the clock, and often generates a large current on the entire chip in a short period of time. This instantaneous large current causes the voltage decay phenomenon. The more transistors that are switched at the same time, the easier it is to trigger the dynamic voltage decay phenomenon.

However, the prior art lacks a proper mechanism to determine how much space should be reserved between components for placing capacitors. For example, the prior art mechanism does not take into account the toggle rate of the circuit, and simply tries to find as much space as possible from the existing space to place capacitors. Please refer to FIG1, which is a schematic diagram of the circuit layout for reserving DCAP space in the prior art. Since the prior art method is to reserve space randomly or guess based on experience, it is very inefficient in reducing voltage decay. For example, if some blocks are already very full (space utilization is very high), there is not enough space to place DCAPs with higher capacitance values (the capacitance value of the capacitor is proportional to the volume) to suppress dynamic voltage decay. However, the toggle rate of such blocks with higher component placement density is usually higher, such as some hotspot blocks close to the processing chip (CPU), display chip (GPU) and memory (DDR) (as circled in the figure). In contrast, there is ample space to place DCAPs in empty blocks with low component placement density, but such blocks usually do not have a very high toggle rate.

In summary, the circuit layout efficiency of the prior art for voltage drop prevention is very poor, which also results in reduced performance and significantly increased costs.

Summary of the invention

In view of the fact that the traditional circuit design method does not consider the impact of the toggle rate on circuit planning, the present invention proposes a method for determining the reserved DCAP space based on the degree of the toggle rate, and analyzes the information through software to properly determine the DCAP space solution to achieve the purpose of reducing the dynamic voltage and realizing the optimization of the circuit configuration.

An embodiment of the present invention provides a method for generating a circuit layout using simulation software, comprising the following steps: (A). planning a plurality of blocks on a circuit board, wherein each of the blocks comprises: an operating space and a reserved space; (B). determining the size of the reserved space in the block according to at least one specific condition; (C). determining whether to adjust the size of the reserved space in the block determined in step (B) according to at least one judgment condition; and (D). generating the circuit layout according to the size of the reserved space in the block determined in step (B) when step (C) determines that no adjustment is required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a circuit layout for reserving DCAP space in the prior art.

FIG. 2 is a block diagram of a circuit layout for generating the present invention.

FIG. 3 is a block classification table generated according to the size of the two-state thixotropic rate of the block.

FIG. 4 is a schematic diagram of a circuit layout obtained by using the architecture shown in FIG. 2 .

FIG. 5 is a diagram illustrating a method for generating a circuit layout using simulation software according to an embodiment of the present invention.

Symbol Description

Steps 202-212, 502-508

FFG1～FFG8 Block Group

Cell(n)～Cell(n-31) Block

DCAP2～DCAP16 Reserved space for capacitor placement

Detailed ways

Please refer to FIG. 2, which is a block diagram of the circuit layout generated by the present invention. First, in step 202, the two-state tactile rate data of each block on the circuit board is provided (which can be summarized as a two-state tactile rate data table). Step 204 is to generate a preliminary block configuration plan based on the collected two-state tactile rate data and netlist information. At this time, multiple blocks will be planned on the circuit board, wherein each of the blocks includes an operation space for setting components and a DCAP reserved space. The access rate of each block can be obtained through the two-state tactile rate data table.

Regarding step 204, please refer to FIG. 3, which is a block classification table generated according to the size of the two-state thixotropic rate of the block, wherein the blocks cell(n), cell(n-1), cell(n-2), and cell(n-3) classified into the block group FFG1 have the highest two-state thixotropic rate, and are therefore set as DCAP16 (the larger the number matched to "DCAP", the more space will be reserved for placing capacitors). For example, the capacitor reserved space allocated to the block set as DCAP8 will be smaller than the capacitor reserved space allocated to the block set as DCAP16, and the capacitor reserved space allocated to the block set as DCAP4 will be smaller than the capacitor reserved space allocated to the block set as DCAP8, and so on. Please note that although capacitors are used as a solution to voltage degradation in the examples of the present invention, the present invention is not limited to this, and capacitors can also be replaced by other passive components as long as the same effect can be achieved.

The dotted line in the middle of FIG. 3 indicates that the current grouping only uses four block groups FFG1 to FFG4. When a finer grouping is required, the dotted line can be pulled down. For example, when the dotted line moves down one row, the block grouping becomes 5 groups. Considering that the total area of the reserved space does not account for too high a proportion of all blocks, how fine the grouping should be (i.e., the extent to which the dotted line should be pulled down) must be compromised. Please note that step 206 can further optimize the placement of components through software functions (such as sdc and floorplan) to generate candidate circuit layouts.

The above is to sort the blocks according to the binary tactile rates corresponding to the multiple blocks, wherein the reserved space allocated to the block is proportional to its binary tactile rate, that is, the block with a higher binary tactile rate may be allocated a larger DCAP block. In addition, the present invention may also consider whether the block is located at a hot spot (e.g., a location adjacent to a CPU, GPU, DDR, etc.) or adjacent to a hot spot, for example, considering the distance between each block and the hot spot.

In order to make full use of the extra circuit space for DCAP and not occupy important component placement space while taking into account DCAP, in step 208, the present invention can use "DCAP block does not occupy 1% to 3% (e.g., 2%) of all block areas" as a judgment condition. This is because if the reserved DCAP space is too large, the efficiency of the overall circuit will be affected. When it is determined that the reserved space exceeds the predetermined value (or predetermined percentage) of the total block area, the process must return to steps 204 and 206 to regenerate candidate circuit layouts.

Next, step 210 continues to further examine the candidate circuit layouts. If the determined DCAP space size of the corresponding block can make the overall dynamic IR drop reach the predetermined target, the current circuit layout is used as the output final layout. Step 212 generates a circuit layout, wherein the predetermined target can be a range that enables the circuit layout to work normally, etc., and the present invention is not limited thereto.

Please refer to FIG. 4 , which is a schematic diagram of a circuit layout obtained by using the architecture shown in FIG. 2 . Compared with FIG. 1 , the circled hotspot locations have sufficient DCAP blocks, and there are no unused large blocks in the overall layout.

Please refer to FIG. 5 , which is a method for generating a circuit layout using simulation software according to an embodiment of the present invention. Please note that if substantially the same result can be obtained, the steps do not necessarily have to be executed in the order shown in FIG. 5 . The method of FIG. 5 can be simply summarized as follows:

502: Plan a plurality of blocks on a circuit board, wherein each block includes: an operation space and a reserved space;

504: Determine the size of the reserved space in the block according to at least one specific condition;

506: Determine whether the size of the reserved space in the determined block needs to be modified according to at least one judgment condition. If so, the process returns to step 504; if not, the process proceeds to step 508;

508: Generate a circuit layout according to the determined size of the reserved space in the block.

Since those skilled in the art can easily understand the details of each step in FIG. 5 after reading the above paragraphs, further description will be omitted here for the sake of brevity.

In summary, by implementing the technical features of the present invention, the extra space on the circuit board can be properly utilized. In addition, since the present invention generates the corresponding circuit layout according to the two-state thixotropic rate data table through software, the generation speed is extremely fast and the space utilization is extremely accurate, without leaving large unusable blocks and sacrificing the placement of important circuit components.

The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims (9)

1. A method of generating a circuit layout using simulation software, comprising the steps of:

(A) Programming a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space;

(B) Determining the size of the reserved space in the block according to at least one specific condition;

(C) Determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one judging condition; and

(D) Generating the circuit layout according to the size of the reserved space in the block determined in the step (B) when the step (C) judges that the adjustment is not needed,

Wherein the at least one specific condition comprises: the at least one judgment condition comprises: whether the total reserved space in the block exceeds a preset value.

2. A method of generating a circuit layout using simulation software, comprising the steps of:

(A) Programming a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space;

(B) Determining the size of the reserved space in the block according to at least one specific condition;

(C) Determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one judging condition; and

(D) Generating the circuit layout according to the size of the reserved space in the block determined in the step (B) when the step (C) judges that the adjustment is not needed,

Wherein the at least one specific condition comprises: the at least one judgment condition comprises: whether the size of the reserved space in the block determined in the step (B) enables the overall dynamic voltage attenuation to reach a preset target or not.

3. A method of generating a circuit layout using simulation software, comprising the steps of:

(A) Programming a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space;

(B) Determining the size of the reserved space in the block according to at least one specific condition;

(C) Determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one judging condition; and

(D) Generating the circuit layout according to the size of the reserved space in the block determined in the step (B) when the step (C) judges that the adjustment is not needed,

Wherein the at least one specific condition further comprises: whether the blocks are located at the hot spot or the distance between each of the blocks and the hot spot, and the at least one judgment condition includes: whether the total reserved space in the block exceeds a preset value.

4. A method of generating a circuit layout using simulation software, comprising the steps of:

(A) Programming a plurality of blocks on a circuit board, wherein each block comprises: an operation space and a reserved space;

(B) Determining the size of the reserved space in the block according to at least one specific condition;

(C) Determining whether to adjust the size of the reserved space in the block determined in the step (B) according to at least one judging condition; and

(D) Generating the circuit layout according to the size of the reserved space in the block determined in the step (B) when the step (C) judges that the adjustment is not needed,

Wherein the at least one specific condition further comprises: whether the blocks are located at the hot spot or the distance between each of the blocks and the hot spot, and the at least one judgment condition includes: whether the size of the reserved space in the block determined in the step (B) enables the overall dynamic voltage attenuation to reach a preset target or not.

5. The method of any one of claims 1 to 4, wherein when step (C) determines that adjustment is required, step (a) is skipped.

6. The method of claim 1 or 2, wherein step (B) further comprises: the blocks are ordered according to the magnitude of the bi-state thixotropic rate corresponding to the block, wherein the reserved space to which a block is allocated is proportional to its bi-state thixotropic rate.

7. A method as claimed in claim 1 or 3, wherein the predetermined value is a predetermined percentage of the total area of the block, and the predetermined percentage is 1% to 3%.

8. The method of claim 2 or 4, wherein the predetermined goal is that the circuit layout is capable of maintaining a state of normal operation.

9. The method of any one of claims 1 to 4, wherein a headspace in the block is used to set a capacitance.