CN111933689B

CN111933689B - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN111933689B
Application number: CN202011001446.8A
Authority: CN
Inventors: 宋富冉; 周儒领; 蔡君正; 许宗能
Original assignee: Jingxincheng Beijing Technology Co Ltd
Current assignee: Jingxincheng Beijing Technology Co Ltd
Priority date: 2020-09-22
Filing date: 2020-09-22
Publication date: 2021-02-19
Anticipated expiration: 2040-09-22
Also published as: CN111933689A

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein the substrate comprises a pad oxide layer and a pad nitride layer; forming a plurality of trenches in the substrate; forming a filling layer in the groove, wherein the filling layer covers the pad nitride layer; carrying out planarization treatment on the filling layer to expose the pad nitride layer; removing part of the filling layer and the pad nitride layer through wet etching to form a plurality of shallow trench isolation structures, wherein the substrate is isolated into a plurality of active areas by the shallow trench isolation structures, and a concave structure is arranged in an area, close to the active areas, of the tops of the shallow trench isolation structures; forming a polycrystalline silicon layer on the substrate to form a polycrystalline silicon side wall in the concave structure; and removing the pad oxide layer to expose the substrate, and placing the substrate in a furnace body to oxidize the polycrystalline silicon side wall and the exposed substrate. The semiconductor structure provided by the invention can avoid electric leakage.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for manufacturing the same.

Background

In current submicron processes, shallow trench isolation techniques are commonly applied. Shallow trench isolation techniques significantly reduce the area of the isolation region, providing minimal active area encroachment and a flatter surface. However, due to local stress concentration, it is easy to over-etch the filled oxide layer at the corner edge of the interface of the sti structure (i.e., the SiO2 close to the active region of silicon) to form a recess, which is commonly referred to as "Divot". This "Divot" phenomenon causes the polysilicon forming the gate to fill the Divot region when the transistor gate crosses over the sti structure and the active region, creating a parasitic device there. Since the turn-on voltage of this parasitic transistor is much lower than the turn-on voltage of the normal transistor originally designed, additional leakage occurs during normal transistor operation.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides a method for manufacturing a semiconductor structure, so as to solve the problem of a recess in a shallow trench isolation structure and avoid the occurrence of a leakage phenomenon in the semiconductor structure.

To achieve the above and other objects, the present invention provides a method for manufacturing a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a pad oxide layer and a pad nitride layer;

forming a plurality of trenches in the substrate;

forming a filling layer in the groove, wherein the filling layer covers the pad nitride layer;

carrying out planarization treatment on the filling layer to expose the pad nitride layer;

removing part of the filling layer and the pad nitride layer through wet etching to form a plurality of shallow trench isolation structures, wherein the substrate is isolated into a plurality of active areas by the shallow trench isolation structures, and a concave structure is arranged in an area, close to the active areas, of the tops of the shallow trench isolation structures;

forming a polycrystalline silicon layer on the substrate to form a polycrystalline silicon side wall in the concave structure, wherein the polycrystalline silicon side wall covers the concave structure;

removing the pad oxide layer to expose the substrate, and placing the substrate in a furnace body to oxidize the polycrystalline silicon side wall and the exposed substrate;

and the thickness of the polysilicon side wall is smaller than the depth of the exposed substrate which is oxidized.

Further, the trench is formed by a dry etching process, the trench extending from the pad nitride layer into the substrate.

Further, the step of forming the filling layer includes:

placing the substrate within a chamber;

and introducing a silicon-containing precursor and an oxygen-containing precursor into the cavity, and heating the cavity to form the filling layer.

Further, the filling layer is subjected to planarization treatment through a chemical mechanical polishing process.

Further, a part of the filling layer and the pad nitride layer is removed by a hydrofluoric acid solution.

Further, the step of forming a polysilicon layer on the substrate to form a polysilicon sidewall in the recess structure includes:

forming the polycrystalline silicon layer on the substrate through a chemical vapor deposition process, wherein the polycrystalline silicon layer covers the active region and the shallow trench isolation structure;

and removing the polycrystalline silicon layer on the active region and at the top of the shallow trench isolation structure by a dry etching process, and reserving the polycrystalline silicon layer in the recessed structure to form the polycrystalline silicon side wall.

Furthermore, the dry etching process takes the pad oxide layer as an etching stop layer.

Further, after the exposed substrate is oxidized, a gate oxide layer is formed.

Further, a part of the filling layer is arranged between the concave structure and the active region.

Further, the present invention provides a semiconductor structure, including:

a substrate;

the shallow trench isolation structures are positioned in the substrate and isolate a plurality of active regions in the substrate;

and the grid oxide layer is positioned on the active region.

In summary, the present invention provides a semiconductor structure and a method for manufacturing the same, wherein when a shallow trench isolation structure is manufactured, a recess structure is formed in a region of the shallow trench isolation structure close to an active region in a wet etching process, and a polysilicon sidewall is formed in the recess structure, so that when a substrate is oxidized, the polysilicon sidewall is oxidized into an oxide, and thus the recess structure can be covered, that is, the recess structure is filled; therefore, when the substrate is again deposited with polysilicon to form the grid electrode, the polysilicon forming the grid electrode can not be filled in the concave structure, and the phenomenon of electric leakage of the semiconductor structure can be avoided. Meanwhile, the shallow trench isolation structure formed by the method has a good isolation effect.

Drawings

FIG. 1: the method for fabricating a semiconductor structure according to the present embodiment is a flowchart.

FIG. 2: the structure diagram corresponding to step S1.

FIG. 3: structure of photoresist.

FIG. 4: the structure diagram corresponding to step S2.

FIG. 5: the structure diagram corresponding to step S3.

FIG. 6: the structure diagram corresponding to step S4.

FIG. 7: removing the structure of the pad oxide layer.

FIG. 8: the structure diagram corresponding to step S5.

FIG. 9: the structure diagram corresponding to step S6.

FIG. 10: and forming a structure diagram of the polysilicon side wall.

FIG. 11: removing the structure of the pad oxide layer.

FIG. 12: the structure diagram corresponding to step S7.

Description of the symbols

101: substrate, 102: pad oxide layer, 103: pad nitride layer, 103 a: patterned photoresist layer, 103 b: opening, 104: groove, 105: filling layer, 106: shallow trench isolation structure, 107: recessed structure, 108: polysilicon layer, 109: polysilicon side wall, 110: oxide layer, 111: gate oxide layer, AA: an active region.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 1, the present embodiment provides a method for manufacturing a semiconductor structure, including:

s1: providing a substrate, wherein the substrate comprises a pad oxide layer and a pad nitride layer;

s2: forming a plurality of trenches in the substrate;

s3: forming a filling layer in the groove, wherein the filling layer covers the pad nitride layer;

s4: carrying out planarization treatment on the filling layer to expose the pad nitride layer;

s5: removing part of the filling layer and the pad nitride layer through wet etching to form a plurality of shallow trench isolation structures, wherein the substrate is isolated into a plurality of active areas by the shallow trench isolation structures, and a concave structure is arranged in an area, close to the active areas, of the tops of the shallow trench isolation structures;

s6: forming a polycrystalline silicon layer on the substrate to form a polycrystalline silicon side wall in the concave structure;

s7: removing the pad oxide layer to expose the substrate, and placing the substrate in a furnace body to oxidize the polycrystalline silicon side wall and the exposed substrate; and the thickness of the polysilicon side wall is smaller than the depth of the exposed substrate which is oxidized.

As shown in fig. 2, in step S1, a substrate 101 is first provided to provide a platform for subsequent processes, where the material of the substrate 101 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, and the substrate 101 further includes a multilayer structure or the like of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), germanium-on-insulator (GeOI), or the like.

As shown in fig. 2, in the present embodiment, the surface of the substrate 101 is first cleaned to remove the impurity particles or other contaminants on the surface of the substrate 101. Then, a pad oxide layer 102 is formed on the substrate 101, and the method for forming the pad oxide layer 102 may be one of high temperature furnace oxidation, rapid thermal oxidation, and in-situ steam generation oxidation. The thickness of the pad oxide layer 102 may be 500-1000 angstroms. The pad oxide layer 102 can serve as a protective layer for the substrate 101, and the substrate 101 covered by the pad oxide layer can be protected in the subsequent process, so that the substrate 101 is prevented from being unnecessarily damaged. The material of the pad oxide layer 102 may be silicon dioxide.

As shown in fig. 2, after forming the pad oxide layer 102, a pad nitride layer 103 is formed on the pad oxide layer 102. The material of the pad nitride layer 103 may be silicon nitride, oxynitride or metal nitride. The pad nitride layer 103 may be formed by one of low pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, or high density plasma chemical vapor deposition. The pad nitride layer 103 also acts as a stop layer for the cmp planarization of the dielectric material filled in the trench.

As shown in fig. 3 to 4, in step S2, a photoresist is first coated on the pad nitride layer 103, and the coated photoresist is patterned by a photolithography process such as exposure and development to form a patterned photoresist layer 103a, wherein the patterned photoresist layer 103a has an opening 103b for defining a trench 104 to be formed in the substrate 101.

As shown in fig. 4-5, in the present embodiment, the position of the trench 104 is defined by the opening 103b, i.e., the pad nitride layer 103, the pad oxide layer 102 and a portion of the substrate 101 below the opening 103b are etched down through the opening 103b, i.e., the portions of the substrate 101, are sequentially removed, so as to form a plurality of trenches 104 in the substrate 101. In this embodiment, the pad nitride layer 103, the pad oxide layer 102 and a portion of the substrate 101 may be sequentially removed by dry etching, that is, the pad nitride layer 103 and the pad oxide layer 102 are sequentially etched using the patterned photoresist layer 103a as a mask layer, then the patterned photoresist layer 103a is removed, and then the substrate 101 is etched using the pad nitride layer 103 and the pad oxide layer 102 as a mask layer. As can be seen in fig. 4, a plurality of trenches 104 are formed in the substrate 101, two trenches 104 being shown in fig. 4. The trench 104 extends from the pad nitride layer 103 into the substrate 101. The trench 104 has an inverted trapezoid shape with a wide top and a narrow bottom, i.e., the width of the top of the trench 104 is greater than the width of the bottom of the trench 104. Of course, in some embodiments, the shape of the channel 104 may also be U-shaped.

As shown in fig. 3 to fig. 4, in this embodiment, the method for forming the trench 104 may be a plasma dry etching, where an etching gas used in the plasma dry etching is to make the sidewall of the trench 104 smooth, have fewer lattice defects, and make the bottom corner of the trench 104 smooth, and the etching gas is to make the sidewall of the trench 104 have a more inclined profile. In this embodiment, the substrate 101 is placed in a reaction chamber to perform an etching operation. The process conditions in the reaction chamber may be as follows: the reaction chamber pressure is between 5mTorr and 30mTorr (e.g., 10mTorr, 15mTorr, 25mTorr, etc.); the RF source power is 400W-1000W (such as 500W, 600W, 750W, 800W, 900W, etc.), the RF bias power is 600W-1200W (such as 700W, 750W, 800W, 900W, 1000W), etc., the etching gas comprises CF4 and inert gas (such as He and/or Ar), the flow rate of CF4 is 20 sccm-60 sccm (such as 30sccm, 40sccm, 50sccm, etc.), the flow rate of the inert gas is 100 sccm-300 sccm (such as 120sccm, 150sccm, 200sccm, etc.), and the etching time is 5 s-10 s. Note that the vertical arrows in fig. 3 indicate the etching direction.

As shown in fig. 5, in step S3, after the trench 104 is formed, the filling layer 105 may be formed in the trench 104 by a plasma enhanced chemical vapor deposition process. The filling layer 105 covers the bottom and sidewalls of the trench 104, and the filling layer 105 covers the pad nitride layer 103. In this embodiment, for example, the substrate 101 is placed in a chamber, then a silicon-containing precursor and an oxygen-containing precursor are introduced into the chamber, and then heating is performed to make the silicon-containing precursor and the oxygen-containing precursor form plasma, and then a reaction is performed to form the filling layer 105 in the trench 104. In this embodiment, the silicon-containing precursor may be tetraethyl orthosilicate, the oxygen-containing precursor may be ozone, and the flow ratio of the oxygen-containing precursor to the silicon-containing precursor may be greater than 20: 1. of course, in some embodiments, the sidewalls and the top corners of the trench 104 may be first thermally oxidized to form thermally oxidized sidewalls and thermally oxidized rounded top corners in the trench 104 to improve the isolation performance, and then the filling layer 105 may be formed on the trench 104 and the pad nitride layer 103 by a plasma enhanced chemical vapor deposition process. The material of the filling layer 105 may include silicon dioxide, silicon nitride, silicon oxynitride, and the like. In some embodiments, the filling layer 105 may also be referred to as an isolation dielectric layer or an isolation oxide layer.

As shown in fig. 6, in step S4, the filling layer 105 is formed on the pad nitride layer 103, so that the filling layer 105 on the pad nitride layer 103 can be removed by a chemical mechanical polishing process, i.e., the filling layer 105 is planarized. In this embodiment, the pad nitride layer 103 is used as a polishing stop layer during the planarization process. For example, the substrate 101 is placed on a polishing head such that the substrate 101 is in contact with a polishing pad, and then the filling layer 105 on the substrate 101 is polished to expose the pad nitride layer 103.

As shown in fig. 6 to 7, in step S5, after the planarization process, a portion of the filling layer 105 is first removed by wet etching, and then the pad nitride layer 103 is removed by wet etching. In this embodiment, the filling layer 105 on the top of the trench is removed by diluted hydrofluoric acid, for example, and then the pad nitride layer 103 is removed by diluted hydrofluoric acid. In the present embodiment, after the pad nitride layer 103 is removed, the pad oxide layer 102 is exposed. Since the wet etching removes only a part of the height of the filling layer 105, the height of the filling layer 105 after etching protrudes from the pad oxide layer 102, so that a step is formed on the top of the filling layer 105 and the upper surface of the pad oxide layer 102. In this embodiment, by controlling the time of the wet etching, the height of the step can be controlled.

As shown in fig. 8, in the present embodiment, after removing the pad nitride layer 103, a shallow trench isolation structure 106 is formed, for example, two shallow trench isolation structures 106 are shown. Of course, more shallow trench isolation structures 106 may be shown. Because the filling layer 105 in the shallow trench isolation structure 106 is made of an insulating material, the shallow trench isolation structure 106 separates a plurality of active areas AA in the substrate 101, and an area between two adjacent shallow trench isolation structures 106 is the active area AA. One active area AA is shown in fig. 8. It should be noted that when the pad nitride layer 103 is removed by wet etching, due to over-etching, a recess structure 107 is formed on the top of the shallow trench isolation structure 106 near the active area AA, and the depth of the recess structure 107 is, for example, 20-30 angstroms. A thinner fill layer 105 remains between the recessed structure 107 and the active area AA. Meanwhile, due to the existence of the recess structure 107, if polysilicon is formed in the recess structure 107, the device may leak, and therefore, an insulating material needs to be filled in the recess structure 107 in a subsequent step to prevent the leakage.

As shown in fig. 9, in step S6, a polysilicon layer 108 is first formed on a substrate 101 by a chemical vapor deposition process, the polysilicon layer 108 being located on a pad oxide layer 102; that is, polysilicon layer 108 is located on active area AA and also located on shallow trench isolation structure 106, and polysilicon layer 108 is also located in recessed structure 107. Polysilicon layer 108 has a thickness of, for example, 40-100 angstroms, such as 50 angstroms. As can be seen in fig. 9, the polysilicon layer 108 fills or substantially fills the recess 107.

As shown in fig. 9, in the present embodiment, a polysilicon layer 108 may be formed on the pad nitride layer 102, for example, by a low pressure chemical vapor deposition process. The process parameters of the low-pressure chemical vapor deposition process can be as follows: the temperature of the reaction chamber ranges from 600 ℃ to 650 ℃, the pressure of the reaction chamber ranges from 250 ℃ to 300mtorr, and the flow rate of silane ranges from 150 ℃ to 170 sccm. The polysilicon layer 108 deposited by the low pressure chemical vapor deposition process has small grains and a dense structure. Of course, in some embodiments, the polysilicon layer 108 may also be formed by an atmospheric pressure chemical vapor deposition process, but the structure of the polysilicon layer 108 formed by the atmospheric pressure chemical vapor deposition process is not compact enough, the oxygen content in the polysilicon layer 108 is high, and a certain oxidation interlayer exists, which is beneficial to the oxidation of the polysilicon layer 108.

As shown in fig. 9-10, after the polysilicon layer 108 is formed, the polysilicon layer 108 on the active area AA and the polysilicon layer 108 on the shallow trench isolation structure 106 may be removed by dry etching, and the polysilicon layer 108 of the recess structure 107 remains, after the etching, the polysilicon layer 108 in the recess structure 107 becomes a polysilicon sidewall 109, the polysilicon sidewall 109 is also located in the recess structure 107, and the polysilicon sidewall 109 substantially fills the recess structure 107. In the present embodiment, after the dry etching, the top of the pad oxide layer 102 and the shallow trench isolation structure 106 are exposed.

In some embodiments, silicon dioxide is also used in place of the polysilicon layer, and then etching is performed to leave only the silicon dioxide within the recessed structures 107, but during the etching, it is also possible for the recessed structures 107 to reappear.

As shown in fig. 10, in some embodiments, an insulating material may also be deposited directly within the recessed structure 107, thereby filling the recessed structure 107, for example, depositing silicon dioxide. However, direct deposition of silicon dioxide requires one more masking process, which increases the cost.

As shown in fig. 11 to 12, in step S7, the pad oxide layer 102 is first removed by wet etching to expose the surface of the substrate 101, i.e., to expose the active area AA. In the present embodiment, the pad oxide layer 102 is removed, for example, by diluted hydrofluoric acid, to expose the active area AA. Then, the substrate 101 is placed in a furnace body for oxidation, and since the active area AA and the polysilicon side wall 109 are made of silicon, the surface of the active area AA is oxidized into a gate oxide layer 111, and the polysilicon side wall 109 is oxidized into an oxide layer 110.

As shown in fig. 12, in the present embodiment, the polysilicon sidewall spacers 109 are oxidized to form an oxide layer 110, i.e., oxidized to form silicon dioxide, so that the oxide layer 110 has an insulating effect, and the oxide layer 110 fills the recess structure 107, so that when a polysilicon material is deposited, the polysilicon material cannot be deposited in the recess structure 107, thereby preventing the occurrence of a leakage phenomenon.

As shown in fig. 12, in the present embodiment, after the active area AA is exposed, the gate oxide layer 111 is formed by oxidation, and the gate oxide layer 111 may contact the oxide layer 110 due to the effect of volume expansion. It should be noted that the thickness of the polysilicon sidewall 109 may be smaller than the depth of the oxidized active region AA, so as to avoid the leakage phenomenon. If the thickness of the polysilicon sidewall 109 is greater than the depth of the oxidized active region AA, a portion of the polysilicon sidewall 109 cannot be oxidized, that is, a portion of the polysilicon sidewall 109 is still located in the recess structure 107. If the polysilicon material is formed again, the polysilicon remaining in the recess 107 may be shorted with the polysilicon material, resulting in leakage.

As shown in fig. 12, the present embodiment provides a semiconductor structure, including: the substrate 101, a plurality of shallow trench isolation structures 106, the shallow trench isolation structures 106 being located in the substrate 101, the shallow trench isolation structures 106 being separated into a plurality of active areas AA within the substrate 101, for example, two shallow trench isolation structures 106 and one active area AA are shown in the figure. There is also a gate oxide layer 111 on the substrate 101, and the gate oxide layer 111 is located on the active area AA.

As shown in fig. 12, the shallow trench isolation structure 106 further has an oxide layer 110 on the top thereof near the active area AA, and the oxide layer 110 is formed by polysilicon oxidation. The oxide layer 110 is in contact with the gate oxide layer 111, and the shallow trench isolation structure 106 protrudes from the gate oxide layer 111.

As shown in fig. 12, in some embodiments, a polysilicon layer may also be formed on the gate oxide layer 111, through which a gate structure may be formed.

As shown in fig. 12, in the present embodiment, the semiconductor structure can be used for manufacturing a semiconductor device, which can be applied to various Integrated Circuits (ICs). The IC according to the present invention is, for example, a memory circuit such as a Random Access Memory (RAM), a dynamic RAM (dram), a synchronous dram (sdram), a static RAM (sram), or a Read Only Memory (ROM), etc. An IC according to the present invention may also be a logic device such as a Programmable Logic Array (PLA), an Application Specific Integrated Circuit (ASIC), a merged DRAM logic integrated circuit (buried DRAM), a radio frequency circuit, or any other circuit device. The IC chip according to the present invention can be used in, for example, consumer electronic products such as personal computers, portable computers, game machines, cellular phones, personal digital assistants, video cameras, digital cameras, cellular phones, and various electronic products such as radio frequency products.

In summary, the present invention provides a semiconductor structure and a method for manufacturing the same, wherein when a shallow trench isolation structure is manufactured, a recess structure is formed in a region of the shallow trench isolation structure close to an active region in a wet etching process, and a polysilicon sidewall is formed in the recess structure, so that when a substrate is oxidized, the polysilicon sidewall is oxidized into an oxide, and thus the recess structure can be covered, that is, the recess structure is filled; therefore, when the grid is formed again on the substrate, the polycrystalline silicon forming the grid cannot be filled in the concave structure, and therefore the phenomenon of electric leakage of the semiconductor structure can be avoided. Meanwhile, the shallow trench isolation structure formed by the method has a good isolation effect.

Reference throughout this specification to "one embodiment", "an embodiment", or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily all embodiments, of the present invention. Thus, respective appearances of the phrases "in one embodiment", "in an embodiment", or "in a specific embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It is to be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the present invention.

It will also be appreciated that one or more of the elements shown in the figures can also be implemented in a more separated or integrated manner, or even removed for inoperability in some circumstances or provided for usefulness in accordance with a particular application.

Additionally, any reference arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise expressly specified. Further, as used herein, the term "or" is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.

As used in the description herein and throughout the claims that follow, "a", "an", and "the" include plural references unless otherwise indicated. Also, as used in the description herein and throughout the claims that follow, unless otherwise indicated, the meaning of "in …" includes "in …" and "on … (on)".

The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.

The systems and methods have been described herein in general terms as the details aid in understanding the invention. Furthermore, various specific details have been given to provide a general understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

Thus, although the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Thus, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.

The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, comprising:

A substrate is provided, which includes a pad oxide layer and a pad nitride layer;

forming a plurality of trenches in the substrate;

forming a filling layer in the trench, and the filling layer covers the pad nitride layer;

performing a planarization process on the filling layer to expose the pad nitride layer;

Parts of the filling layer and the pad nitride layer are removed by wet etching to form a plurality of shallow trench isolation structures that isolate the substrate into a plurality of active regions, A region of the top of the shallow trench isolation structure close to the active region has a recessed structure;

forming a polysilicon layer on the substrate to form a polysilicon spacer in the recessed structure, the polysilicon spacer covering the recessed structure;

removing the pad oxide layer to expose the substrate and placing the substrate in a furnace to oxidize the polysilicon spacers and the exposed substrate;

Wherein, the thickness of the polysilicon spacer is less than the exposed depth of the substrate being oxidized;

Wherein, after the exposed substrate is oxidized, a gate oxide layer is formed;

Wherein, the polysilicon spacer is oxidized into an oxide layer, and the gate oxide layer contacts the oxide layer;

Wherein, the polysilicon layer includes an oxide interlayer.

2 . The manufacturing method of claim 1 , wherein the trenches are formed by a dry etching process, and the trenches extend from the pad nitride layer into the substrate. 3 .

3. The manufacturing method according to claim 1, wherein the step of forming the filling layer comprises:

placing the substrate in the cavity;

The silicon-containing precursor and the oxygen-containing precursor are passed into the cavity, and the cavity is heated to form the filling layer.

4 . The manufacturing method according to claim 1 , wherein the filling layer is planarized by a chemical mechanical polishing process. 5 .

5 . The manufacturing method of claim 1 , wherein part of the filling layer and the pad nitride layer are removed by a hydrofluoric acid solution. 6 .

6 . The manufacturing method of claim 1 , wherein the step of forming a polysilicon layer on the substrate to form polysilicon spacers in the recessed structure comprises: 6 .

forming the polysilicon layer on the substrate by a chemical vapor deposition process, the polysilicon layer covering the active region and the shallow trench isolation structure;

The polysilicon layer located on the active region and the top of the shallow trench isolation structure is removed by a dry etching process, and the polysilicon layer located in the recessed structure remains, so as to form the polysilicon spacers .

7 . The manufacturing method according to claim 6 , wherein, in the dry etching process, the pad oxide layer is used as an etching stop layer. 8 .

8 . The manufacturing method according to claim 1 , wherein a part of the filling layer is further provided between the recessed structure and the active region. 9 .

9. The semiconductor structure formed by the manufacturing method according to any one of claims 1-8, characterized in that, comprising:

substrate;

a plurality of shallow trench isolation structures located in the substrate, the plurality of shallow trench isolation structures isolating a plurality of active regions in the substrate;

A gate oxide layer is located on the active region.