CN111933648A - Array substrate, preparation method thereof and display device - Google Patents

Abstract

The present disclosure provides an array substrate, comprising: a base substrate, a polysilicon thin film transistor and an amorphous silicon thin film transistor located on the same side of the base substrate, the base substrate is divided into a display area and a peripheral area of the display area. a peripheral area, the polysilicon thin film transistor is located in the peripheral area, and the amorphous silicon thin film transistor is located in the display area; the polysilicon thin film transistor includes: a polysilicon semiconductor pattern and a polysilicon semiconductor pattern located on the side away from the substrate substrate The amorphous silicon thin film transistor is a bottom gate type thin film transistor, including: an amorphous silicon semiconductor pattern and a second gate located on the side of the polysilicon semiconductor pattern close to the base substrate; the The first gate and the second gate are arranged in the same layer. The present disclosure also provides a preparation method of an array substrate and a display device.

Description

Array substrate, preparation method thereof, and display device

technical field

The present invention relates to the field of display, in particular to an array substrate, a preparation method thereof and a display device.

Background technique

Low Temperature Poly-Silicon (LTPS) products are the mainstream products in the display field currently on the market, which is attributed to the advantages of LTPS due to its high mobility, high driving, and miniaturization of TFT size. However, there is a problem that the off-state leakage current Ioff is relatively high when using an LTPS thin film transistor (Thin Film Transistor, TFT for short). When the LTPS thin film transistor is applied to the display area of the display panel, the off-state leakage current Ioff is too large, resulting in high power consumption of the product.

In order to solve the problem that the off-state leakage current Ioff is too large, a dual-gate LTPS thin film transistor (Thin Film Transistor, TFT for short) is proposed in the related art to reduce the leakage current Ioff. However, with the improvement of the resolution of the display panel, the size of each pixel unit in the display panel is correspondingly reduced, and at this time, the size of the TFT in the pixel unit needs to be correspondingly reduced. The double-gate LTPS design will cause the overall size of the TFT to be too large, which cannot meet the TFT size requirements of high-resolution products.

It can be seen that neither the single-gate LTPS thin film transistor nor the double-gate LTPS thin film transistor is suitable for the pixel design of the display area of the high-resolution display product.

SUMMARY OF THE INVENTION

The present invention aims to solve at least one of the technical problems existing in the prior art, and provides an array substrate, a preparation method thereof, and a display device.

In a first aspect, an embodiment of the present disclosure provides an array substrate, comprising: a base substrate, a polysilicon thin film transistor and an amorphous silicon thin film transistor located on the same side of the base substrate, the base substrate is divided into a display area and a a peripheral area around the display area, the polysilicon thin film transistor is located in the peripheral area, and the amorphous silicon thin film transistor is located in the display area;

The polysilicon thin film transistor includes: a polysilicon semiconductor pattern and a first gate located on a side of the polysilicon semiconductor pattern away from the base substrate;

The amorphous silicon thin film transistor is a bottom gate type thin film transistor, comprising: an amorphous silicon semiconductor pattern and a second gate located on the side of the polysilicon semiconductor pattern close to the base substrate;

The first gate and the second gate are disposed in the same layer.

In some embodiments, the polysilicon thin film transistor further comprises: a first source electrode and a first drain electrode located on a side of the first gate electrode away from the base substrate, the first source electrode and the first drain electrode a drain is electrically connected to the polysilicon semiconductor pattern;

The amorphous silicon thin film transistor further comprises: a second source electrode and a second drain electrode located on the side of the amorphous silicon semiconductor pattern away from the base substrate, the second source electrode and the second drain electrode are all electrically connected with the amorphous silicon semiconductor pattern;

The first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged in the same layer.

In some embodiments, corresponding ohmic contact patterns are provided between the second source electrode and the amorphous silicon semiconductor pattern, and between the second drain electrode and the amorphous silicon semiconductor pattern;

Corresponding etching barrier patterns are arranged between the second source electrode and the corresponding ohmic contact pattern, and between the second drain electrode and the corresponding ohmic contact pattern, and the material of the etching barrier pattern includes metal materials .

In some embodiments, the orthographic projection of the etch stop pattern on the base substrate and the orthographic projection of the corresponding ohmic contact pattern on the base substrate completely overlap.

In some embodiments, the material of the etch stop pattern includes molybdenum.

In a second aspect, an embodiment of the present disclosure further provides a display device, including: the array substrate provided in the above-mentioned first aspect.

In a second aspect, an embodiment of the present disclosure further provides a method for preparing an array substrate, including:

providing a base substrate, the base substrate is divided into a display area and a peripheral area located around the display area;

A polysilicon thin film transistor and an amorphous silicon thin film transistor are formed on the base substrate, the polysilicon thin film transistor is located in the peripheral area, the amorphous silicon thin film transistor is located in the display area, and the polysilicon thin film transistor includes: polysilicon A semiconductor pattern and a first gate located on the side of the polysilicon semiconductor pattern away from the substrate, the amorphous silicon thin film transistor is a bottom gate thin film transistor, including: an amorphous silicon semiconductor pattern and a first gate located close to the polysilicon semiconductor pattern The second gate on one side of the base substrate, the first gate and the second gate are arranged in the same layer.

In some embodiments, the step of forming a polysilicon thin film transistor and an amorphous silicon thin film transistor on the base substrate includes:

A polysilicon semiconductor pattern is formed on one side of the base substrate, and the polysilicon semiconductor pattern is located in the peripheral region;

forming a first gate insulating layer on the side of the polysilicon semiconductor pattern away from the base substrate;

The first gate and the second gate are formed on a side of the first gate insulating layer away from the base substrate, the first gate is located in the peripheral region, and the second gate in said display area;

forming a second gate insulating layer on a side of the first gate and the second gate away from the base substrate;

An amorphous silicon semiconductor pattern is formed on a side of the second gate insulating layer away from the base substrate, and the amorphous silicon semiconductor pattern is located in the display area;

forming an interlayer dielectric layer on the side of the amorphous silicon semiconductor pattern away from the base substrate;

A first source electrode, a first drain electrode, a second source electrode and a second drain electrode are formed on the side of the interlayer dielectric layer away from the base substrate, and the first source electrode and the first drain electrode are located at the The peripheral region is electrically connected to the polysilicon semiconductor pattern, the second source electrode and the second drain electrode are located in the display region and are electrically connected to the amorphous silicon semiconductor pattern.

In some embodiments, corresponding ohmic contact patterns are provided between the second source electrode and the amorphous silicon semiconductor pattern and between the second drain electrode and the amorphous silicon semiconductor pattern; the Corresponding etching barrier patterns are provided between the second source electrode and the corresponding ohmic contact pattern, and between the second drain electrode and the corresponding ohmic contact pattern, and the material of the etching barrier pattern includes metal materials;

The step of forming an amorphous silicon semiconductor pattern on the side of the second gate insulating layer away from the base substrate includes:

Forming an amorphous silicon semiconductor material film, an ohmic contact material film and an etching barrier material film in sequence on the side of the second gate insulating layer away from the base substrate;

A photoresist film layer is coated on the side of the etch stop material film away from the base substrate, and the photoresist film layer is processed by a halftone mask process. The part located outside the area where the amorphous silicon semiconductor pattern is to be formed is completely removed, the part of the photoresist film layer located in the area where the ohmic contact pattern is to be formed is completely retained, and the photoresist film layer is located in the area where the ohmic contact pattern is to be formed. Part of the channel region of the amorphous silicon semiconductor pattern remains;

The etching barrier material film, the ohmic contact material film and the amorphous silicon semiconductor material film are etched, and the etching barrier material film, the ohmic contact material film and the amorphous silicon semiconductor material film are located in the The part below the photoresist film layer is retained to obtain the preliminary pattern of the etching barrier pattern, the preliminary pattern of the ohmic contact pattern and the final pattern of the amorphous silicon semiconductor pattern;

Ashing is performed on the photoresist film layer, the photoresist film layer is located in the part of the area where the ohmic contact pattern is to be formed, and the photoresist film layer is located in the amorphous silicon semiconductor to be formed. Part of the channel region of the pattern is completely removed;

The preliminary pattern of the etching barrier pattern and the preliminary pattern of the ohmic contact pattern are etched, and the portion of the preliminary pattern of the etching barrier pattern and the preliminary pattern of the ohmic contact pattern located in the channel region of the amorphous silicon semiconductor pattern is completely removed, The final pattern of the etching barrier pattern and the final pattern of the ohmic contact pattern are obtained.

In some embodiments, the step of forming an interlayer dielectric layer on a side of the amorphous silicon semiconductor pattern away from the base substrate includes:

forming an interlayer dielectric material film on the side of the amorphous silicon semiconductor pattern away from the base substrate;

A first via hole connected to the polysilicon semiconductor pattern is formed by dry etching, and a second via hole connected to the etch stop pattern is formed.

Description of drawings

FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure;

FIG. 2 is a schematic cross-sectional view of another array substrate according to an embodiment of the present disclosure;

3 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present disclosure;

FIG. 4 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present disclosure;

5a-5f are schematic cross-sectional views of the intermediate structure of the array substrate prepared by the preparation method shown in FIG. 1;

FIG. 6 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present disclosure;

FIGS. 7 a to 7 e are schematic cross-sectional views illustrating the preparation of amorphous silicon semiconductor patterns, ohmic contact patterns, and etching barrier patterns according to embodiments of the disclosure.

Detailed ways

In order for those skilled in the art to better understand the technical solutions of the present invention, an array substrate, a preparation method thereof, and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic cross-sectional view of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 1 , the array substrate includes: a base substrate 11 , and polysilicon thin film transistors 1 and amorphous silicon located on the same side of the base substrate 11 . For the thin film transistor 2, the base substrate 11 is divided into a display area and a peripheral area around the display area, the polysilicon thin film transistor 1 is located in the peripheral area, and the amorphous silicon thin film transistor 2 is located in the display area. Among them, the polysilicon thin film transistor 1 includes: a polysilicon semiconductor pattern 3 and a first gate 4 located on the side of the polysilicon semiconductor pattern 3 away from the substrate 11; the amorphous silicon thin film transistor 2 is a bottom gate type thin film transistor, including: amorphous silicon The semiconductor pattern 5 and the second gate 6 located on the side of the polysilicon semiconductor pattern 3 close to the base substrate 11 ; the first gate 4 and the second gate 6 are arranged in the same layer.

It should be noted that, in the embodiments of the present disclosure, two structures or more structures are "disposed on the same layer" specifically means that the two structures or more structures can be prepared based on the same material film, and the different structures disposed on the same layer are different from The distances between the base substrates 11 may or may not be equal.

A first gate insulating layer 12 is arranged between the first gate 4 and the polysilicon semiconductor pattern 3 to insulate between the first gate 4 and the polysilicon semiconductor pattern 3; the second gate 6 is arranged between the polysilicon semiconductor pattern 3 There is a first gate insulating layer 12 so that a second insulating layer 13 is formed between the second gate electrode 6 and the polysilicon semiconductor pattern 3 .

Among them, a plurality of pixel units arranged in an array are arranged in the display area, each pixel unit is provided with a pixel circuit, and the pixel circuit is generally composed of a thin film transistor and a capacitor. limited. In the accompanying drawings, only one thin film transistor located in the display area and one thin film transistor located in the peripheral area are exemplarily drawn, which are only for illustrative purposes and do not limit the technical solutions of the present disclosure.

In the embodiment of the present disclosure, on the one hand, the polysilicon thin film transistor 1 with relatively high electron mobility (electron mobility is about 30cm ² /Vs) is arranged in the peripheral area of the array substrate; for example, it is applied to the gate driving circuit ( Gatedriver On Array, referred to as GOA circuit), multiplexing circuit (also known as MUX circuit), can meet the high requirements for the electron mobility of components in the peripheral area of the display panel. On the other hand, in the display area of the display panel, the pixel unit has lower requirements on the electron mobility of the thin film transistor, and the electron mobility of the amorphous silicon thin film transistor 2 (generally, the electron mobility is about 10 cm ² /Vs) can satisfy corresponding requirements.

The off-state leakage current Ioff of the single-gate amorphous silicon thin film transistor 2 is relatively small, which can meet the leakage current requirements of the pixel unit for the thin film transistor. The amorphous thin film transistor is designed as a bottom gate thin film transistor, which can not only meet the small leakage current requirements of pixel units for thin film transistors, but also meet the small size requirements of pixel units of high resolution products for thin film transistors; In the amorphous silicon thin film transistor 2, the first gate 4 is located below the amorphous silicon semiconductor pattern 5 and completely blocks the channel region, which is beneficial to reduce the light leakage current. At the same time, the second gate 6 of the amorphous silicon thin film transistor 2 and the first gate 4 of the polysilicon thin film transistor 1 are arranged in the same layer, so that the first gate 4 and the second gate 6 can pass through the same material film. The patterning process is used for preparation, which can effectively reduce the preparation process and improve the utilization rate of the material film.

In some embodiments, the array substrate according to claim 1 is characterized in that, the polysilicon thin film transistor 1 further comprises: a first source electrode 7 and a first drain electrode 8 located on the side of the first gate electrode 4 away from the base substrate 11 . , the first source electrode 7 and the first drain electrode 8 are both electrically connected to the polysilicon semiconductor pattern 3; the amorphous silicon thin film transistor 2 also includes: a second source electrode 9 located on the side of the amorphous silicon semiconductor pattern 5 away from the base substrate 11 and the second drain electrode 10, the second source electrode 9 and the second drain electrode 10 are electrically connected to the amorphous silicon semiconductor pattern 5; the first source electrode 7, the first drain electrode 8, the second source electrode 9 and the second drain electrode Pole 10 set on the same floor.

Specifically, an interlayer dielectric layer 14 is formed on the side of the amorphous silicon semiconductor pattern 5 away from the base substrate 11 , and the first source electrode 7 , the first drain electrode 8 , the second source electrode 9 and the second drain electrode 10 are located between the layers. On the side of the dielectric layer 14 away from the base substrate 11, the first source electrode 7 and the first drain electrode 8 are respectively electrically connected to the polysilicon semiconductor pattern 3 through the first via hole; the second source electrode 9 and the second drain electrode 10 respectively pass through The second via hole is electrically connected to the amorphous silicon semiconductor pattern 5 .

The second source 9 and the second drain 10 of the amorphous silicon thin film transistor 2 are arranged in the same layer as the first source 7 and the first drain 8 of the polysilicon thin film transistor 1, so that the first source 7 and the first drain The electrode 8 , the second source electrode 9 , and the second drain electrode 10 can be prepared by patterning the same material film, which can effectively reduce the preparation process and improve the utilization rate of the material film.

It should be noted that, in the embodiment of the present disclosure, the polysilicon thin film transistor 1 may be a top-gate thin film transistor or a double-gate thin film transistor, and FIG. 1 only exemplifies the polysilicon thin film transistor 1 as a top-gate thin film transistor Case.

When the polysilicon thin film transistor 1 is a double-gate thin film transistor, a third gate is further arranged between the polysilicon semiconductor pattern 3 and the base substrate 11, and the first gate 4 is electrically connected to the third gate (not in this case). shown); when the polysilicon thin film transistor 1 is a dual-gate thin film transistor, the size of the polysilicon thin film transistor 1 (the peripheral area has lower requirements for the size of the thin film transistor) will increase accordingly, but the off-state leakage current can be reduced accordingly.

In addition, in the polysilicon thin film transistor 1, the polysilicon semiconductor pattern 3 includes a channel region and a non-channel region, and the channel region is covered by the first gate electrode 4 for carrier transport. In order to reduce the resistance of the non-channel region and improve the performance of the polysilicon thin film transistor 1 , the non-channel region of the polysilicon semiconductor pattern 3 is generally made conductive.

The embodiments of the present disclosure provide an array substrate, wherein the low-temperature polysilicon thin film transistors located in the peripheral area can improve the driving and charging capability of the peripheral circuits, and the bottom-gate amorphous silicon thin film transistors located in the display area can meet the requirements of low off-state leakage current and small size requirements, this design is especially suitable for high-resolution products; at the same time, the second gate in the bottom gate type amorphous silicon thin film transistor is the same as the first gate in the top gate type/dual gate type low temperature polysilicon thin film transistor The layer arrangement enables the first gate electrode and the second gate electrode to be prepared by performing a patterning process on the same material thin film, which can effectively reduce the preparation process and improve the utilization rate of the material thin film.

FIG. 2 is a schematic cross-sectional view of another array substrate provided by an embodiment of the present disclosure. As shown in FIG. 2 , the difference from the previous embodiment is that in this embodiment, the second source electrode 9 and the amorphous silicon semiconductor pattern 5 are between the second drain electrode 10 and the amorphous silicon semiconductor pattern 5 are provided with a corresponding ohmic contact pattern 15; between the second source electrode 9 and the corresponding ohmic contact pattern 15, between the second drain electrode 10 and the corresponding ohmic contact pattern 15 Corresponding etching barrier patterns 16 are provided between the ohmic contact patterns 15 , and the material of the etching barrier patterns 16 includes metal materials.

The ohmic contact pattern 15 is used to reduce the contact resistance between the amorphous silicon semiconductor pattern 5 and the second source electrode 9 and the second drain electrode 10 . In actual production, it is found that in order to realize the electrical connection between the first source electrode 7 and the first drain electrode 8 and the polysilicon semiconductor pattern 3, it is necessary to sequentially etch the interlayer dielectric layer 14, the second insulating layer and the first insulating layer to form the first source electrode 7 and the first drain electrode 8. A via hole; in order to realize the electrical connection between the second source electrode 9 and the second drain electrode 10 and the amorphous silicon semiconductor pattern 5, only the interlayer dielectric layer 14 needs to be etched to form the second via hole. When the first via hole and the second via hole are formed by the same etching process, over-etching is likely to occur in the display area, so that the ohmic contact pattern 15 is located in the part of the second via hole to be mis-etched, The contact mode of the second source electrode 9 and the second drain electrode 10 formed thereafter and the ohmic contact pattern 15 is side contact, and the contact resistance is relatively large at this time.

In order to solve the above technical problems, in the embodiment of the present disclosure, when the ohmic contact pattern 15 is provided, an etching barrier layer made of metal material is also formed on the side of the ohmic contact pattern 15 away from the base substrate 11 . Among them, the materials of the interlayer dielectric layer 14, the second gate insulating layer 13, and the first gate insulating layer 12 are often inorganic insulating materials such as silicon oxide and silicon carbide, and dry etching is often used during via etching. The metal material film has a better blocking effect on the dry etching process, which can effectively reduce the over-etching.

In the embodiment of the present disclosure, on the one hand, the etching barrier layer can protect the ohmic contact pattern 15 during the process of etching the via hole in the interlayer dielectric layer 14, so as to prevent the ohmic contact pattern 15 from being etched incorrectly; on the other hand, it can Electrical connection between the second source electrode 9 , the second drain electrode 10 and the amorphous silicon semiconductor pattern 5 is achieved.

In some embodiments, the material of the etching stopper pattern 16 includes molybdenum; molybdenum not only has better conductivity, but also has a certain density, which can effectively block the dry etching process.

In some embodiments, the orthographic projection of the etch stop pattern 16 on the base substrate 11 and the orthographic projection of the corresponding ohmic contact pattern 15 on the base substrate 11 completely overlap. That is, the cross-sectional patterns of the etching stopper pattern 16 and the ohmic contact pattern 15 are exactly the same, and the etching stopper pattern 16 and the ohmic contact pattern 15 can be prepared based on the same mask, which can reduce the use of masks in the production process. quantity.

Embodiments of the present disclosure also provide a method for preparing an array substrate, which can be used to prepare the array substrate provided in the above embodiments, which will be described in detail below with reference to the accompanying drawings.

FIG. 3 is a flowchart of a method for preparing an array substrate according to an embodiment of the present disclosure. As shown in FIG. 3 , the preparation method includes:

S1. Provide a base substrate.

Wherein, the base substrate is divided into a display area and a peripheral area located around the display area.

S2, forming a polycrystalline silicon thin film transistor and an amorphous silicon thin film transistor on the base substrate.

Among them, the polysilicon thin film transistor is located in the peripheral area, the amorphous silicon thin film transistor is located in the display area, the polysilicon thin film transistor includes: a polysilicon semiconductor pattern and a first gate located on the side of the polysilicon semiconductor pattern away from the substrate, and the amorphous silicon thin film transistor is the bottom The gate type thin film transistor includes: an amorphous silicon semiconductor pattern and a second gate located on the side of the polysilicon semiconductor pattern close to the base substrate, and the first gate and the second gate are arranged in the same layer.

4 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present disclosure, and FIGS. 5 a to 5 f are schematic cross-sectional views of an intermediate structure of an array substrate fabricated by the fabrication method shown in FIG. 1 , as shown in FIG. 4 As shown in 5f, the preparation method can be used to prepare the array substrate shown in FIG. 1, and the preparation method includes:

Step S1, providing a base substrate.

Wherein, the base substrate is divided into a display area and a peripheral area located around the display area.

Step S201 , forming a polysilicon semiconductor pattern on one side of the base substrate.

Referring to FIG. 5a, in step S201, first, an amorphous silicon semiconductor material film is deposited on the base substrate 11 by a vapor deposition method; The crystalline silicon semiconductor pattern; finally, the crystallization process is performed on the amorphous silicon semiconductor pattern located in the peripheral area, so that the amorphous silicon semiconductor pattern is transformed into the polysilicon semiconductor pattern 3 .

Or, first, deposit an amorphous silicon semiconductor material film on the base substrate 11 by a vapor deposition method; then perform a crystallization process on the amorphous silicon semiconductor material film, so that the amorphous silicon semiconductor material film is converted into a polycrystalline silicon semiconductor material film; finally A patterning process is performed on the polysilicon semiconductor material film to obtain a polysilicon semiconductor pattern 3 in the peripheral area.

In some embodiments, the crystallization process includes: a solid phase crystallization process, a laser crystallization process, or a thermal annealing process.

It should be noted that the "patterning process" in the embodiments of the present disclosure refers to at least some of the process steps including photoresist coating, exposure, development, etching, and photoresist stripping.

Step S202 , forming a first gate insulating layer on the side of the polycrystalline silicon semiconductor pattern away from the base substrate.

Referring to FIG. 5b, a first gate insulating layer 12 is formed on the side of the polysilicon semiconductor pattern 3 away from the base substrate 11 by a deposition process. The material of the first gate insulating layer 12 includes silicon oxide and/or silicon carbide.

Step S203 , forming a first gate electrode and a second gate electrode on the side of the first gate insulating layer away from the base substrate, the first gate electrode is located in the peripheral region, and the second gate electrode is located in the display region.

Referring to FIG. 5c, in step S203, a gate conductive material film is firstly formed by a deposition process, and then a patterning process is performed on the gate conductive material film to form the pattern of the first gate 4 in the peripheral area and form the pattern in the display area. The pattern of the second gate 6 .

In some embodiments, the material of the gate conductive material film includes a metallic material.

It should be noted that the orthographic projection of the first gate 4 on the plane where the polysilicon semiconductor pattern 3 is located defines the channel region on the polysilicon semiconductor pattern 3, in order to reduce the resistance of the part located in the non-channel region on the polysilicon semiconductor pattern 3. , the part of the polysilicon semiconductor pattern 3 located in the non-channel region can be subjected to conducting treatment (eg, doping ions).

Step S204 , forming a second gate insulating layer on the side of the first gate electrode and the second gate electrode away from the base substrate.

Referring to FIG. 5d , a second gate insulating layer 13 is formed on a side of the first gate electrode 4 and the second gate electrode 6 away from the base substrate 11 by a deposition process. The material of the second gate insulating layer 13 includes silicon oxide and/or silicon carbide.

Step S205, forming an amorphous silicon semiconductor pattern on the side of the second gate insulating layer away from the base substrate.

Referring to FIG. 5e, firstly, a film of amorphous silicon semiconductor material is deposited on the base substrate 11 by a vapor deposition method; then a patterning process is performed on the film of amorphous silicon semiconductor material to obtain an amorphous silicon semiconductor pattern 5 in the display area. .

Step S206 , forming an interlayer dielectric layer on the side of the amorphous silicon semiconductor pattern away from the base substrate.

Referring to FIG. 5f, an interlayer dielectric material film is formed on the side of the amorphous silicon semiconductor pattern 5 away from the base substrate 11 by a deposition process, and then a first via hole connected to the polysilicon semiconductor pattern 3 is formed by a dry etching process. 17 and a second via hole 18 connected to the amorphous silicon semiconductor pattern 5 . The remaining portion of the interlayer dielectric material film constitutes the interlayer dielectric layer 14 .

In some embodiments, the material of the interlayer dielectric layer 14 includes silicon oxide and/or silicon carbide.

Step S207 , forming a first source electrode, a first drain electrode, a second source electrode and a second drain electrode on the side of the interlayer dielectric layer away from the base substrate.

Referring to FIG. 1, first, a source-drain conductive material film is formed by a deposition process, and then a patterning process is performed on the source-drain conductive material film to form the patterns of the first source electrode 7 and the first drain electrode 8 in the peripheral area. The display area forms a pattern of the second source electrode 9 and the second drain electrode 10 . The first source electrode 7 and the first drain electrode 8 are electrically connected to the polysilicon semiconductor pattern 3 through the first via hole, and the second source electrode 9 and the second drain electrode 10 are electrically connected to the amorphous silicon semiconductor pattern 5 through the second via hole.

In some embodiments, the material of the source-drain conductive material film includes a metal material.

6 is a flowchart of another method for fabricating an array substrate provided by an embodiment of the present disclosure, and FIGS. 7 a to 7 e are schematic cross-sectional views of preparing an amorphous silicon semiconductor pattern, an ohmic contact pattern, and an etching barrier pattern in an embodiment of the present disclosure. , as shown in Figures 6 to 7e, the preparation method can be used to prepare the array substrate shown in Figure 2. The difference between the preparation method shown in Figure 6 and the preparation method shown in Figure 4 is that in the preparation method shown in Figure 6 An ohmic contact pattern 15 and an etch stop pattern 16 are also prepared. Specifically, step S205 includes steps S2051 to S2056. Only steps S2051 to S2055 in FIG. 6 will be described in detail below, and for other steps in FIG. 6 , reference may be made to the foregoing description of FIG. 4 .

Step S2051 , forming an amorphous silicon semiconductor material film, an ohmic contact material film and an etching barrier material film in sequence on the side of the second gate insulating layer away from the base substrate.

Referring to FIG. 7a, an amorphous silicon semiconductor material film 5a, an ohmic contact material film 15a and an etch stop material film 16a are sequentially formed through a deposition process. The material of the ohmic contact material film 15a includes N+a-Si; the material of the etch stop material film 16a includes metal material. In some embodiments, the material of the etch stop material film 16a includes molybdenum.

In step S2052, a photoresist film layer is coated on the side of the etching barrier material film away from the lining, and the photoresist film layer is processed by a halftone mask process.

Referring to Fig. 7b, first, a photoresist film layer 19 is coated on the surface 16a of the etching barrier material film, and then the photoresist film layer 19 is subjected to a photomask treatment by a halftone mask, and finally the photoresist film layer 19 is subjected to a photomask treatment by a developer solution. The photoresist film layer 19 after photomask processing is subjected to development processing. The part of the photoresist film layer 19 located outside the area where the amorphous silicon semiconductor pattern 5 is to be formed is completely removed, the part of the photoresist film layer 19 located in the area where the ohmic contact pattern 15 is to be formed is completely retained, and the photoresist film layer 19 is completely retained. A portion of the layer 19 in the channel region where the amorphous silicon semiconductor pattern 5 is to be formed remains partially.

Step S2053, etching the etching barrier material film, the ohmic contact material film and the amorphous silicon semiconductor material film.

Referring to FIG. 7c, first, the etching barrier material film 16a is etched by a wet etching process, and the portion of the etching barrier material film 16a located under the photoresist film layer 19 is retained to obtain a preliminary etching barrier pattern 16. Then the dry etching process is used to etch the ohmic contact material film 15a and the amorphous silicon semiconductor material film 5a, and the ohmic contact material film 15a and the amorphous silicon semiconductor material film 5a are located in the part below the photoresist film layer 19 Remaining, a preliminary pattern of the ohmic contact pattern 15 and a final pattern of the amorphous silicon semiconductor pattern 5 are obtained.

Step S2054, performing ashing treatment on the photoresist film layer.

Referring to FIG. 7d, the photoresist film layer 19 is ashed, so that the part of the photoresist film layer 19 located in the area where the ohmic contact pattern 15 is to be formed remains, and the photoresist film layer 19 is located in the amorphous Part of the channel region of the silicon semiconductor pattern 5 is completely removed.

Step S2055, etching the preliminary pattern of the etching barrier pattern and the preliminary pattern of the ohmic contact pattern.

Referring to FIG. 7e, first, the etching barrier material film is etched by a wet etching process, and the part of the etching barrier material film located in the channel region is completely removed to obtain the final pattern of the etching barrier pattern 16; The ohmic contact material film is etched by an etching process, and the part of the ohmic contact material film located in the channel region is completely removed to obtain the final pattern of the ohmic contact pattern 15; the channel region of the amorphous silicon semiconductor pattern 5 is exposed.

After the end of step S2055, the remaining photoresist film layer 19 is peeled off.

Thereafter, in the process of forming the interlayer cutoff layer and forming the first via hole 17 and the second via hole 18 by dry etching, the etching stopper pattern 16 can protect the ohmic contact pattern 15 to prevent the ohmic contact pattern 15 from being mistakenly etching.

An embodiment of the present disclosure provides a method for preparing an array substrate. In the array substrate prepared by the method, the low-temperature polysilicon thin film transistor 1 located in the peripheral area can improve the driving and charging capability of the peripheral circuit, and the bottom gate type transistor located in the display area can improve the driving and charging capability of the peripheral circuit. The amorphous silicon thin film transistor 2 can meet the requirements of low leakage current and small size in the off-state, and this design is particularly suitable for high-resolution products; at the same time, the second gate 6 in the bottom gate type amorphous silicon thin film transistor 2 The first gate 4 in the gate type/dual gate type low temperature polysilicon thin film transistor 1 is arranged in the same layer, so that the first gate 4 and the second gate 6 can be prepared by patterning the same material film, which can effectively Reduce the preparation process and improve the utilization rate of the material film.

An embodiment of the present disclosure further provides a display device, the display device includes an array substrate, and the array substrate adopts the array substrate provided in any of the above embodiments. For details, please refer to the descriptions in the above embodiments, and details are not repeated here. .

The display device in the embodiment of the present disclosure may be any product or component with display function, such as liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, and navigator.

Since the display device provided in the third embodiment includes the array substrate provided in the foregoing embodiments, this embodiment has the beneficial technical effects described in the foregoing embodiments.

It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, without departing from the spirit and essence of the present invention, various modifications and improvements can be made, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (10)

1. An array substrate, characterized in that it comprises: a base substrate, a polysilicon thin film transistor and an amorphous silicon thin film transistor located on the same side on the base substrate, and the base substrate is divided into a display area and a polysilicon thin film transistor located in the display area a peripheral peripheral area, the polysilicon thin film transistor is located in the peripheral area, and the amorphous silicon thin film transistor is located in the display area; The polysilicon thin film transistor includes: a polysilicon semiconductor pattern and a first gate located on a side of the polysilicon semiconductor pattern away from the base substrate; The amorphous silicon thin film transistor is a bottom gate type thin film transistor, comprising: an amorphous silicon semiconductor pattern and a second gate located on the side of the polysilicon semiconductor pattern close to the base substrate; The first gate and the second gate are disposed in the same layer. 2 . The array substrate according to claim 1 , wherein the polysilicon thin film transistor further comprises: a first source electrode and a first drain electrode located on a side of the first gate away from the base substrate, 3 . Both the first source electrode and the first drain electrode are electrically connected to the polysilicon semiconductor pattern; The amorphous silicon thin film transistor further comprises: a second source electrode and a second drain electrode located on the side of the amorphous silicon semiconductor pattern away from the base substrate, the second source electrode and the second drain electrode are all electrically connected with the amorphous silicon semiconductor pattern; The first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged in the same layer. 3 . The array substrate according to claim 2 , wherein the second source electrode and the amorphous silicon semiconductor pattern and between the second drain electrode and the amorphous silicon semiconductor pattern are both arranged. 4 . A corresponding ohmic contact pattern is provided; Corresponding etching barrier patterns are arranged between the second source electrode and the corresponding ohmic contact pattern, and between the second drain electrode and the corresponding ohmic contact pattern, and the material of the etching barrier pattern includes metal materials . 4 . The array substrate according to claim 3 , wherein an orthographic projection of the etch stop pattern on the base substrate and an orthographic projection of the corresponding ohmic contact pattern on the base substrate 4 . , the two completely overlap. 5 . The array substrate according to claim 3 , wherein the material of the etching barrier pattern comprises molybdenum. 6 . 6. A display device, comprising: the array substrate according to any one of the preceding claims 1-5. 7. A method for preparing an array substrate, comprising: providing a base substrate, the base substrate is divided into a display area and a peripheral area located around the display area; A polysilicon thin film transistor and an amorphous silicon thin film transistor are formed on the base substrate, the polysilicon thin film transistor is located in the peripheral area, the amorphous silicon thin film transistor is located in the display area, and the polysilicon thin film transistor includes: polysilicon A semiconductor pattern and a first gate located on the side of the polysilicon semiconductor pattern away from the substrate, the amorphous silicon thin film transistor is a bottom gate thin film transistor, including: an amorphous silicon semiconductor pattern and a first gate located close to the polysilicon semiconductor pattern The second gate on one side of the base substrate, the first gate and the second gate are arranged in the same layer. 8 . The method for preparing an array substrate according to claim 7 , wherein the step of forming a polysilicon thin film transistor and an amorphous silicon thin film transistor on the base substrate comprises: 9 . A polysilicon semiconductor pattern is formed on one side of the base substrate, and the polysilicon semiconductor pattern is located in the peripheral region; forming a first gate insulating layer on the side of the polysilicon semiconductor pattern away from the base substrate; The first gate and the second gate are formed on a side of the first gate insulating layer away from the base substrate, the first gate is located in the peripheral region, and the second gate in said display area; forming a second gate insulating layer on a side of the first gate and the second gate away from the base substrate; An amorphous silicon semiconductor pattern is formed on a side of the second gate insulating layer away from the base substrate, and the amorphous silicon semiconductor pattern is located in the display area; forming an interlayer dielectric layer on the side of the amorphous silicon semiconductor pattern away from the base substrate; A first source electrode, a first drain electrode, a second source electrode and a second drain electrode are formed on the side of the interlayer dielectric layer away from the base substrate, and the first source electrode and the first drain electrode are located at the The peripheral region is electrically connected to the polysilicon semiconductor pattern, the second source electrode and the second drain electrode are located in the display region and are electrically connected to the amorphous silicon semiconductor pattern. 9 . The method for fabricating an array substrate according to claim 8 , wherein between the second source electrode and the amorphous silicon semiconductor pattern, the second drain electrode and the amorphous silicon semiconductor pattern Corresponding ohmic contact patterns are arranged therebetween; corresponding etching blocking patterns are arranged between the second source electrode and the corresponding ohmic contact pattern, and between the second drain electrode and the corresponding ohmic contact pattern, The material of the etch stop pattern includes metal material; The step of forming an amorphous silicon semiconductor pattern on the side of the second gate insulating layer away from the base substrate includes: Forming an amorphous silicon semiconductor material film, an ohmic contact material film and an etching barrier material film in sequence on the side of the second gate insulating layer away from the base substrate; A photoresist film layer is coated on the side of the etch stop material film away from the base substrate, and the photoresist film layer is processed by a halftone mask process. The part located outside the area where the amorphous silicon semiconductor pattern is to be formed is completely removed, the part of the photoresist film layer located in the area where the ohmic contact pattern is to be formed is completely retained, and the photoresist film layer is located in the area where the ohmic contact pattern is to be formed. Part of the channel region of the amorphous silicon semiconductor pattern remains; The etching barrier material film, the ohmic contact material film and the amorphous silicon semiconductor material film are etched, and the etching barrier material film, the ohmic contact material film and the amorphous silicon semiconductor material film are located in the The part below the photoresist film layer is retained to obtain the preliminary pattern of the etching barrier pattern, the preliminary pattern of the ohmic contact pattern and the final pattern of the amorphous silicon semiconductor pattern; Ashing is performed on the photoresist film layer, the photoresist film layer is located in the part of the area where the ohmic contact pattern is to be formed, and the photoresist film layer is located in the amorphous silicon semiconductor to be formed. Part of the channel region of the pattern is completely removed; The preliminary pattern of the etching barrier pattern and the preliminary pattern of the ohmic contact pattern are etched, and the portion of the preliminary pattern of the etching barrier pattern and the preliminary pattern of the ohmic contact pattern located in the channel region of the amorphous silicon semiconductor pattern is completely removed, The final pattern of the etching barrier pattern and the final pattern of the ohmic contact pattern are obtained. 10 . The manufacturing method of an array substrate according to claim 9 , wherein the step of forming an interlayer dielectric layer on the side of the amorphous silicon semiconductor pattern away from the base substrate comprises: 10 . forming an interlayer dielectric material film on the side of the amorphous silicon semiconductor pattern away from the base substrate; A first via hole connected to the polysilicon semiconductor pattern is formed by dry etching, and a second via hole connected to the etch stop pattern is formed.

Images