CN111913136A - Method for detecting whether test bit and tester interface are connected in error or not and chip test system - Google Patents
Method for detecting whether test bit and tester interface are connected in error or not and chip test system Download PDFInfo
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- CN111913136A CN111913136A CN202010785979.3A CN202010785979A CN111913136A CN 111913136 A CN111913136 A CN 111913136A CN 202010785979 A CN202010785979 A CN 202010785979A CN 111913136 A CN111913136 A CN 111913136A
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- 238000012360 testing method Methods 0.000 title claims abstract description 187
- 238000000034 method Methods 0.000 title claims abstract description 19
- 230000005284 excitation Effects 0.000 claims abstract description 23
- 238000012545 processing Methods 0.000 claims description 17
- 238000005259 measurement Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012790 confirmation Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
- G01R31/68—Testing of releasable connections, e.g. of terminals mounted on a printed circuit board
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention discloses a method for detecting whether a test position of a chip test board is connected with a tester interface in a wrong way and a chip test system, which are suitable for the situation that the chip test board is provided with a plurality of chip test positions, and each chip test position is connected with the corresponding interface of the tester through a connector to realize the connection between a chip and the tester. The invention specifically relates to a method for judging whether the connection between the connector of each chip test position and each interface of the testing machine is wrong or not by respectively connecting the connectors on each chip test position in series with resistors with different resistance values, then outputting an excitation signal to each resistor by the testing machine, collecting a response signal of each resistor, and finally judging whether the connection between the connector of each chip test position and each interface of the testing machine is wrong or not according to whether the response signal of each resistor accords with a corresponding preset signal or not, so that the testing machine can be prevented from mixing the test results of the chips of each chip test position due to the connection between the connector of the chip test position and the interface, and further, the testing machine is prevented from mixing.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a method for detecting whether a testing position of a chip testing board is connected with a tester interface in a wrong way and a chip testing system.
Background
In order to ensure the quality of the chip, the performance test of the chip is required before the chip leaves a factory, and only the chip meeting the performance requirement is subjected to subsequent packaging procedures and the like to be packaged and leave the factory. The chip testing system generally includes a tester loaded with a testing program, a testing circuit board in communication connection with the tester, and a transporting device, which discharges a tested chip to a corresponding position according to a testing result output by the tester.
In order to improve the testing efficiency, a plurality of testing sites are usually disposed on the testing circuit board, each testing site electrically connects the tested chip to the testing machine through a corresponding connector, and the testing machine tests a plurality of chips simultaneously. However, when connectors of each test site on the test circuit board are manually connected with interfaces of the tester, the connectors are easily connected and mixed with the interfaces of the tester, if the connectors are connected and mixed, the test results of the chips will be mixed, and errors will also occur when the carrying device carries out blanking according to the test results. For example, the chip a is placed at the test site a, the chip B is placed at the test site B, the connector a corresponding to the test site a should originally be connected to the interface a of the tester, and the connector B corresponding to the test site B should originally be connected to the interface B of the tester; if the connector A is wrongly connected with the interface B, the connector B is connected with the interface A, and the testing machine tests, the test result of the chip A is used as the test result of the chip B, the test result of the chip B is used as the test result of the chip A, and at the moment, when the carrying device carries out blanking according to the test result of the testing machine, blanking and material mixing can also occur, for example, good chips B are used as bad products for blanking, and bad chips A are used as good products for blanking.
Disclosure of Invention
The invention aims to provide a chip testing system which can detect whether the connection between each testing position of a chip testing board and each interface of a testing machine is misconnected so as to avoid mixing.
Another objective of the present invention is to provide a method for detecting whether the connection between each test bit of the chip test board and each interface of the tester is misconnected, so as to avoid mixing.
In order to achieve the above object, the present invention provides a chip testing system, which includes a chip testing board and a testing machine, wherein the chip testing board is provided with at least two chip testing positions, each chip testing position is connected with a testing machine interface through a connector, each connector is respectively connected with a resistor in series, and the resistances of the resistors are different; the testing machine comprises a power supply module, a measuring module and a processing module, wherein the power supply module outputs excitation signals to the resistors, the processing module collects response signals of the resistors through the measuring module, the processing module respectively compares the response signals of the resistors with preset signals, and judges whether the connection between each connector and each interface of the testing machine is wrong or not according to comparison results.
Compared with the prior art, the connectors on the chip test positions are respectively connected with the resistors with different resistance values in series, the power module of the testing machine is used for outputting excitation signals to the resistors, the acquisition module of the testing machine is used for acquiring response signals of the resistors, and the processing module is used for judging whether the connectors and the interfaces of the testing machine are in wrong connection or not according to the fact that whether the response signals of the resistors accord with the corresponding preset signals or not.
In an embodiment, the excitation signal is a current signal, the response signal is a voltage signal, the preset signal is a voltage interval, and if the response signal of any one of the resistors is outside the corresponding voltage interval, the processing module determines that a fault exists between the connector and the interface of the tester and outputs an alarm signal.
In an embodiment, the excitation signal is a voltage signal, the response signal is a current signal, the preset signal is a current interval, and if the response signal of any one of the resistors is outside the corresponding current interval, the processing module determines that a fault exists between the connector and the interface of the tester and outputs an alarm signal.
In one embodiment, the chip testing board is provided with two chip testing positions, the number of the resistors is two, and the resistance value of one resistor is twice that of the other resistor.
In an embodiment, the connector is a bull-horn connector, and the connector is connected with an interface wiring of the testing machine through a cable wire.
Specifically, the chip testing system further comprises a carrying device, wherein the carrying device is in communication connection with the testing machine through a walking line and is used for blanking the chips at the chip testing positions according to the testing results of the testing machine.
In order to achieve the above object, the present invention provides a method for detecting whether a test bit of a chip test board is misconnected with a tester interface, wherein the chip test board is provided with at least two chip test bits, and each chip test bit is connected with the tester interface through a connector. The method comprises the following steps:
providing a plurality of resistors with different resistance values, and respectively connecting each connector with one resistor in series;
outputting an excitation signal to each resistor through the tester, and collecting a response signal of each resistor;
and respectively comparing the response signal of each resistor with a preset signal, and judging whether the connection between each connector and each interface of the tester is wrong or not according to the comparison result.
Compared with the prior art, the invention respectively connects the connectors on each chip test position in series with the resistors with different resistance values, then the test machine outputs excitation signals to each resistor, collects response signals of each resistor, and finally judges whether the connection between the connector of each chip test position and each interface of the test machine is wrong according to whether the response signals of each resistor accord with the corresponding preset signals, thereby avoiding mixing the test results of the chips of each chip test position by the test machine caused by the connection between the connector of the chip test position and the interface of the test machine, further avoiding discharging and mixing materials, ensuring the quality of the chips in the application of the rear section, and simultaneously reducing the reworking, scrapping, customer complaint and the like of the chips caused by the mixing materials.
In an embodiment, the excitation signal is a current signal, the response signal is a voltage signal, the preset signal is a voltage interval, and if the response signal of any one of the resistors is outside the corresponding voltage interval, it is determined that a fault exists between the connector and the interface of the tester, and an alarm signal is output.
In an embodiment, the excitation signal is a voltage signal, the response signal is a current signal, the preset signal is a current interval, and if the response signal of any one of the resistors is outside the corresponding current interval, it is determined that a fault exists between the connector and the interface of the tester, and an alarm signal is output.
In one embodiment, the chip testing board is provided with two chip testing positions, the number of the resistors is two, and the resistance value of one resistor is twice that of the other resistor.
Drawings
FIG. 1 is a flowchart illustrating a method for detecting whether a test bit of a chip test board is incorrectly connected to a tester interface according to an embodiment of the present invention.
FIG. 2 is a block diagram of a chip test system according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a chip test system according to an embodiment of the present invention.
FIG. 4 is a schematic diagram of a chip test system according to another embodiment of the present invention.
Detailed Description
In order to explain technical contents, structural features, and effects achieved by the present invention in detail, the following detailed description is given with reference to the embodiments and the accompanying drawings.
The invention discloses a method for detecting whether a test position of a chip test board is connected with a tester interface in a wrong way, which is suitable for the situation that the chip test board is provided with a plurality of chip test positions, and each chip test position is connected with the corresponding interface wiring of the tester through a connector to realize the connection between a chip and the tester interface so as to obtain whether the connection between the chip test position and the tester interface is in a wrong way, thereby avoiding mixing the test results of the chips of each chip test position due to the connection between the chip test position and the tester interface in a wrong way and further avoiding the occurrence of blanking and mixing of the tester.
As shown in fig. 1, the method for detecting whether the test bit of the chip test board is connected with the tester interface in error includes the following steps:
s101, providing a plurality of resistors with different resistance values, and respectively connecting each connector with a resistor in series. Wherein the resistance value difference between the individual resistors is as large as possible, e.g. the resistance values between different resistors differ by 1k omega.
S102, outputting excitation signals to each resistor through a testing machine, and collecting response signals of each resistor.
S103, respectively comparing the response signals of the resistors with preset signals, and judging whether the connectors are connected with the interfaces of the tester in a wrong way or not according to comparison results. The preset signal is set according to the excitation signal to be output and the resistance value of the resistor.
In one embodiment of the present invention, the excitation signal is a current signal, and the response signal is a voltage signal, and the connector connected in series with each resistor is determined whether to be connected to the correct tester interface by applying the same amount of current to the resistor with different resistance and obtaining the voltage of each resistor. In this embodiment, the preset signal is a voltage interval, and if the response signal of any resistor is located outside the corresponding voltage interval, it is determined that there is a fault between the connector and the interface of the test machine, and an alarm signal is output to remind a worker. It is common knowledge how to set the voltage interval according to the possible fluctuation of the voltage in the specific embodiment, and therefore, the detailed description thereof is omitted.
For example, in an embodiment where a chip testing board has two chip testing sites, the connector of one chip testing site is connected in series with the resistor R1, and the connector of the other chip testing site is connected in series with the resistor R2, and the resistance of the resistor R1 is twice as large as the resistance of the resistor R2. Taking the resistance value of the resistor R1 as 1k Ω and the resistance value of the resistor R2 as 2k Ω as an example, if the tester outputs 1mA current to the resistor R1 and the resistor R2, respectively, the preset voltage corresponding to the resistor R1 should be about 1V, and the preset voltage corresponding to the resistor R2 should be about 2V. If the voltage collected by the resistor R1 is about 1V and the voltage collected by the resistor R2 is about 2V, it is indicated that the connectors connected in series with the resistor R1 and the resistor R2 have no wrong connection tester interface. On the contrary, if the voltage collected by the resistor R1 is about 2V and the voltage collected by the resistor R2 is about 1V, it is indicated that the voltage between the connector connected in series with the resistor R1 and the resistor R2 and the interface of the tester is mixed, and at this time, an alarm signal is output to remind the staff of checking and confirming on site.
In another embodiment of the present invention, the stimulus signal is a voltage signal, and the response signal is a current signal, and the connector connected in series with each resistor is connected to the correct tester interface by providing the same voltage to each resistor with different resistance and obtaining the current of each resistor. In this embodiment, the preset signal is a current interval, and if the response signal of any resistor is located outside the corresponding current interval, it is determined that there is a fault between the connector and the interface of the test machine, and an alarm signal is output to remind a worker. It is common knowledge how to set the current interval according to the possible fluctuation of the current in the specific embodiment, and therefore, the detailed description is omitted here.
The invention also discloses a chip testing system, as shown in fig. 2, the chip testing system comprises a chip testing board 10, a testing machine 20 and a carrying device 30. The conveying device 30 is in communication connection with the testing machine 20 through a walking line, and is configured to discharge chips (not shown) at chip test sites according to test results of the testing machine 20. The chip test board 10 is provided with at least two chip test sites, each chip test site is connected with a corresponding tester interface through a connector, each connector is further connected with a resistor in series, and the resistance values of the resistors are different. The testing machine 20 includes a power module 21, a measuring module 22, and a processing module 23, where the power module 21 outputs an excitation signal to each resistor, the processing module 23 collects a response signal of each resistor via the measuring module 22, and the processing module 23 further compares the response signal of each resistor with a corresponding preset signal thereof, and determines whether there is a connection error between each connector and each interface of the testing machine 20 according to a comparison result. The preset signal is set according to the excitation signal to be output by the power module 21 and the resistance value of the resistor. In one embodiment, the chip test site is electrically connected to the connector through a plurality of wires, so as to electrically connect the chip to the connector, and further electrically connect the chip to the tester 20. The connector is a header connector, and the connector is connected to the interface wiring of the tester 20 through a cable wire, but the specific implementation is not limited thereto.
In one embodiment of the present invention, the excitation signal is a current signal, and correspondingly, the response signal is a voltage signal, the tester 20 applies the same amount of current to each resistor with different resistance through its power module 21, and obtains the voltage of each resistor through the measurement module 22 to determine whether the connector connected in series with the resistor is connected to the correct tester interface. In this embodiment, the preset signal is a voltage interval, and if the response signal of any resistor is located outside the corresponding voltage interval, the processing module 23 determines that there is a connection error between the connector and the interface of the test machine 20, and outputs an alarm signal to remind a worker. It is common knowledge how to set the voltage interval according to the possible fluctuation of the voltage in the specific embodiment, and therefore, the detailed description thereof is omitted.
As shown in fig. 3, in an embodiment, the chip testing board 10 has two chip testing sites 111 and 112, wherein the connector 121 of one chip testing site 111 is connected in series with the resistor R1, the connector 122 of the other chip testing site 112 is connected in series with the resistor R2, the resistance of the resistor R1 is twice the resistance of the resistor R2, and the other ends of the resistor R1 and the resistor R2 are both grounded. Taking the resistance value of the resistor R1 as 1k Ω and the resistance value of the resistor R2 as 2k Ω as an example, if the power module 21 of the tester 20 outputs 1mA current to the resistor R1 and the resistor R2, respectively, the preset voltage corresponding to the resistor R1 should be about 1V, and the preset voltage corresponding to the resistor R2 should be about 2V. If the voltage collected by the measurement module 22 is about 1V for the resistor R1 and about 2V for the resistor R2, it indicates that neither of the connectors 121 and 122 connected in series with the resistor R1 and the resistor R2 has an interface of the testing machine 20, and the testing machine 20 can normally perform the chip test. On the contrary, if the voltage collected by the measurement module 22 is about 2V for the resistor R1 and about 1V for the resistor R2, it indicates that the connections between the connectors 121 and 122 connected in series with the resistors R1 and R2 and the interface of the test machine 20 are mixed, and at this time, the test machine 20 does not perform the chip test and outputs an alarm signal to remind the operator to perform the on-site inspection and confirmation. In a specific implementation, an alarm lamp or a buzzer or the like may be provided in the testing machine 20, and the processing module 23 outputs an alarm instruction to alarm the alarm lamp or the buzzer to remind the operator, but the invention should not be limited thereto.
As shown in fig. 4, in an embodiment, the chip testing board 10 has three chip testing sites 111, 112, 113, wherein the connector 121 of one chip testing site 111 is connected in series with the resistor R1 ', the connector 122 of another chip testing site 112 is connected in series with the resistor R2', and the connector 123 of another chip testing site 113 is connected in series with the resistor R3 ', the resistor R1', the resistor R2 ', and the resistor R3', which are all grounded. Taking the resistance value of the resistor R1 ' as 1k Ω, the resistance value of the resistor R2 ' as 3k Ω, and the resistance value of the resistor R3 ' as 6 Ω as an example, if the power module 21 of the tester 20 outputs 1.2mA current to the resistor R1 ', the resistor R2 ', and the resistor R3 ', the preset voltage corresponding to the resistor R1 ' should be about 1.2V, the preset voltage corresponding to the resistor R2 ' should be about 3.6V, and the preset voltage corresponding to the resistor R3 ' should be about 7.2V. If the voltage collected by the measurement module 22 is about 1.2V for the resistor R1 ', about 3.6V for the resistor R2', and about 7.2V for the resistor R3 ', it is indicated that none of the connectors 121, 122, and 123 connected in series with the resistor R1', the resistor R2 ', and the resistor R3' are connected to the wrong interface of the tester 20, and the tester 20 can perform the chip test normally. On the contrary, if the voltage of the resistor R1 ' is about 7.2V, the voltage of the resistor R2 ' is about 3.6V, and the voltage of the resistor R3 ' is about 1.2V, which are collected by the measurement module 22, it is described that the connectors 121 and 123 connected in series with the resistor R1 ' and the resistor R3 ' are mixed with the interface of the tester 20, and at this time, the tester 20 does not perform the chip test, and outputs an alarm signal to remind the worker to perform the on-site inspection and confirmation.
In another embodiment of the present invention, the excitation signal is a voltage signal, and correspondingly, the response signal is a current signal, the tester 20 provides the same voltage to each resistor with different resistance value by its power module 21 and obtains the current of each resistor by the measurement module 22 to determine whether the connector connected in series with the resistor is connected to the correct tester interface. In this embodiment, the preset signal is a current interval, and if the response signal of any resistor is located outside the corresponding current interval, the processing module 23 determines that there is a connection error between the connector and the interface of the test machine 20, and outputs an alarm signal to remind a worker. It is common knowledge how to set the current interval according to the possible fluctuation of the current in the specific embodiment, and therefore, the detailed description is omitted here.
In summary, the connectors on the chip test sites are respectively connected in series with resistors with different resistance values, then the power module 21 of the testing machine 20 outputs the excitation signals to the resistors, the acquisition modules of the testing machine 20 acquire the response signals of the resistors, and finally, whether the connection between the connectors of the chip test sites and the interfaces of the testing machine 20 is wrong is judged according to whether the response signals of the resistors conform to the corresponding preset signals, so that the test result of the chip of each chip test site is mixed by the testing machine 20 due to the connection between the connectors of the chip test sites and the interfaces of the testing machine 20, the occurrence of blanking and mixing is avoided, the quality of the chip in the rear-section application is ensured, and the reworking, scrapping, customer complaints and the like of the chip due to mixing are reduced.
The above disclosure is only a preferred embodiment of the present invention, and certainly should not be taken as limiting the scope of the present invention, which is therefore intended to cover all equivalent changes and modifications within the scope of the present invention.
Claims (10)
1. A chip testing system comprises a chip testing board and a testing machine, wherein the testing machine comprises a power supply module, a measuring module and a processing module, the chip testing board is provided with at least two chip testing positions, each chip testing position is connected with a testing machine interface through a connector in a wiring mode, the chip testing system is characterized in that each connector is respectively connected with a resistor in series, the resistance values of the resistors are different, the power supply module outputs excitation signals to the resistors, the processing module collects response signals of the resistors through the measuring module, the processing module further compares the response signals of the resistors with preset signals respectively, and whether the connection between the connectors and the interfaces of the testing machine is wrong or not is judged according to comparison results.
2. The chip testing system of claim 1, wherein the excitation signal is a current signal, the response signal is a voltage signal, the preset signal is a voltage interval, and if the response signal of any one of the resistors is outside the corresponding voltage interval, the processing module determines that there is a fault between the connector and the interface of the tester and outputs an alarm signal.
3. The chip testing system of claim 1, wherein the excitation signal is a voltage signal, the response signal is a current signal, the predetermined signal is a current interval, and if the response signal of any one of the resistors is outside the corresponding current interval, the processing module determines that there is a fault between the connector and the interface of the tester and outputs an alarm signal.
4. The chip test system according to any one of claims 1 to 3, wherein the chip test board is provided with two chip test sites, the number of the resistors is two, and the resistance of one of the resistors is twice as large as that of the other resistor.
5. The chip test system of claim 1, wherein the connector is a header connector, the connector being connected to the interface wires of the tester by cable wires.
6. The chip testing system of claim 1, further comprising a handling device communicatively coupled to the tester via a walking line for unloading the chips from the chip test sites based on the test results from the tester.
7. A method for detecting whether a test bit of a chip test board is misconnected with a tester interface or not, wherein the chip test board is provided with at least two chip test bits, and each chip test bit is connected with the tester interface through a connector in a wiring way, and the method is characterized by comprising the following steps:
providing a plurality of resistors with different resistance values, and respectively connecting each connector with one resistor in series;
outputting an excitation signal to each resistor through the tester, and collecting a response signal of each resistor;
and respectively comparing the response signal of each resistor with a preset signal, and judging whether the connection between each connector and each interface of the tester is wrong or not according to the comparison result.
8. The method as claimed in claim 7, wherein the excitation signal is a current signal, the response signal is a voltage signal, the predetermined signal is a voltage interval, and if the response signal of any one of the resistors is outside the corresponding voltage interval, the method determines that the interface between the connector and the tester is faulty, and outputs an alarm signal.
9. The method as claimed in claim 7, wherein the excitation signal is a voltage signal, the response signal is a current signal, the predetermined signal is a current interval, and if the response signal of any one of the resistors is outside the corresponding current interval, the method determines that the interface between the connector and the tester is faulty, and outputs an alarm signal.
10. The method as claimed in any one of claims 7 to 9, wherein the chip test board has two chip test sites, and the number of the resistors is two, wherein the resistance of one of the resistors is twice as large as the resistance of the other resistor.
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| CN115201720A (en) * | 2021-04-08 | 2022-10-18 | 格科微电子（上海）有限公司 | Wiring inspection method and device of wafer test equipment, wafer test equipment and system |
| CN113560202A (en) * | 2021-07-26 | 2021-10-29 | 广东利扬芯片测试股份有限公司 | IC chip sorting detection auxiliary system |
| CN114578266A (en) * | 2022-03-18 | 2022-06-03 | 湖南宇诺辰电子科技有限公司 | Method and system for testing reliability of domestic mainboard |
| CN114578266B (en) * | 2022-03-18 | 2022-08-16 | 湖南宇诺辰电子科技有限公司 | Method and system for testing reliability of domestic mainboard |
| CN115356512A (en) * | 2022-08-18 | 2022-11-18 | 深圳市锦锐科技股份有限公司 | Integrated single-chip microcomputer chip abnormity analysis system |
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Application publication date: 20201110 |