CN111900959B - Clock spread spectrum generating circuit based on linear feedback shift register - Google Patents
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
- H03K5/1254—Suppression or limitation of noise or interference specially adapted for pulses generated by closure of switches, i.e. anti-bouncing devices
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
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Abstract
本发明公开了一种基于线性反馈移位寄存器的时钟展频生成电路，涉及数字电路领域，该电路包括随机数产生子电路、频率选择子电路以及时钟生成子电路，随机数产生子电路包括若干阶的线性反馈移位寄存器以产生随机数序列，该随机数序列输入到频率选择子电路中用于控制时钟展频信号的高电平持续时间，继而对时钟信号进行调制生成时钟展频信号，该电路可以更好地降低输出信号的峰值频谱，从而达到更佳EMI性能。
The invention discloses a clock spread spectrum generation circuit based on a linear feedback shift register, and relates to the field of digital circuits. The circuit includes a random number generation subcircuit, a frequency selection subcircuit and a clock generation subcircuit. The random number generation subcircuit includes several order linear feedback shift register to generate a random number sequence, which is input into the frequency selection sub-circuit to control the high level duration of the clock spread spectrum signal, and then modulate the clock signal to generate a clock spread spectrum signal, This circuit can better reduce the peak spectrum of the output signal, resulting in better EMI performance.
Description
Technical Field
The invention relates to the field of digital circuits, in particular to a clock spread spectrum generating circuit based on a linear feedback shift register.
Background
With the development of technology, the clock frequency of digital signals is higher and higher, and in a high-frequency digital system, the EMI (Electromagnetic Interference) is also larger than that of a lower-frequency system, where the EMI is an influence of a circuit system on a peripheral circuit system through conduction or radiation, and the EMI causes a reduction in circuit performance to make related authentication unable to pass, and may cause a failure of the whole system.
The clock signal is often the highest frequency and steepest edge signal in the circuit system, most of the EMI problems are generated related to the clock signal, there are many ways to reduce EMI, including shielding, filtering, isolating, ferrite bead, signal edge control, and adding power and GND layer in the PCB, and the like, and in addition, Spread Spectrum (Spread Spectrum Clocking) is also an effective method to reduce EMI.
Disclosure of Invention
The present invention provides a clock spread spectrum generating circuit based on a linear feedback shift register, aiming at the above problems and technical requirements, and the technical scheme of the present invention is as follows:
a clock spread spectrum generating circuit based on a linear feedback shift register comprises a random number generating sub-circuit, a frequency selecting sub-circuit and a clock generating sub-circuit; the random number generating sub-circuit comprises a plurality of stages of linear feedback shift registers, and taps of the linear feedback shift registers lead out spread spectrum period selection ends to be connected to the frequency selection sub-circuit;
the frequency selection sub-circuit comprises a first multiplexer, a spread spectrum period selection end led out by the random number generation sub-circuit is connected to a state bit of the first multiplexer, the first multiplexer comprises at least two input ends, clock period signals are respectively connected to the input ends of the first multiplexer through deviation processors on each branch, each deviation processor also respectively obtains a period deviation number corresponding to the input and processes the clock period signals according to the period deviation number, and each deviation processor comprises an adder and/or a subtracter; the output end of the first multiplexer is connected with the output end of the frequency selection sub-circuit and is connected with the clock generation sub-circuit;
the clock generation sub-circuit comprises a second multi-path selector, a trigger, a down counter, a loading control logic and a comparison logic, wherein the output end of the second multi-path selector is connected with the input end of the trigger, the clock end of the trigger acquires a clock signal, the output end of the trigger is subjected to self-counting by the down counter and then is input to the first input end of the second multi-path selector, and the second input end of the second multi-path selector is connected with the output end of the frequency selection sub-circuit;
the output end of the trigger is connected to the state bit of the second multiplexer after passing through the loading control logic, the loading control logic outputs a high level to the state bit of the second multiplexer when the output signal of the trigger is 0 so that the second multiplexer gates the second input end, otherwise, outputs a low level to the state bit of the second multiplexer so that the second multiplexer gates the first input end;
the output end of the trigger outputs a clock spread spectrum signal after passing through a comparison logic, the comparison logic outputs a high level when the output signal of the trigger is more than a half of the clock period signal, otherwise outputs a low level, the clock spread spectrum signal is also output to the clock end of a linear feedback shift register in the random number generation sub-circuit, and the clock spread spectrum signal is counted by taking the clock signal as a unit.
In the loading control logic, the output signal of the trigger is input to the state bit of a third multi-path selector according to the bit self or after the bit self, the first input end of the third multi-path selector obtains a high level, the second input end obtains a low level, and the output end of the third multi-path selector is connected with the state bit of the second multi-path selector; and when the output signal of the trigger is 0, the state bit of the third multiplexer inputs a low level and gates the first input end to output a high level, otherwise, the state bit of the third multiplexer inputs a high level and gates the second input end to output a low level.
The further technical scheme is that n state bits of spreading period selection ends connected to a first multiplexer are respectively led out from taps at n different orders of the linear feedback shift register, and the first multiplexer comprises 2nThe first multiplexer is connected with the spread spectrum period selection ends in a mode that n is larger than or equal to 2.
The frequency selection sub-circuit further comprises a fourth multiplexer, one input end of the fourth multiplexer is connected with the output end of the first multiplexer, the other input end of the fourth multiplexer inputs a clock periodic signal, the output end of the fourth multiplexer is connected with the output end of the frequency selection sub-circuit, and the state bit of the fourth multiplexer is connected with the spread spectrum enabling end.
The further technical scheme is that the deviation processors on every two branches respectively acquire the period deviation number of the input.
The beneficial technical effects of the invention are as follows:
the application discloses a clock spread spectrum generating circuit based on a linear feedback shift register, which utilizes the linear feedback shift register to generate a random code and utilizes the random code to modulate a clock signal so as to achieve the purpose of spreading the clock signal, and can better reduce the peak frequency spectrum of an output signal, thereby achieving better EMI performance.
Drawings
Fig. 1 is a circuit configuration diagram of a clock spread spectrum generation circuit according to the present application.
Fig. 2 is a frequency spectrum of an original clock signal used in a measurement experiment.
Fig. 3 is a frequency spectrum of a signal obtained by clock-spreading the original clock signal shown in fig. 2 by a conventional triangulation method.
Fig. 4 is a frequency spectrum of a signal obtained by clock-spreading the original clock signal shown in fig. 2 by the clock spread spectrum generation circuit of the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
Referring to fig. 1, the clock spread spectrum generation circuit includes a random number generation sub-circuit, a frequency selection sub-circuit, and a clock generation sub-circuit.
The random number generating sub-circuit includes a Linear Feedback Shift Register (LFSR), and the LFSR includes several stages, in this application, the specific order of the LFSR is not limited to be adjustable, for example, fig. 1 includes 19 stages, and actually 9 stages, 11 stages, 21 stages, and so on may also be selected.
The tap lead-out spread spectrum period selection end of the LFSR is connected to the frequency selection sub-circuit. In the application, a spreading period selection terminal is led out from a tap at a certain order in the LFSR, or a plurality of spreading period selection terminals are led out from taps at a certain order in the LFSR, that is, n spreading period selection terminals are led out from n taps at different orders in the LFSR and are connected to a frequency selection sub-circuit, where n is greater than or equal to 2.
When each spreading period selection end is led out from the LFSR, the spreading period selection end can be led out from a tap at any order according to actual needs, for example, fig. 1 takes a tap at 0 order of a 19-order LFSR as an example, that is, the random number generation sub-circuit is composed of a 19-order LFSR, and the generation polynomial of the random number generation sub-circuit is g (x) ═ x19+x16+1, Q [ 0] at 0 th order]And leading out a spread spectrum period selection end to the frequency selection sub-circuit. For example, when two spreading period selection terminals are extracted, except for Q [ 0] at 0 th order]Besides, Q1 at 1 st order can be led out]And so on. Because the random number sequence output by the random number generation sub-circuit is related to the initial value of the LFSR, the initial value of the LFSR can be configured according to actual needs to generate different random number sequences.
The frequency selection sub-circuit includes a first multiplexer MUX1, the random number generation sub-circuit derives a spreading period selection terminal connected to the status bit of the first multiplexer MUX1, and the first multiplexer MUX1 includes at least two input terminals, as shown in fig. 1 by way of example where the MUX1 includes one status bit and two input terminals. When the random number generation sub-circuit brings out n spread spectrum period selection terminals, the MUX1 includes 2nThe input end and n state bits, n state bits of MUX1 correspond respectively and connect n spread spectrum period selection ends.
The clock period signal period is connected to each input terminal of the first multiplexer MUX1 through each branch, and the sequence length of the clock period signal period is not limited, and is represented as period [6:0] by a sequence of 7 bits. Each branch is provided with a deviation processor, the deviation processor includes an adder and/or a subtractor, and the deviation processor on each branch further obtains the corresponding input period deviation number, for example, in fig. 1, the deviation processor on one branch of the MUX1 is the adder P1 and correspondingly obtains the input period deviation number spread _ plus, and the deviation processor on the other branch is the subtractor M1 and correspondingly obtains the input period deviation number spread _ minus. It should be noted that both the spread _ plus and the spread _ minus indicate the number of cycle deviations, and the present application adopts different expressions for distinguishing the inputs of the adder and the subtractor. The number of cycle offsets of the inputs acquired by the offset processors on each of the two branches connected to the input terminal of MUX1 may be the same or different, for example, in fig. 1, the spread _ plus and the spread _ minus may be the same or different, for example, when MUX1 has four input terminals connected to four branches, the number of cycle offsets of the offset processors on the four branches may be the same or different.
When the state bits of the MUX1 input different signals, the MUX1 gates different branches to output the clock skew signal spread _ period such that the output clock skew signal spread _ period has a different period skew with respect to the clock period signal period. For example, referring to fig. 1 as an example, when the state bit of the MUX1 obtains a low level from the spreading period selection end, the MUX1 gates the branch of the adder P1, and thus the spread _ period + spread _ plus; when the state bit of the MUX1 gets high from the spreading period selection end, the MUX1 gates the branch of the subtractor M1, so that the spread _ period is period-spread _ minus.
In this application, the output terminal of the MUX1 is connected to the output terminal of the frequency selection sub-circuit and connected to the clock generation sub-circuit, and in this application, the output terminal of the MUX1 may be directly connected to the clock generation sub-circuit, or the output terminal of the MUX1 is connected to the clock generation sub-circuit through the fourth multiplexer MUX4, as shown in fig. 1, the frequency selection sub-circuit further includes the fourth multiplexer MUX4, one input terminal of the MUX4 is connected to the output terminal of the MUX1, and the other input terminal is connected to the clock period signal period, the output terminal of the MUX4 is connected to the output terminal of the frequency selection sub-circuit, and the status bit of the MUX4 is connected to the spread spectrum enable terminal spread _. The circuit may be a high-level enable or a low-level enable, fig. 1 of the present application takes a high-level enable as an example, when the spread _ en is a high level, the MUX4 gates the input end connected to the MUX1 to output the clock deviation signal spread _ period for controlling the high-level duration of the clock spreading signal clk _ g, and then the subsequently generated clock spreading signal clk _ g performs spreading with the period as the center; when the spread _ en is at a low level, the MUX4 gates the input terminal to which the periodic clock signal period is connected to directly output period, and at this time, the clock spreading signal clk _ g generated subsequently has no period deviation, i.e., no spreading. Thereby making the circuit compatible with spread spectrum functionality as well as original functionality.
The clock generation sub-circuit comprises a second multiplexer MUX2, a flip-flop T1, a down counter M2, load control logic and comparison logic, the flip-flop T1 in this application being a D flip-flop. The output terminal of the second multiplexer MUX2 is connected to the input terminal of the flip-flop T1, the clock terminal of the flip-flop T1 obtains the clock signal clk, the output terminal of the flip-flop T1 outputs the fine _ count signal, the fine _ count signal is subjected to self-decrement by the down-counter M2 and then is input to the first input terminal (0 state bit terminal in the figure) of the second multiplexer MUX2, that is, the output terminal of the flip-flop T1 is connected to the down-counter M2, and meanwhile, the down-counter M2 obtains the self-decrement 1. A second input (the 1-state bit terminal in the figure) of the second multiplexer MUX2 is connected to the output of the frequency selection sub-circuit.
The output terminal of the flip-flop T1 is connected to the state bit MUX2 of the second multiplexer MUX2 to output Load _ fine after passing through the Load control logic, and the Load control logic outputs high level Load _ fine to the state bit of the second multiplexer MUX2 when the output signal of the flip-flop T1 is 0, so that the second multiplexer MUX2 gates the second input terminal, thereby loading the spread _ period generated by the frequency selection sub-circuit into the fine _ count signal as the initial value of the next count. The Load control logic outputs a low Load _ fine to the state bit of the second multiplexer MUX2 when the output signal of the flip-flop T1 is not 0, causing the second multiplexer MUX2 to gate the first input to obtain the self-decremented value of fine _ count.
In the load control logic of the present application, the output signal fine _ count of the flip-flop T1 is first bit-wise input from or to the state bit of the third multiplexer MUX3, the first input terminal (0 state bit terminal in the figure) of the third multiplexer MUX3 obtains a high level, the second input terminal (1 state bit terminal in the figure) obtains a low level, and the output terminal of the third multiplexer MUX3 is connected to the state bit of the second multiplexer MUX 2. When the fine _ count is counted to 0, the bitwise OR operation is performed and then the low level 0 is output to the state bit of the MUX3 so as to gate the high level signal of the first input end to the MUX 2; when fine _ count is not 0, a bitwise or operation is performed to output a high 1 to the state bit of MUX3 to gate the low signal at the second input to MUX 2.
The output signal fine _ count of the flip-flop T1 also outputs the clock spreading signal clk _ g after passing through the comparison logic, and the comparison logic outputs a high level when the output signal of the flip-flop T1 is greater than half of the clock period signal period, and otherwise outputs a low level. In the method, fine _ count and period/2 are compared, and the comparison result is input to the state bit of the fifth multiplexer MUX5, the first input terminal of the MUX5 inputs low level, the second input terminal inputs high level, when fine _ count is less than period/2, the low level is output to the state bit of the MUX5 to enable the state bit to gate the first input terminal to output low level clk _ g, otherwise, the high level is output to the state bit of the MUX5 to enable the state bit to gate the second input terminal to output high level clk _ g, the clock spreading signal clk _ g is counted by taking the clock signal clk as a unit, and period is the period of clk _ g counted by taking clk as a unit. In comparing fine _ count with period/2, the present application compares fine _ count with a sequence of high k-1 bits of a periodic signal period, which has k bits in common, and when comparing fine _ count with its sequence of high k-1 bits, which is equivalent to comparing with half of period, for example, in the present application, period [6:0], this step compares fine _ count with period [6:1], which is equivalent to using period/2 to control the high and low durations of clk _ g, respectively, which, as seen from the output waveform of clk _ g, will change with different initial values each time the fine _ count is loaded, and the low duration will remain constant in each period, which, as a whole, is random between clk _ count and period + read _ 2.
In order to illustrate the effect of the clock spread spectrum generation circuit on reducing EMI, the present application has performed an actual measurement experiment, the spectrum of an original clock signal without spreading is shown in fig. 2, the spectrum of a signal obtained by spreading the original clock signal by using a conventional triangle tuning method is shown in fig. 3, and the peak of the spectrum is-12.25 dB at 500 kHz. The spectrum of the signal after the original clock signal is spread by using the circuit of the present application is shown in fig. 4, the peak value of the spectrum is-21.74 dB at 500kHz, which is 9.49dB lower than the peak value obtained by the triangle debugging method, so that the spread spectrum generating circuit of the present application can better reduce the peak spectrum of the output signal, thereby achieving better EMI performance.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
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| CN113835466B (en) * | 2021-08-20 | 2023-08-08 | 苏州浪潮智能科技有限公司 | A control device and method for realizing server spread spectrum |
| CN115810334B (en) * | 2022-11-18 | 2024-10-25 | 广西自贸区睿显科技有限公司 | Chip circuit for reducing electromagnetic interference of OLED driving circuit |
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