CN111900201A - Semiconductor structure and manufacturing method - Google Patents

Abstract

The present application discloses a semiconductor structure and a manufacturing method. The semiconductor structure includes: a substrate with a trench; a gate dielectric layer located on the trench wall; a first dielectric layer located at the lower part of the trench a gate; a second gate located on the first gate, wherein the width of the second gate is smaller than that of the first gate; an isolation layer located on the upper part of the trench and filled at least to the second gate and the trench part of the space between the grooves. The semiconductor structure of the present application has a first gate and a second gate, the second gate is located on the first gate, the width of the second gate is smaller than the width of the first gate, and the two side walls of the second gate are There is a space between the substrate and the active N-type junction transistor and a wide space between the metal and the junction of the overlapping part, which improves the gate-induced drain leakage current characteristic and solves the problem of increasing metal gate resistance.

Description

Semiconductor structure and manufacturing method

technical field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method.

Background technique

In order to improve the integration of semiconductor chips, the size of semiconductor elements is gradually shrinking, so in order to manufacture more transistors in a limited area, the pattern size and the spacing between patterns are also reduced. It is difficult to secure desired operating characteristics in downsized cell transistors, and in order to solve these difficulties, research and development of buried word lines is booming.

The semiconductor structure shown in FIGS. 1 and 2 includes word lines 11 and active regions 12 , FIG. 2 is a schematic cross-sectional view along line AA' in FIG. 1 , and FIG. 2 shows a liner Bottom 1 , gate dielectric layer 2 , work function metal layer 3 , isolation layer 6 and gate 10 , and isolation layer 6 is located on the top surface of gate 10 . The structure of the buried word line is due to the current leakage caused by GIDL (gate induced drain leakage) in the overlap region of the metal gate and the active N-type junction transistor, which causes the refresh of the GIDL element of the semiconductor element. The characteristic (tREF, Refresh Time) is degraded, and in order to prevent current leakage, the formation method of the buried word line (BW, buried word line) needs to be improved. In order to improve the above-mentioned problems, the previous technology forms a polysilicon film in the overlapping area, but there is a problem that the gate resistance increases, and it is easy to cause defects in the reduced pattern size.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a semiconductor structure and a manufacturing method. In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended to be an extensive review, nor is it intended to identify key/critical elements or delineate the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the detailed description that follows.

According to an aspect of the embodiments of the present application, a semiconductor structure is provided, including:

a substrate having grooves on the substrate;

a gate dielectric layer on the trench wall;

a first gate located in the lower part of the trench;

a second gate on the first gate, wherein the width of the second gate is smaller than that of the first gate;

The isolation layer is located on the upper part of the trench and fills at least a part of the gap between the second gate electrode and the trench.

According to another aspect of the embodiments of the present application, a method for manufacturing a semiconductor structure is provided, including:

providing a substrate;

forming gate trenches on the substrate;

forming a gate dielectric layer on the trench wall;

forming a first gate at the lower part of the trench;

forming a second gate on the first gate; wherein the width of the second gate is smaller than that of the first gate;

An isolation layer is filled in the trench, and the isolation layer is filled into a part of the gap between the second gate electrode and the trench.

According to another aspect of the embodiments of the present application, a semiconductor device is provided, including the above-mentioned semiconductor structure.

According to another aspect of the embodiments of the present application, there is provided an electronic device including the above-mentioned semiconductor structure.

The technical solution provided by one aspect of the embodiments of the present application may include the following beneficial effects:

The semiconductor structure provided by the embodiments of the present application has a first gate and a second gate, the second gate is located on the first gate, the width of the second gate is smaller than that of the first gate, and the width of the second gate is smaller than that of the first gate. There is a space between the two sidewalls and the substrate, and there is a wide space between the active N-junction transistor and the metal and the junction of the overlapping part, which improves the gate-induced drain leakage current characteristics and solves the increase of metal gate resistance. The problem.

Other features and advantages of the present application will be set forth in the description which follows, and, in part, will become apparent from the description, or may be inferred or unambiguously determined from the description, or may be implemented by practice of the present application. example to understand. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description, claims, and drawings.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 shows a schematic diagram of a semiconductor structure in the prior art;

Figure 2 shows a schematic cross-sectional view along the line A-A' in Figure 1;

FIG. 3 shows a schematic diagram of a semiconductor structure according to an embodiment of the present application;

FIG. 4 shows a schematic diagram of a semiconductor structure according to an embodiment of the present application;

FIG. 5 shows a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

FIG. 6 shows a schematic structural diagram of an embodiment of the present application after a trench is formed by etching on a substrate;

FIG. 7 shows a schematic structural diagram of an embodiment of the present application after an oxide layer is formed on the trench;

FIG. 8 shows a schematic structural diagram after forming a work function metal layer according to an embodiment of the present application;

FIG. 9 shows a schematic structural diagram after forming a metal gate according to an embodiment of the present application;

FIG. 10 shows a schematic structural diagram of an embodiment of the present application after depositing a cleaning layer;

FIG. 11 shows a schematic structural diagram of an embodiment of the present application after the cleaning layer is etched;

FIG. 12 shows a schematic structural diagram after depositing a gate layer according to an embodiment of the present application;

FIG. 13 shows a schematic structural diagram after forming the second gate according to an embodiment of the present application;

FIG. 14 shows a schematic structural diagram of an embodiment of the present application after the cleaning layer is removed.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

As shown in FIG. 3, an embodiment of the present application provides a semiconductor structure, including:

Substrate 1, the substrate 1 has grooves;

a gate dielectric layer 2 on the trench wall;

the first gate 4 at the lower part of the trench;

a second gate 5 located on the first gate 4, wherein the width of the second gate 5 is smaller than that of the first gate 4;

The isolation layer 6 is located on the upper part of the trench and fills at least a part of the gap between the second gate 5 and the trench.

In some embodiments, the semiconductor structure further includes a work function metal layer 3 located on the lower part of the inner sidewall of the groove of the gate dielectric layer 2 , and the work function metal layer 3 is sandwiched between the gate dielectric layer 2 and the first gate electrode between 4.

As shown in FIG. 4 , in some embodiments, there is an air gap 9 between the isolation layer 6 , the first gate 4 , the second gate 5 and the gate dielectric layer 2 .

In some embodiments, the material of the isolation layer 6 is silicon nitride.

In some embodiments, the substrate 1 is one of a silicon substrate 1 , a silicon germanium substrate 1 or a III-V compound semiconductor substrate 1 .

In some embodiments, the material of the gate dielectric layer 2 may be SiO ₂ , Si ₃ N ₄ , HfSiOx, HfO ₂ , ZrO ₂ , Al ₂ O ₃ , TiO ₂ , La ₂ O ₃ , SrTiO ₃ , LaAlO ₃ and a material in the group consisting of combinations thereof.

In some embodiments, the material of the work function metal layer 3 can be TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa, NiTa, MoN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi, Ni ₃ Si, Pt, Ru, Ir, Mo, HfRu or RuO _x .

In some embodiments, the first gate 4 and the second gate 5 can be made of W, Co, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, _RuTax , _NiTax , MoN _x , TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi _x , Ni ₃ Si, Pt, Ru, Ir, Mo, HfRu, RuO _x and a combination of the group consisting of a material formed.

The semiconductor structure provided by the embodiments of the present application has a first gate and a second gate, the second gate is located on the first gate, the width of the second gate is smaller than that of the first gate, and the width of the second gate is smaller than that of the first gate. There is a space between the two sidewalls and the substrate, and there is a wide space between the active N-junction transistor and the metal and the junction of the overlapping part, which improves the gate-induced drain leakage current characteristics and solves the increase of metal gate resistance. The problem.

This embodiment also provides a semiconductor device including the above-mentioned semiconductor structure.

This embodiment also provides an electronic device including the above-mentioned semiconductor structure. The electronic devices include smart phones, computers, tablet computers, wearable smart devices, artificial intelligence devices, power banks, and the like.

As shown in FIG. 5 , this embodiment also provides a method for manufacturing a semiconductor structure, including:

S1. A substrate 1 is provided.

S2 , forming a gate trench on the substrate 1 .

In some embodiments, a mask layer is first deposited on the substrate 1 to form a mask layer, and then the substrate 1 is etched to form a trench.

S3, forming a first gate 4 at the lower part of the trench.

In some embodiments, S3, forming the first gate 4 in the lower part of the trench, including:

S31, performing trench oxidation, and forming an oxide layer on the trench;

S32, depositing a work function metal layer 3 on the oxide layer;

S33 , depositing a first gate electrode 4 on the work function metal layer 3 .

S4 , forming a second gate 5 on the first gate 4 ; wherein the width of the second gate 5 is smaller than the width of the first gate 4 .

In some embodiments, S4, forming a second gate 5 on the first gate 4, including:

S41, depositing a cleaning layer 7 (Disposal Layer) on the first gate 4;

S42, performing sidewall dry etching on the cleaning layer 7;

S43, using the same metal deposition material as the first gate electrode 4 to perform etching back by dry etching to form a second gate electrode 5 on the first gate electrode 4;

S44, the cleaning layer 7 is removed.

S5, filling the isolation layer 6 in the trench, and filling the isolation layer 6 into a part of the gap between the second gate 5 and the trench.

In some embodiments, forming the gate trench on the substrate 1 includes:

A gate trench is formed by etching on the substrate 1 using a dry etching process.

In some embodiments, the filling of the isolation layer 6 in the trench includes:

An isolation layer 6 (SiN) is deposited to form an air gap 9 to form a buried word line; wherein, the air gap 9 is located in the isolation layer 6, the first gate 4, the second gate 5 and the gate between the dielectric layers 2.

The first gate 4 and the second gate 5 are both metal gates and have the same material, such as tungsten.

A method for manufacturing a semiconductor structure according to another embodiment of the present application includes:

1. Form a trench, and then form a first gate 4 .

In some embodiments, step 1 specifically includes:

1-1. Taking the top surface of the substrate 1 as a reference, a gate trench is etched on the substrate 1 by a dry etching process, as shown in FIG. 6 . In some embodiments, the mask layer 13 is first deposited on the substrate 1 to form a gate trench, and then the substrate 1 is etched to form a gate trench.

1-2. Perform trench oxidation to form an oxide layer on the trench, as shown in FIG. 7 .

1-3. A work function metal layer 3 is formed by deposition, as shown in FIG. 8 . The material of the work function metal layer 3 may be TiN material.

1-4 After depositing the first gate electrode 4 (W), a metal gate electrode is formed by dry etching back, as shown in FIG. 9 .

2. After the sidewall spacers are formed with the cleaning layer 7, the second gate 5 is formed using the same material as the first time, so as to expand the distance between the N-type junction transistor and the metal gate, and improve the GILD and resistance problems.

In some embodiments, step 2 specifically includes:

2-1. Deposit a cleaning layer 7 (carbon layer or SiN) on the metal gate fabricated for the first time, as shown in Figure 10;

2-2. Perform sidewall dry etching on the cleaning layer 7 (Disposal Layer), as shown in FIG. 11 .

2-3. Use the same metal (W) as that of the first gate electrode 4 to deposit the gate electrode layer 8 , as shown in FIG. 12 .

2-4. The gate layer 8 is etched back by dry etching, so as to form the second gate 5 on the first gate 4, as shown in FIG. 13 .

2-5. The cleaning layer 7 is removed by dry etching or wet etching to expand the distance between the metal gate and the N-type junction transistor, as shown in FIG. 14 .

2-6. After the first and second metal gates are formed, SiN filling and dry etching are performed on the insulating film to form the final buried word line, as shown in Figure 3; or, step coverage is deposited. ) SiN with poor characteristics forms an air gap 9, as shown in FIG. 4, and improves the GIDL defect more effectively.

After the first metal gate deposition and etching, when forming the second gate 5, the sidewall pattern (cleaning layer 7) is used to deposit the same metal as the first etching, so that the N-type junction transistor and the overlapping part can be formed. The metal and junction spacing is widened, improving GIDL characteristics, and solving the problem of increased metal gate resistance.

The manufacturing method provided by this embodiment includes: using a carbon layer or SiN with good step coverage as the cleaning layer 7, forming the second gate 5, etching the sidewall of the cleaning layer 7, depositing the second gate, and using the cleaning layer 7. Layer 7 is the step of forming buried word line metal gate patterns.

The present application provides a method for manufacturing a semiconductor structure with a buried word line structure. After the first gate electrode is deposited and etched, when the second gate electrode 5 is formed, a sidewall pattern (the sidewall pattern is formed by the cleaning layer 7) is used to deposit and After etching the same metal as the first gate, the metal-junction interval between the active N-type junction transistor and the overlapping portion can be widened, the GIDL characteristic can be improved, and the problem of increased metal gate resistance can be solved.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (15)

1. A semiconductor structure, comprising:

a substrate having a trench thereon;

the gate dielectric layer is positioned on the groove wall;

a first gate electrode located at a lower portion of the trench;

a second gate on the first gate, wherein the second gate has a width less than the first gate;

and the isolation layer is positioned at the upper part of the groove and at least fills a part of the gap between the second grid electrode and the groove.

2. The semiconductor structure of claim 1, wherein air gaps are provided between the isolation layer, the first gate, the second gate, and the gate dielectric layer.

3. The semiconductor structure of claim 1, further comprising a work function metal layer between the gate dielectric layer and the first gate electrode.

4. The semiconductor structure of claim 1, wherein the material of the isolation layer is silicon nitride.

5. The semiconductor structure of claim 1, wherein the substrate is one of a silicon substrate, a silicon germanium substrate, or a III-V compound semiconductor substrate.

6. The semiconductor structure of claim 1, wherein the gate dielectric layer is made of an oxide.

7. A method of fabricating a semiconductor structure, comprising:

providing a substrate;

forming a gate trench on the substrate;

forming a gate dielectric layer on the trench wall;

forming a first grid electrode at the lower part of the groove;

forming a second gate on the first gate; the width of the second grid electrode is smaller than that of the first grid electrode;

and filling an isolation layer in the trench, wherein the isolation layer is filled in a part of the gap between the second gate and the trench.

8. The method of claim 7, wherein forming a gate trench on the substrate comprises:

and etching the substrate by using a dry etching process to form a groove.

9. The method of claim 7, wherein forming a first gate in a lower portion of the trench comprises:

performing trench oxidation to form an oxide layer on the trench;

depositing a work function metal layer on the oxide layer;

and depositing and forming a first grid on the work function metal layer.

10. The method of claim 7, wherein forming a second gate over the first gate comprises:

depositing a cleaning layer on the metal grid manufactured for the first time;

performing side wall dry etching on the cleaning layer;

performing back etching in a dry etching mode by using the same metal deposition as the first grid material to form a second grid on the first grid;

and removing the cleaning layer.

11. The method of claim 7, wherein depositing the isolation layer forms a buried word line, comprising:

depositing an isolation layer for complete filling;

and carrying out dry back etching on the isolation layer to form the buried word line.

12. The method of claim 7, wherein depositing the isolation layer forms a buried word line, comprising:

depositing an isolation layer to form an air gap and form a buried word line; the air gaps are located among the isolation layer, the first grid electrode, the second grid electrode and the grid dielectric layer.

13. A semiconductor device comprising the semiconductor structure of any one of claims 1 to 6.

14. An electronic device comprising the semiconductor structure of any one of claims 1 to 6.

15. The electronic device of claim 14, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

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