CN111900168A - Memory cells, memory devices and electronic equipment - Google Patents

Abstract

A storage unit, a storage device and an electronic device are disclosed. According to an embodiment, the memory cell may include: a transistor; and a capacitive component connected with the transistor, wherein the capacitive component includes a positive capacitor and a negative capacitor connected in series with each other. The capacitor component is formed as a trench capacitor, and the shape of the trench is U-shaped, including two vertical sidewalls and a bottom wall connecting the vertical sidewalls; the capacitor component includes a first conductive layer-dielectric layer-second conductive layer- A stack of negative capacitance material layers-third conductive layers; and each conductive layer includes a metal electrode material layer.

Description

Memory cells, memory devices and electronic equipment

This case is a divisional application of the parent application with the application number of "201610048641.3", the filing date of January 25, 2016, and the name of the invention "memory unit, storage device and electronic equipment". The entire content of the parent case is included by reference here.

technical field

The present disclosure relates to the field of storage, and more particularly, to a storage unit with a large storage capacitance, a storage device including the storage unit, and an electronic device including the storage device.

Background technique

Capacitors are often used in memory devices to store charge in order to store data. However, with the continuous miniaturization of devices, the area of the chip used to form the capacitor has continued to shrink, so that the capacitance value of the capacitor has become smaller. In order to ensure memory performance, it is desirable to obtain as large a capacitance as possible without occupying an excessively large chip area.

SUMMARY OF THE INVENTION

An object of the present disclosure is, at least in part, to provide a memory cell having a large storage capacitance, a memory device including the memory cell, and an electronic device including the memory device.

According to one aspect of the present disclosure, there is provided a memory cell including: a transistor; and a capacitance component connected with the transistor, wherein the capacitance component includes a positive capacitor and a negative capacitor connected in series with each other.

According to another aspect of the present disclosure, there is provided a memory device including the above-described memory cell.

According to yet another aspect of the present disclosure, there is provided an electronic device including the above-mentioned storage device.

According to an embodiment of the present disclosure, a storage capacitor assembly is formed using a series combination of a negative capacitor and a conventional capacitor (or, in other words, a positive capacitor). Compared with conventional storage capacitors, such capacitor components can realize large storage capacitors under the same footprint.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG. 1 is a schematic circuit diagram illustrating a memory cell according to an embodiment of the present disclosure;

2(a)-2(g) are cross-sectional views illustrating some stages in a flow of manufacturing a memory cell according to an embodiment of the present disclosure;

3 is a cross-sectional view illustrating a configuration of a memory cell according to another embodiment of the present disclosure;

4(a)-4(d) are cross-sectional views illustrating some stages in a process of manufacturing a memory cell according to another embodiment of the present disclosure;

5 is a cross-sectional view illustrating a configuration of a memory cell according to another embodiment of the present disclosure.

Throughout the drawings, the same reference numerals are used to refer to the same or like parts.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element can be "under" the other layer/element.

FIG. 1 is a schematic circuit diagram illustrating a memory cell according to an embodiment of the present disclosure.

As shown in FIG. 1 , the memory cell 100 according to this embodiment includes a transistor 101 and a capacitance component 103 connected to the transistor. For example, such memory cells may constitute dynamic random access memory (DRAM) cells in a 1T1C configuration.

Transistor 101 may include various forms of transistors, such as various forms of metal oxide semiconductor field effect transistors (MOSFETs), such as fin field effect transistors (FinFETs), semiconductor-on-insulator (SOI) MOSFETs, nanowire field effect transistors ( nanowire FET) and so on.

Generally, transistor 101 may include a gate, a source and a drain. In the example of FIG. 1 , the gate may be connected to the terminal T1 , one of the source/drain may be connected to the terminal T2 , and the other of the source/drain may be connected to the capacitive component 103 . The other end of the capacitance component 103 is connected to the terminal T3. Thus, in this example, the transistor 101 is connected in series with the capacitive component 103 .

The capacitive component 103 may include a conventional capacitor (or, a positive capacitor) 1031 and a negative capacitor 1033 connected in series. Typically, capacitors include a plate-dielectric layer-plate configuration, where the dielectric layer can store charge. Conventional capacitors exhibit "positive" capacitive characteristics, that is, as the charge stored in the dielectric layer increases, the voltage across the two plates increases. In this disclosure, such a dielectric layer is referred to as a conventional dielectric layer, or simply simply a dielectric layer, as the term has the conventional meaning in the art. In contrast, some materials can exhibit "negative" capacitive properties under certain conditions, that is, as the stored charge increases, the voltage between the plates appears to decrease instead. Such materials are referred to as "negative capacitance materials". For example, some ferroelectric materials (such as Zr, Ba or Sr-containing materials, such as HfZrO ₂ , BaTiO ₃ , KH ₂ PO ₄ or NBT, etc.) can polarize when they reach a certain critical electric field. The polarization causes a large amount of bound charges to accumulate on the surface of the material instantaneously, reducing the voltage across the ferroelectric material.

Due to the series relationship, the capacitance C _t of the capacitive component 103 can be expressed as:

C _t =|C _n |C/(|C _n |-C),

Here, C is the capacitance value of the positive capacitor 1031, C _n is the capacitance value of the negative capacitor 1033 (a negative value as described above), and |C _n | represents the absolute value of C _n . According to the above formula, it can be seen that when |C _n | is approximately equal to C, C _t can tend to infinity. Of course, this is an ideal situation, and in practice, a relatively large capacitance _Ct (eg, about 2-5 times the absolute value of C) can also be achieved. Preferably, |C _n |>C.

In view of the stacked configuration of the capacitors and the series connection relationship, the capacitor component 103 may be formed in a stacked form of a first conductive layer-dielectric layer-second conductive layer-negative capacitance material layer-third conductive layer. At this time, the first conductive layer-dielectric layer-second conductive layer can form a positive capacitor 1031, and the second conductive layer-negative capacitive material layer-third conductive layer can form a negative capacitor 1033, and since the common second conductive layer , they form a series connection. Alternatively, the capacitive component 103 may be formed in the form of a stack of the first conductive layer-dielectric layer-negative capacitive material layer-third conductive layer. At this time, the first conductive layer and the third conductive layer constitute two pole plates of the capacitor component 103 , and the combination of the dielectric layer and the negative capacitance material layer constitutes the capacitive medium of the capacitor component 103 .

According to embodiments of the present disclosure, the capacitive components may be formed in the form of trench capacitors. In a limited area, trench capacitors can increase the opposing plate area of the capacitor and thus increase the capacitance value. For example, trenches may be formed in the substrate in which the transistors are formed, or in one or more layers of a metallization stack over the transistors, and capacitive components may be formed in the trenches. The layers in the capacitor stack configuration may extend along the side and bottom walls of the trench.

Each of the conductive layers (the first conductive layer, the second conductive layer, and the third conductive layer) may include various suitable conductive materials, such as metals, metal nitrides, and the like. For better compatibility with semiconductor processes, the conductive materials may include materials used in semiconductor processes to form conductive contacts, such as conductive diffusion barrier materials such as TiN and metal electrode materials such as W, and the like. Metal electrode materials can form low ohmic contacts, making them suitable for conductive layers (eg, the first conductive layer or the third conductive layer) that need to form connections to other components. In addition, in order to avoid the diffusion of the metal electrode material, a conductive diffusion barrier material layer may be used in conjunction therewith.

Furthermore, when forming the trench capacitor in the substrate, the outermost layer of the capacitor (either the first conductive layer or the third conductive layer) may be formed using the doped regions in the substrate. In this case, the doped region can be directly connected to one of the source/drain of the transistor (which can also be the doped region) and thus connect the capacitive component to the transistor.

It should be pointed out here that although the 1T1C configuration is used as an example to describe the memory cell, the present disclosure is not limited thereto. The capacitive assemblies disclosed herein can be applied to any application requiring large capacitance, including various forms of capacitor-based storage devices.

According to an embodiment of the present disclosure, there is also provided a memory device that may include a plurality of such memory cells. For example, memory cells may be arranged in a two-dimensional array, each memory cell's terminal T1 may be connected to a word line, terminal T2 may be connected to a bit line, and terminal T3 may be connected to a common potential (eg, ground). Through the word line, a row of memory cells corresponding to the bit line can be selected; through the bit line, data can be written or read into the memory cells corresponding to the bit line in the selected row. Of course, the memory device can also be implemented in various other configurations.

2(a)-2(g) are cross-sectional views illustrating some stages in a flow of manufacturing a memory cell according to an embodiment of the present disclosure.

As shown in Fig. 2(a), a substrate 1001 is provided. Here, the description is made by taking the fabrication of an n-type transistor as an example, so the substrate 1001 can be a p-type lightly doped silicon wafer. However, the present disclosure is not limited thereto. The substrate 1001 may include various suitable substrates, such as semiconductor-on-insulator (SOI) substrates, compound semiconductors such as SiGe, and the like.

In substrate 1001, as described above, trenches may be formed to form capacitive components therein.

To this end, as shown in FIG. 2( a ), a hard mask layer may be formed on the substrate 1001 . In this example, the hard mask layer includes an oxide (eg, silicon oxide) layer 1003 and a nitride (eg, silicon nitride) layer 1005 . For example, the thickness of the oxide layer 1003 is about 5-20 nm, and the thickness of the nitride layer 1005 is about 50-200 nm. A patterned (eg, photolithographic by exposure, development) photoresist 1007 may be formed on the hard mask layer. Here, the photoresist 1007 is patterned to have openings corresponding to the trenches to be formed.

Then, as shown in FIG. 2(b), the patterned photoresist 1007 may be used as a mask to pattern the hard mask layers (1005, 1003), such as reactive ion etching (RIE), to remove the photoresist The pattern of 1007 is transferred into the hard mask layers (1005, 1003). Next, the substrate 1001 may be patterned, eg, RIE, to form trenches R therein, using the hard mask layers ( 1005 , 1003 ) as masks. Subsequently, a capacitor element will be formed in the trench R. After the trench R is formed, the photoresist 1007 may be removed. Here, the hard mask layer may not be removed first, so as to protect the surface of the substrate 1001 .

In this example, portions of the substrate 1001 proximate the sidewalls and bottom walls of the trench R may be doped to form doped regions (ie, conductive regions) extending along the sidewalls and bottom walls of the trench R, And thus constitute a pole plate of the capacitor assembly (for example, the above-mentioned first conductive layer). Such doped regions can be formed, for example, as follows. Specifically, as shown in FIG. 2( c ), on the substrate 1001 on which the trench R is formed (here, a hard mask layer helps to form dopant extending along the sidewall and bottom wall of the trench R region), a dopant source layer 1009 may be formed (eg, by deposition). The dopant source layer refers to a material layer containing a dopant. For example, the dopant source layer 1009 may include an oxide doped with an n-type dopant such as As or P. The thickness of the dopant source layer 1009 may not fill the trench R, so it extends along the side and bottom walls of the trench R. Preferably, the dopant source layer 1009 may be deposited in a substantially conformal manner. Subsequently, an anneal may be performed to drive the dopants in the dopant source layer 1009 into the substrate 1001 . Since the dopant source layer 1009 is arranged along the sidewall and bottom wall of the trench R, the n-type doped region 1011 is formed along the sidewall and the bottom wall of the trench R. Afterwards, the dopant source layer 1009 may be removed, as shown in FIG. 2(d).

It should be pointed out here that the doped regions may be formed in various other suitable manners (eg, ion implantation).

Next, the trenches R may be filled with layers of materials to form a stacked configuration of capacitive components. In this example, after forming the n-type doped region 1011 as the first conductive layer as described above, the trench R may be filled with a dielectric layer, a second conductive layer, a negative capacitance material layer and a third conductive layer in sequence, to form capacitive components.

Specifically, as shown in FIG. 2( e ), a high-K dielectric layer 1013 , a conductive diffusion barrier layer 1015 , a negative capacitance material layer 1017 , a conductive diffusion barrier layer 1019 and a metal electrode material layer may be sequentially formed in the trench R 1021. For example, the high-K dielectric layer 1013 may include HfO ₂ with a thickness of about 1-10 nm. At this time, an interface layer (not shown), such as an oxide layer, may be formed on the sidewalls and bottom walls of the trench R, with a thickness of about 0.5-5 nm, and then a high-K dielectric layer 1013 is formed on the interface layer. Alternatively, instead of the high-K dielectric layer 1013, an oxide layer may be formed, eg, with a thickness of about 2-10 nm. For example, the conductive diffusion barrier layer 1015 may include TiN with a thickness of about 1-10 nm; the negative capacitance material layer 1017 may include HfZrO ₂ with a thickness of about 3-15 nm; the conductive diffusion barrier layer 1019 may include TiN with a thickness of about 2 nm ~10 nm; the metal electrode material layer 1021 may include W, and its thickness may fill the trench R. In this case, the n-type doped region 1011 (first conductive layer)-high-K dielectric layer 1013 (dielectric layer)-conductive diffusion barrier layer 1015 (second conductive layer) can constitute a positive capacitor; the conductive diffusion barrier layer 1015 (second conductive layer)-negative capacitance material layer 1017-conductive diffusion barrier layer 1019 and metal electrode material layer 1021 (third conductive layer) may constitute a negative capacitor. Here, the third conductive layer includes a metal electrode material layer 1021, which is to better form a low-ohmic contact with a subsequently formed contact (see 1035-3 in FIG. 2(g) ); the conductive diffusion barrier layer 1019 Diffusion of the metal electrode material layer 1021 into the negative capacitance material layer 1017 can be avoided. For example, the high-K dielectric layer 1013, the conductive diffusion barrier layer 1015, the negative capacitance material layer 1017, the conductive diffusion barrier layer 1019, and the metal electrode material layer 1021 can be deposited in sequence in a substantially conformal manner to fill the The trenches R are then filled with these layers by planarization such as chemical mechanical polishing (CMP) (with a hard mask layer as a stop) followed by an etch back.

In this example, the dielectric layer 1013 is formed first, and then the negative capacitance material layer 1017 is formed. However, the present disclosure is not limited thereto. For example, the layer of negative capacitance material may be formed first, followed by the formation of the dielectric layer.

After the capacitive components are formed, the hard mask layer can be removed and transistors formed on the substrate 1001 . There are many ways in the art to form various forms of transistors, such as MOSFETs, which will not be repeated here. Figure 2(f) shows an example of a transistor. As shown in FIG. 2( f ), the transistor may include a gate stack (including a gate dielectric layer 1025 and a gate electrode layer 1027 ), gate spacers 1029 formed around the gate stack, and source/drain regions 1031 . In addition, shallow trench isolation (STI) 1023 is also shown in FIG. 2(f). In this example, the transistor is an n-type device whose source/drain regions 1031 are in the form of n-type doped regions in the substrate 1001 . One of the source/drain regions of the transistor (in this example, the source/drain region on the right in Fig. 2(f)) extends to meet the n-type doped region 1011, thereby realizing the connection between the transistor and the capacitive component .

Contacts with other components may also be formed. For example, as shown in FIG. 2(g), an interlayer dielectric layer 1033 (eg, nitride) may be formed on the substrate on which transistors and capacitor components are formed as shown in FIG. 2(f). In the interlayer dielectric layer 1033, at positions corresponding to the gate of the transistor, the other of the source/drain regions (the one not connected to the capacitive component), and the capacitive component (specifically, the metal electrode material layer 1021), for example Contacts 1035-1, 1035-2, and 1035-3 are formed by etching, forming contact holes, and filling the contact holes with a layer of conductive material (eg, a metal contact material such as W). Of course, the (conductive) diffusion barrier layer can also be formed on the sidewall and bottom wall of the contact hole first, and then the metal contact material layer is filled. The contact portions 1035-1, 1035-2, and 1035-3 may correspond to the terminals T1, T2, and T3 in FIG. 1, respectively.

3 is a cross-sectional view illustrating a configuration of a memory cell according to another embodiment of the present disclosure.

The memory cell shown in FIG. 3 is substantially the same as the memory cell shown in FIG. 2( g ), except that the conductive diffusion barrier layer 1015 as the second conductive layer is omitted. In this example, the n-type doped region 1011 (the first conductive layer) constitutes one pole plate of the capacitor component, and the conductive diffusion barrier layer 1019 and the metal electrode material layer 1021 (the third conductive layer) constitute the other pole of the capacitor component plate, and the stack of the high-K dielectric layer 1013 (dielectric layer) and the negative capacitance material layer 1017 constitutes the capacitive medium of the capacitive component. Likewise, the order of the high-K dielectric layer 1013 and the negative capacitance material layer 1017 can be swapped.

In the above embodiments, the capacitor element is formed on the substrate like the transistor. However, the present disclosure is not limited thereto. For example, capacitive components may also be formed in metallization stacks.

4(a)-4(d) are cross-sectional views illustrating some stages in a process of manufacturing a memory cell according to another embodiment of the present disclosure.

As shown in FIG. 4( a ), transistors may be formed on the substrate 2001 . There are many ways in the art to form various forms of transistors, such as MOSFETs, which will not be repeated here. Figure 4(a) shows an example of a transistor. As shown in FIG. 4( a ), the transistor may include a gate stack (including a gate dielectric layer 2025 and a gate electrode layer 2027 ), gate spacers 2029 formed around the gate stack, and source/drain regions 2031 . In addition, shallow trench isolation (STI) 2023 is also shown in FIG. 4(a).

An interlayer dielectric layer 2033 may be formed on the substrate on which the transistors are formed, and contacts 2035-1, 2035-2, and 2035-3. Regarding the interlayer dielectric layers and the contacts, reference can be made to the above description.

Next, as shown in FIG. 4( b ), another interlayer dielectric layer 2037 (eg, nitride) may be formed on the interlayer dielectric layer 2033 . In the interlayer dielectric layer 2037, for example, by etching, a trench R1 can be formed, and then a capacitor element can be formed in the trench R1. In this example, the position of the trench R1 corresponds to the source/drain region to which the capacitive element is to be connected (the source/drain region on the right in FIG. 4(b) ), and penetrates the interlayer dielectric layer 2037 to expose the Contacts 2035-3 corresponding to the source/drain regions.

Subsequently, various material layers may be filled into the trench R1 to form a capacitor component. In this example, for example, a conductive diffusion barrier layer 2039 (eg, TiN, with a thickness of about 1-10 nm, which can be formed by atomic layer deposition (ALD)), a metal electrode material layer 2041 ( For example, W, with a thickness of about 5-50 nm, can be formed by ALD, chemical vapor deposition (CVD), etc.), a conductive diffusion barrier layer 2043 (eg, TiN, with a thickness of about 1-10 nm, can be formed by ALD), Negative capacitance material layer 2045 (for example, HfZrO ₂ with a thickness of about 3-15 nm, which can be formed by ALD), a conductive diffusion barrier layer 2047 (for example, TiN, with a thickness of about 1-10 nm, which can be formed by ALD), high K dielectric layer 2049 (eg HfO ₂ with a thickness of about 3-15 nm, which can be formed by ALD), conductive diffusion barrier layer 2051 (eg, TiN, with a thickness of about 1-10 nm, which can be formed by ALD), and metal electrode materials Layer 2053 (eg W, which can be formed by ALD, CVD, etc.). In this case, the conductive diffusion barrier layer 2039, the metal electrode material layer 2041, and the conductive diffusion barrier layer 2043 (first conductive layer)-negative capacitance material layer 2045-conductive diffusion barrier layer 2047 (second conductive layer) may be form a negative capacitor. Here, the first conductive layer includes a metal electrode material layer 2041, which is to better form a low-ohmic contact with the lower contact portion 2035-3; the conductive diffusion barrier layer 2039 and the conductive diffusion barrier layer 2043 can avoid metal electrodes Material layer 2041 diffuses into other layers (eg, negative capacitance material layer 2045). In addition, the conductive diffusion barrier layer 2047 (second conductive layer)-high-K dielectric layer 2049-conductive diffusion barrier layer 2051 and metal electrode material layer 2053 (third conductive layer) may form a positive capacitor. Here, the third conductive layer includes a metal electrode material layer 2053, which is to better form a low-ohmic contact with a subsequently formed contact (see 2059-3 in FIG. 4(d) ); the conductive diffusion barrier layer 2051 Diffusion of the metal electrode material layer 1021 into other layers can be avoided. For example, conductive diffusion barrier layer 2039, metal electrode material layer 2041, conductive diffusion barrier layer 2043, negative capacitance material layer 2045, conductive diffusion barrier layer 2047, high-K dielectric layer may be sequentially deposited in a substantially conformal manner 2049. Conductive diffusion barrier layer 2051, and deposit a metal electrode material layer 2053 to fill trench R1, and then perform a planarization process such as CMP to fill trench R1 with these layers.

In this example, the negative capacitance material layer 2045 is formed first, and then the dielectric layer 2049 is formed. However, the present disclosure is not limited thereto. For example, the layer of negative capacitance material may be formed first, followed by the formation of the dielectric layer.

Furthermore, as shown in FIG. 4(d), in the 0 interlayer dielectric layer 2037, contact portions 2055-1 and 2055-2 corresponding to the contact portions 2035-1 and 2035-2 may be formed. Afterwards, another interlayer dielectric layer 2057 (eg, nitride) may be formed. In the interlayer dielectric layer 2057, contact portions 2059-1, 2059-2, and 2059-3 corresponding to the contact portions 2055-1 and 2055-2 and the capacitance component (specifically, the metal electrode material layer 2053) may be formed. The contact portions 2059-1, 2059-2, and 2059-3 may correspond to the terminals T1, T2, and T3 in FIG. 1, respectively.

5 is a cross-sectional view illustrating a configuration of a memory cell according to another embodiment of the present disclosure.

The memory cell shown in FIG. 5 is substantially the same as the memory cell shown in FIG. 4(d), except that the conductive diffusion barrier layer 2047 as the second conductive layer is omitted. In this example, the conductive diffusion barrier layer 2039, the metal electrode material layer 2041 and the conductive diffusion barrier layer 2043 (the first conductive layer) constitute one electrode plate of the capacitor assembly, the conductive diffusion barrier layer 2051 and the metal electrode material layer 2053 The (third conductive layer) constitutes the other plate of the capacitor element, and the stack of the negative capacitance material layer 2045 and the high-K dielectric layer 2049 constitutes the capacitor medium of the capacitor element. Likewise, the order of the negative capacitance material layer 2045 and the high-K dielectric layer 2049 can be swapped.

The memory device according to the embodiment of the present disclosure may be applied to various electronic devices. Such electronic devices are, for example, smart phones, tablet computers (PCs), personal digital assistants (PDAs), and the like.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (14)

1. A storage unit, comprising: transistors; and A capacitive component connected to this transistor, The capacitive assembly includes a positive capacitor and a negative capacitor connected in series with each other; Wherein, the capacitor component is formed as a trench capacitor, and the shape of the trench is U-shaped, including two vertical sidewalls and a bottom wall connecting the vertical sidewalls; The capacitor assembly includes a stack of a first conductive layer-dielectric layer-second conductive layer-negative capacitance material layer-third conductive layer; and each conductive layer includes a metal electrode material layer. 2. The memory cell according to claim 1, wherein the material of the negative capacitance material layer is a material containing Zr, Ba or Sr. 3. The memory cell of claim ₁ , wherein the material of the negative capacitance material layer comprises one of the following: _HfZrO2 , BaTiO3, _KH2PO4 or NBT _. 4. The memory cell of claim 1, wherein the absolute value of the capacitance of the negative capacitor is greater than or equal to the capacitance value of the positive capacitor. 5. The memory cell of claim 1, wherein the capacitive component is formed on a substrate on which the transistor is formed, and the first conductive layer or the third conductive layer includes a doped region in the substrate. 6. The memory cell of claim 5, wherein the doped region is connected to one of the source/drain regions of the transistor, thereby connecting the capacitive component to the transistor. 7. The memory cell of claim 1, wherein the second conductive layer comprises a conductive diffusion barrier material layer. 8. The memory cell of claim 1, wherein at least one of the first conductive layer and the third conductive layer comprises a stack of a conductive diffusion barrier material layer and a metal electrode material layer. 9. The memory cell of claim 7 or 8, wherein the conductive diffusion barrier material layer comprises TiN. 10. The memory cell of claim 8, wherein the metal electrode material layer comprises W. 11. The memory cell of claim 8, wherein the capacitive component is formed in a metallization stack over a transistor. 12. The memory cell of claim 11, wherein the first conductive layer or the third conductive layer adjacent to the lower layer comprises a stack of a conductive diffusion barrier material layer-metal electrode material layer-conductive diffusion material layer. 13. A memory device comprising a plurality of memory cells as claimed in any one of claims 1-12. 14. An electronic device comprising the memory device of claim 13.

Images