CN111899783A

CN111899783A - High-speed MRAM chip using write detection and data read-write method thereof

Info

Publication number: CN111899783A
Application number: CN201910374099.4A
Authority: CN
Inventors: 戴瑾
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2019-05-06
Filing date: 2019-05-06
Publication date: 2020-11-06
Anticipated expiration: 2039-05-06
Also published as: CN111899783B

Abstract

The invention discloses a high-speed MRAM chip utilizing write detection and a data read-write method thereof, wherein the MRAM chip comprises an MRAM main storage unit and a plurality of peripheral circuits, the peripheral circuits comprise an address decoder, a read-write controller and an input-output controller, and the MRAM chip also comprises a write-in register, a write-in detection circuit, an error correction controller and an error correction redundant unit; the MRAM main storage unit and the peripheral circuit are used for cooperatively executing read-write operation; the write-in register is used for temporarily storing an address to be written in and data to be written in the address; the write detection circuit is used for sending an error signal when a write operation failure condition is detected; the error correction controller is provided with a write queue and an error correction address storage unit for storing an error address and a corresponding replacement address. The invention utilizes the write-in state detection circuit, and combines the error correction redundant unit on the basis of the ECC check detection circuit, thereby further improving the error correction capability and further improving the read-write speed of the MRAM.

Description

High-speed MRAM chip using write detection and data read-write method thereof

Technical Field

The invention relates to the field of semiconductor chips, in particular to a high-speed MRAM chip utilizing write detection and a data read-write method thereof.

Background

MRAM is a new memory and storage technology, can be read and written randomly as SRAM/DRAM, and can permanently retain data after power failure as Flash memory.

The method has good economy, occupies small silicon chip area per unit volume, and has great advantages compared with SRAM; the number of additional photomasks required in the manufacturing process is small, and the cost advantage is larger than that of the embedded NOR Flash. Its performance is also quite good, the read-write time delay is close to SRAM, and the power consumption is much lower than that of flash memory. Also MRAM is not compatible with standard CMOS semiconductor processes like DRAM and Flash. The MRAM may be integrated with the logic circuit in one chip. The principle of MRAM is based on a structure called MTJ (magnetic tunnel junction). It consists of two layers of ferromagnetic material sandwiching a very thin layer of non-ferromagnetic insulating material, as shown in fig. 1 and 2.

The lower layer of ferromagnetic material is a reference layer with a fixed magnetization direction and the upper layer of ferromagnetic material is a variable magnetization direction memory layer whose magnetization direction can be parallel or anti-parallel to the fixed magnetization layer (as shown in fig. 1 and 2). Due to quantum physical effects, current can pass through the middle tunnel barrier layer, but the resistance of the MTJ is related to the magnetization direction of the variable magnetization layer. The former case has a low resistance and the latter case has a high resistance.

The process of reading the MRAM is to measure the resistance of the MTJ. Using the newer STT-MRAM technology, writing to MRAM is also simpler: write operations are performed through the MTJ using a stronger current than read. A bottom-up current places the variable magnetization layer in a parallel direction to the fixed layer (as shown in fig. 1) and a top-down circuit places it in an anti-parallel direction (as shown in fig. 2).

To achieve the goal of replacing DRAM, and partially replacing SRAM, MRAM has a speed that is inadequate. The read-out speed can be made fast, but the write-in speed is physically limited by the write pulse length.

Shortening the write pulse does not necessarily cause a write failure, but only gradually the error rate rises to an unacceptable level. Therefore, as long as the error correction capability of the chip is improved, the writing speed can be greatly improved.

The U.S. patent publication No. US20180061466a1, which is the most advanced concept in the industry at present, proposes:

1. a writing state detection circuit is added in the MRAM, and when the written bit is detected to reach the target state, the writing operation is terminated in advance;

2. a reference cell is required, having a reference resistance;

3. a write detection circuit for determining its current state by comparing the resistance of the written cell with a reference resistance;

4. the specific implementation method is that the same voltage of the written unit is applied to the reference unit, the potential of the same point on the written circuit is compared, the resistance of the written unit is different, the circuit voltage division is inevitably different, and the point position on the detected point is changed.

However, the above-mentioned us patent has a significant problem, which makes it impossible or very difficult to apply its idea to products; that is how the reference cell is constructed.

1. If a fixed resistor is used as the reference cell, the process results in different on-chip MTJ resistance distributions (inter-chip non-uniformity and intra-chip non-uniformity) on different wafers and the same wafer. The production flow is very complicated by using fixed or adjustable resistors;

2. if a reference cell is constructed by using memory cells in a chip, in the architecture of a single reference cell, the resistance of the reference cell must be a certain value between the average resistances of a P-state (magnetization directions are parallel, corresponding to a low resistance state) and an AP-state (magnetization directions are antiparallel, corresponding to a high resistance state), and only one set of reference cells in the P-state and one set of reference cells in the AP-state can be used for parallel averaging, such as most of the reading circuits. Then the problem that applying the same write voltage to the reference cells, regardless of the direction, will certainly have some of the reference cells to be written, changing state and resulting in lost reference value;

3. using a single reference cell, avoiding false positives becomes a serious problem. Due to various deviations in the chip including measurement errors, some cells that do not complete a write operation are erroneously determined to be a write operation, which may cause a chip error, and the tolerance for the error is very low for a memory chip.

Another US patent with publication number US10115446 proposes an error buffer for the first time, but the only way provided is how to detect a write error and how to judge it, which is to perform a read operation after the write operation, and which has a great influence on the speed and power consumption.

Disclosure of Invention

In order to solve the problems in the prior art, the writing state detection circuit is utilized, and on the basis of the ECC check detection circuit, the error correction redundancy unit is combined, so that the writing speed is increased, the error correction capability is further improved, and the reading and writing speed of the MRAM is further improved. The technical scheme is as follows:

in one aspect, the invention provides a high-speed MRAM chip using write detection, comprising an MRAM main storage unit and a plurality of peripheral circuits, wherein the peripheral circuits comprise an address decoder, a read-write controller and an input-output controller, and the MRAM chip further comprises a write register, a write detection circuit, an error correction controller and an error correction redundancy unit;

the MRAM main storage unit and the peripheral circuit are used for cooperatively executing read-write operation;

the write-in register is used for temporarily storing an address to be written in and data to be written in the address;

the write detection circuit is used for sending an error signal to the error correction controller when a write operation failure condition of the MRAM main storage unit and/or the peripheral circuit is detected, wherein the error signal comprises an error address of data of the failed write operation stored in the MRAM main storage unit;

the error correction controller is provided with a write queue and an error correction address storage unit, responds to a received error signal, controls to put the data corresponding to the failed write operation in the write register into the write queue, further generates a request for writing the data into a replacement address of the error correction redundant unit, and stores the data of the failed write operation in an error address of the MRAM main storage unit and the corresponding replacement address into the error correction address storage unit.

Further, the write queue in the error correction controller also has an address, and if the address in the read instruction received by the MRAM chip is the address of the write queue, the data corresponding to the address in the write queue is returned.

Furthermore, the MRAM chip also comprises a high-resistance state writing reference unit for providing a reference electrical signal for judging whether the MRAM main storage unit is in a high-resistance state or not and a low-resistance state writing reference unit for providing a reference electrical signal for judging whether the MRAM main storage unit is in a low-resistance state or not, and the writing detection circuit receives output signals of the high-resistance state writing reference unit and the low-resistance state writing reference unit and corresponding detection signals in a writing loop of the MRAM main storage unit; when the MRAM main storage unit is set to be in a high-resistance state, the writing detection circuit compares a detection signal of the MRAM main storage unit with a signal provided by the high-resistance state writing reference unit and judges, and when the MRAM main storage unit is judged to be in the high-resistance state, the writing detection circuit sends a writing operation termination signal; when the MRAM main storage unit is set to be in a low-resistance state, the writing detection circuit compares a detection signal of the storage unit with a signal provided by the low-resistance state writing reference unit and judges, and when the storage unit is judged to be in the low-resistance state, the writing detection circuit sends out a signal for stopping writing operation.

Further, the write detection circuit includes:

the reference signal selector is used for receiving output signals of the high-resistance state writing reference unit and the low-resistance state writing reference unit and selectively outputting signals provided by the high-resistance state writing reference unit or the low-resistance state writing reference unit according to the type of writing operation of the storage unit;

the comparator is used for receiving the output signal of the reference signal selector and a detection point signal in a write-in loop of the storage unit, comparing the output signal with the detection point signal and outputting a corresponding signal;

and the termination write operation controller is connected with the comparator, generates a corresponding control signal according to the output signal of the comparator and provides the control signal for the module for controlling the write operation so as to terminate or continue the write operation of the current storage unit.

Further, if the write detection circuit detects that the write operation has been completed before the write pulse is terminated, the write operation is terminated early; and if the write operation is not detected to be completed when the write pulse is cut off to the end, outputting an error reporting signal to the error correction controller.

Preferably, the MRAM main memory unit and the error correction redundancy unit both include an ECC check detection circuit.

In another aspect, the present invention provides a data reading method based on the MRAM chip, including the following steps:

the MRAM chip sends a received reading instruction to an error correction controller, wherein the reading instruction comprises a reading address;

the error correction controller compares the read address with an error address stored in an error correction address storage unit and an address in a write queue;

if the read address is in the error address, matching a corresponding replacement address, and returning data of the replacement address in the error correction redundancy unit;

if the read address is in the address in the write queue, returning the data of the address in the write queue;

otherwise, the data of the read address in the MRAM main storage unit is returned.

In another aspect, the present invention provides a data writing method based on the MRAM chip, including the following steps:

the MRAM chip sends a received writing instruction to an error correction controller, wherein the writing instruction comprises a writing address and data to be written;

the error correction controller compares the write address with an error address stored in an error correction address storage unit and addresses in a write queue;

if the write address is in the error address or the write queue, replacing the data of the write address in the MRAM main storage unit with the data to be written in the write instruction at this time, and deleting the address in the write queue, the error address stored in the error correction address storage unit, the replacement address and the data of the replacement address in the error correction redundant unit;

and if the write address is not in the error address or the write queue, writing the data to be written in the write address in the MRAM main storage unit.

Further, the data writing method of the MRAM chip further includes the following operations after the data to be written is written at the write address in the MRAM main storage unit:

the write detection circuit detects the write operation condition, and if the write operation fails, an error report signal is sent to the error correction controller;

responding to the error reporting signal, the error correction controller puts the data to be written in the write-in queue of this time temporarily stored in the write-in register, and the error correction controller stores the write-in address in the MRAM main storage unit as an error address into the error correction address storage unit;

the write-in queue generates a write-in request, and the data to be written is written into the spare replacement address in the error correction redundancy unit;

and the error correction controller stores the replacement address into the error correction address storage unit and associates the corresponding error address.

Further, the invention judges the failure of the write operation by the following method:

and if the number of error bits generated by the write operation exceeds a preset value, judging that the write operation fails.

The high-speed MRAM chip utilizing write detection provided by the invention can produce the following beneficial effects:

a. the problem of error is solved while high-speed writing is ensured;

b. a reliable write detection circuit capable of mass production;

c. and the addition of error correction redundant storage is more economical than enhancing the error correction function of ECC. The latter needs to further add error-correcting Bit magnetic tunnel junction and MOS tube on each word;

d. the application is in the fields of Internet of things, wearable electronic equipment and the like with strict requirements on standby power consumption.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art magnetic tunnel junction with a variable magnetization layer placed parallel to a fixed layer;

FIG. 2 is a schematic diagram of a prior art magnetic tunnel junction with a variable magnetization layer placed antiparallel to the fixed layer;

FIG. 3 is a schematic diagram of a memory cell of an MRAM provided in the prior art;

FIG. 4 is a diagram illustrating a structure of an MRAM chip according to the prior art;

FIG. 5 is a diagram illustrating a structure of an MRAM chip using a high-resistance state or low-resistance state memory cell on the chip as a reference cell in the prior art;

FIG. 6 is a schematic diagram of a high speed MRAM chip utilizing write sensing according to an embodiment of the invention;

FIG. 7 is a schematic diagram of a write circuit with write detection according to an embodiment of the present invention;

FIG. 8 is a flowchart of a method for reading data from a high speed MRAM chip using write sensing according to an embodiment of the invention;

FIG. 9 is a flowchart of a method for writing data in a high speed MRAM chip using write sensing according to an embodiment of the invention;

FIG. 10 is a graph of the distribution of the P-state and AP-state resistances of a magnetic tunnel junction.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, apparatus, article, or device that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or device.

Each memory cell of MRAM consists of an MTJ and a MOS transistor. The gate of the MOS tube is connected to Word Line (hereinafter abbreviated as WL bit Line) of the chip to switch on or off the unit, and the MTJ and the MOS tube are connected in series on Bitline (hereinafter abbreviated as BL bit Line) of the chip. Read and write operations are performed on the Bit Line as shown in FIG. 3. An MRAM chip is made up of one or more arrays of MRAM memory cells, each array having a number of external circuits, as shown in fig. 4:

the row address decoder changes the received address into the selection of Word Line;

the column address decoder changes the received address into the selection of Bit Line;

the read-write controller controls read (measurement) write (current application) operation on the Bit Line;

input and output control and external exchange data.

The read-out circuit of an MRAM needs to detect the resistance of the MRAM memory cell. Since the resistance of the MTJ may drift with temperature, etc., the general approach is to use some memory cells on the chip that have been written to a high resistance state or a low resistance state as reference cells, as shown in fig. 5. The resistance of the memory cell and the reference cell are compared using a Sense Amplifier (Sense Amplifier).

In an embodiment of the present invention, there is provided a high-speed MRAM chip using write detection, as shown in fig. 6, the MRAM chip includes an MRAM main storage unit and a plurality of peripheral circuits, the peripheral circuits include an address decoder, a read/write controller, and an input/output controller, and the MRAM chip further includes a write register, a write detection circuit, an error correction controller, and an error correction redundancy unit;

The invention proposes to add a write status detection circuit to leave the data in the register if a write error is found after writing. In the next period, data is written into the error correction redundancy unit, and meanwhile, new read-write instructions are not delayed to be processed. The circuit diagram of the write status detection circuit is shown in fig. 7. In order to detect the writing state, a low resistance state write reference unit (referred to as Ref _ P hereinafter) and a high resistance state write reference unit (referred to as Ref _ AP hereinafter) need to be constructed, and the design concept includes:

1. writing by using a given voltage and a given pulse length;

2. each circuit of write-in circuit is added with a write-in detection circuit;

3. if a memory cell needs to be written into the P state, the write detection circuit of the circuit uses the low-resistance state write reference unit as a reference for comparison, and sends a signal to terminate the write operation in advance when the resistance of the written unit is judged to be smaller than the resistance value corresponding to the low-resistance state write reference unit;

4. if a memory cell needs to be written into the AP state, the write detection circuit of the circuit uses the high-resistance state write reference unit as a reference for comparison, and sends a signal to terminate the write operation in advance when the resistance of the written cell is judged to be larger than the resistance value corresponding to the high-resistance state write reference unit.

In the system of this embodiment, there are multiple high resistance write reference cells, that is, each of the multiple high resistance write reference cells can be regarded as a high resistance write reference cell group, which includes an MTJ structure identical to that in the memory cell and is in a high resistance state. When the storage capacitor is used or refreshed (the refresh capacitor is described in detail later), a voltage required for writing a high-resistance state is applied to a write loop of the high-resistance state write reference cell, so that the state of the group of reference cells is not changed and is stabilized in the high-resistance state. In the MRAM array of the present embodiment, each row of memory cells corresponds to a high resistance state write reference cell, and the high resistance state write reference cells are output in parallel.

In the system of this embodiment, there are a plurality of low resistance write reference cells, that is, each of the low resistance write reference cells can be regarded as a group of low resistance write reference cells, each of which includes an MTJ structure identical to that in the memory cell and is in a low resistance state. When the storage capacitor is used or refreshed (the refreshing capacitor is described in detail later), the voltage required for writing the low-resistance state is applied to the write loop of the low-resistance state write reference unit, so that the state of the group of reference units is not changed and is stabilized in the low-resistance state. In the MRAM array of the present embodiment, each row of memory cells corresponds to one low resistance state write reference cell, and the low resistance state write reference cells are output in parallel.

A write reference control section in the write circuit controls a write operation when the write reference cell is required. The same write operation is performed when it is desired to generate or refresh Ref _ P and Ref _ AP, which does not change the state of the reference cell in the inventive design. The write reference control circuit electrically connects the sensing of Ref _ P to the write circuit to the high potential output terminals of all the P-state reference cells, and electrically connects the sensing of Ref _ AP to the write circuit to the high potential output terminals of all the AP-state reference cells.

The write-in detection circuit is used for receiving output signals of the high-resistance state write reference unit and the low-resistance state write reference unit and detection point signals of write-in loops of the storage units; when the storage unit is set to be in a high-resistance state, the write-in detection circuit compares a detection point signal of the storage unit with a signal provided by the high-resistance state write reference unit and judges the detection point signal, and when the storage unit is judged to be in the high-resistance state, the write-in detection circuit sends out a write-in operation termination signal; when the storage unit is set to be in a low-resistance state, the write detection circuit compares a detection point signal of the storage unit with a signal provided by the low-resistance state write reference unit and judges, and when the storage unit is judged to be in the low-resistance state, the write detection circuit sends out a write operation termination signal.

The high-resistance state potential adjusting unit is used for reducing the output voltage of the high-resistance state write reference unit and then inputting the reduced output voltage into the write detection circuit, namely slightly reducing the equivalent resistance serving as reference; the low-resistance state potential adjusting unit is used for increasing the output voltage of the low-resistance state write reference unit and then inputting the output voltage into the write detection circuit, namely slightly increasing the equivalent resistance serving as reference.

This is done because the resistance of the memory cells in the P-state and the AP-state have a distribution, as shown in fig. 10, Ref _ P and Ref _ AP are the adjusted resistance of the P-state and the AP-state, respectively, and the few P-state cells with high resistance and the few AP-state cells with low resistance are close to the middle reference point. Errors are not allowed for memory chips. With a single reference resistor, the error problem is difficult to avoid.

After the output signals adjusted by the high-resistance state potential adjusting unit and the low-resistance state potential adjusting unit are written into the detection circuit for use, a small amount of missed judgment still exists (the writing operation is actually finished and is not found), but a large space still exists in an error-prone area near a middle reference point, so that the erroneous judgment can be avoided (the judgment is finished without being finished). For memory type products, a small number of missed decisions is acceptable, with the consequence that a small number of memory cells will complete a whole write pulse, wasting a small amount of energy, while a false decision is unacceptable because it will cause a storage of erroneous information.

A preferable design idea is to store the reference voltages output by the high resistance state write reference unit and the low resistance state write reference unit on the capacitors respectively. This eliminates the need to turn on the reference cell to apply the write voltage every time a write operation is performed, thereby reducing power consumption.

Therefore, in this embodiment, the high-resistance state potential adjustment unit and the low-resistance state potential adjustment unit are respectively provided with a high-resistance state reference signal storage capacitor for storing the reference electrical signal output by the high-resistance state write reference unit, so that the reference voltage for performing high-resistance state comparison can be directly provided by the high-resistance state reference signal storage capacitor, and a low-resistance state reference signal storage capacitor for storing the reference electrical signal output by the low-resistance state write reference unit, so that the reference voltage for performing high-resistance state comparison can be directly provided by the low-resistance state reference signal storage capacitor.

Further, the MRAM main storage unit comprises one or more MRAM memory unit arrays, each MRAM memory unit comprises a magnetic tunnel junction and an MOS tube, the magnetic tunnel junction and the drain electrode of the MOS tube are connected in series on the BL bit line of the MRAM chip, and the grid electrode of the MOS tube is connected with the WL bit line of the MRAM chip.

Further, the address decoder includes a row address decoder for converting a received address into a selection of WL bit lines and a column address decoder for converting a received address into a selection of BL bit lines.

The write detection circuit includes a reference signal selector, a comparator, and a termination write operation controller.

The reference signal selector receives output signals of the high-resistance state writing reference unit and the low-resistance state writing reference unit and selects and outputs signals provided by the high-resistance state writing reference unit or the low-resistance state writing reference unit according to the type of writing operation of the storage unit.

The comparator receives the output signal of the reference signal selector and a detection point signal in a memory cell write loop, compares the output signal with the detection point signal, and outputs a corresponding signal. Each bit line has a corresponding comparator, and the comparators connected to the two bit lines are shown in fig. 7.

The controller for terminating the write operation is connected with the comparator, and generates a corresponding control signal to be supplied to the write circuit according to the received output result of the comparator so as to terminate or continue the write operation of the current storage unit.

When the storage unit is subjected to write operation set to be in a high-impedance state, after the write operation is compared with the high-impedance state reference unit, the write operation termination controller sends a write operation termination signal to turn off corresponding write operation in the write circuit when judging that the storage unit is in the high-impedance state; when the storage unit is subjected to the write operation set to be in the low-resistance state, after the low-resistance state reference unit is compared, the write operation termination controller sends out a write operation termination signal to turn off the corresponding write operation in the write circuit when the storage unit is judged to be in the low-resistance state.

The key points of the invention are as follows:

1. a write register containing the address to be written and the data to be written. Both data remain in this register at the same time as the write operation.

2. And a write detection circuit is added in each write unit. If a bit fails a write operation, the write detect circuit generates a signal. And reporting to the error correction controller.

3. The error correction redundancy unit is an extra part of the memory cells. The error correction controller contains the original memory address in error and a substitute address in the redundancy unit in which the data is stored.

4. The error correction controller, upon receiving an error signal from the write detection circuit, selects an address in a free redundant cell, records the address in the write register and the address, and stores the data written in the write register in the free address in the redundant cell. The method comprises the following specific steps:

a) when the MRAM chip receives the read-write command, the error correction controller compares the received address with the internal error address, and the address in the write queue:

i. if the address is not in the normal read-write operation, normal read-write operation is continued, and whether a write request exists in the write queue is checked. If yes, the steps are executed, and data are stored in the error correction redundancy unit.

if the address is therein

1. If the command is a read command, returning the data in the redundant unit/write queue;

2. if the command is a write command, continuing the ordinary write operation and tracking the write result;

b) when one normal read-write instruction is finished, if the instruction is a read operation, continuing; if it is a write operation

i. If the number of error bits generated by the write operation does not exceed the preset value, the error correction controller compares the received address with the error address in the error correction controller, and the address in the write queue. If it is, the relevant record is deleted, otherwise it continues.

And ii, if the number of error bits generated by the write operation exceeds a preset value, putting the data written into the register into a write queue of the error correction controller, and generating a write request.

In another embodiment of the present invention, a data reading method based on the MRAM chip is provided, as shown in fig. 8, including the following steps:

s11, sending the received reading instruction to an error correction controller by the MRAM chip, wherein the reading instruction comprises a reading address;

s12, the error correction controller compares the read address with the error address stored in the error correction address storage unit and the address in the write queue;

s131, if the read address is in the error address, matching a corresponding replacement address, and returning data of the replacement address in the error correction redundancy unit;

s132, if the read address is in the address in the write queue, returning the data of the address in the write queue;

s133, otherwise, returning the data of the read address in the MRAM main storage unit.

In another embodiment of the present invention, a data writing method based on the MRAM chip is provided, as shown in fig. 9, including the following steps:

s21, sending the received writing instruction to an error correction controller by the MRAM chip, wherein the writing instruction comprises a writing address and data to be written;

s22, the error correction controller compares the write address with the error address stored in the error correction address storage unit and the address in the write queue;

s23, if the write address is in the error address or the write queue, replacing the data of the write address in the MRAM main storage unit with the data to be written in the write command, deleting the address in the write queue, the error address stored in the error correction address storage unit, the replacement address and the data of the replacement address in the error correction redundant unit, and writing the data to be written in the write address in the MRAM main storage unit;

and S24, if the write address is not in the error address or the write queue, writing the data to be written in the write address in the MRAM main storage unit.

Further, the data writing method of the MRAM chip further includes, after step S24, performing the following operations, as shown in fig. 9:

s25, the write detection circuit detects the write operation status, if the write operation fails, an error signal is sent to the error correction controller;

s26, responding to the error signal, the error correction controller puts the data to be written in this time temporarily stored in the writing register into the writing queue, and the error correction controller stores the writing address in the MRAM main storage unit as an error address into the error correction address storage unit;

s27, the writing queue generates a writing request, and the data to be written is written into the spare replacement address in the error correction redundancy unit;

and S28, the error correction controller stores the replacement address into the error correction address storage unit and associates the corresponding error address.

if the number of error bits generated by the write operation exceeds a preset value, determining that the write operation fails; this preset value is generally set as the limit that the ECC circuit can correct.

The best implementation method of the invention is as follows: both the main and redundant storage contain ECC (check bits added for error correction). For example, in a 32 or 64bit word, an ECC is added that can correct two bit errors. At this time, the preset value of the number of error bits occurring by the write operation may be set to 2 or 3. When the write detection circuit detects a write error exceeding 2-3 bits, the error correction redundancy storage is used.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. A high-speed MRAM chip using write detection comprises an MRAM main storage unit and a plurality of peripheral circuits, wherein the peripheral circuits comprise an address decoder, a read-write controller and an input-output controller, and are characterized by further comprising a write register, a write detection circuit, an error correction controller and an error correction redundancy unit;

2. The MRAM chip of claim 1, wherein the write queue in the error correction controller also has an address, and if the address in the read command received by the MRAM chip is the address of the write queue, the data corresponding to the address in the write queue is returned.

3. The MRAM chip of claim 1, further comprising a high resistance state write reference cell for providing a reference electrical signal for determining whether the MRAM main memory cell is in a high resistance state and a low resistance state write reference cell for providing a reference electrical signal for determining whether the MRAM main memory cell is in a low resistance state, wherein the write detection circuit receives output signals of the high resistance state write reference cell and the low resistance state write reference cell and corresponding detection signals in a write loop of the MRAM main memory cell; when the MRAM main storage unit is set to be in a high-resistance state, the writing detection circuit compares a detection signal of the MRAM main storage unit with a signal provided by the high-resistance state writing reference unit and judges, and when the MRAM main storage unit is judged to be in the high-resistance state, the writing detection circuit sends a writing operation termination signal; when the MRAM main storage unit is set to be in a low-resistance state, the writing detection circuit compares a detection signal of the storage unit with a signal provided by the low-resistance state writing reference unit and judges, and when the storage unit is judged to be in the low-resistance state, the writing detection circuit sends out a signal for stopping writing operation.

4. The MRAM chip of claim 3, wherein the write detection circuit comprises:

5. The MRAM chip of claim 1, wherein if the write detection circuit detects that a write operation has been completed before a write pulse is terminated, the write operation is terminated early; and if the write operation is not detected to be completed when the write pulse is cut off to the end, outputting an error reporting signal to the error correction controller.

6. The MRAM chip of claim 1, wherein the MRAM main storage unit and the error correction redundancy unit each comprise an ECC check detection circuit.

7. A data reading method based on the MRAM chip of any one of claims 1 to 6, comprising the steps of:

if the read address is in the error address, matching the corresponding replacement address, and returning the data of the replacement address in the error correction redundancy unit;

8. A data writing method based on the MRAM chip of any one of claims 1 to 6, comprising the steps of:

9. The method of claim 8, further comprising, after writing the data to be written at the write address in the MRAM main memory unit:

10. The data writing method of an MRAM chip according to claim 9, wherein the writing operation failure is judged by:

and if the number of error bits generated by the write operation exceeds a preset value, determining that the write operation fails.