CN111884650B - Low-stray analog phase-locked loop linearization circuit - Google Patents

Abstract

The invention relates to a low-stray analog phase-locked loop linearization circuit, which belongs to the technical field of analog integrated circuit design. The invention consists of a frequency and phase detector, a charge pump, a pulse current source, a pulse generator, a voltage-controlled oscillator, a frequency divider and an error accumulation modulator. The pulse generator controls the pulse current source to generate a current with a certain pulse width, and moves the lock point in the steady state to the linear working area of the charge pump, thereby reducing the quantization noise folding effect and the instantaneous ripple of the voltage-controlled oscillator input voltage . The low-spurious analog phase-locked loop linearization circuit of the present invention achieves the effect of a circuit structure that can make the PLL work in the CP linear region without causing significant reference spurs.

Description

A Low Spurious Analog Phase Locked Loop Linearization Circuit

technical field

The invention relates to a low stray analog phase-locked loop linearization circuit, which belongs to the technical field of analog integrated circuit design.

Background technique

Phase-locked loop (hereinafter referred to as PLL) is the core circuit in various communication and clock chips, and the spectral noise, jitter, spurious and other indicators of its output signal are very critical, which will directly affect the system performance. The charge pump (hereinafter referred to as CP) is an important module in the PLL, and its output current passes through the loop filter to generate the control voltage of the voltage-controlled oscillator. The noise performance of the CP output signal is critical, determining the in-band noise floor of the entire PLL and the jitter of the PLL output clock.

The charge pump converts the phase signal output by the frequency and phase detector into a current signal. The ideal CP input and output function is a linear relationship with a fixed slope, as shown in Figure 8(a), the ordinate is the output charge of the charge pump, and the abscissa is is the phase difference, but in the actual circuit, due to various non-ideal factors in the operation of the device, nonlinear effects will appear near the phase difference of zero. Especially in the fractional PLL, the nonlinear characteristic of CP will fold and move the fractional modulator noise outside the PLL bandwidth into the PLL bandwidth, deteriorating the in-band noise of the PLL; at the same time, it will also degrade the reference spurious frequency of the PLL. stray performance.

For the problem that the nonlinearity of the CP deteriorates the PLL in-band noise, solutions have been documented. For example, in the article "Hung-Ming Chien and Tsung-Hsien Lin, etc., "A 4GHz Fractional-N Synthesizer for IEEE 802.11a," in IEEE Symposium On VLSI CircuitsDigest of Technical Papers. published by Hung-Ming Chien in 2004, Using the constant current bias method as shown in Figure 1 to change the steady-state input phase difference of the PLL, so that it moves to the linear operating region, as shown in Figure 8(b), so as to avoid the nonlinearity of the PLL. The in-band noise deterioration problem. However, the cost of making the PLL work in the CP linear region in the above literature is high reference spurs. It is necessary to invent a circuit structure that can make the PLL work in the CP linear region without causing significant reference spurs.

SUMMARY OF THE INVENTION

The purpose of the present invention is to propose a low-spurious analog phase-locked loop linearization circuit, so that the PLL can work in the CP linear region without causing significant reference spurious circuit structure.

The low spurious analog phase locked loop linearization circuit proposed by the present invention includes a pulse current source 207, a pulse generator 200, a frequency discriminator 201, a charge pump 202, a filter 203, a voltage controlled oscillator 204, a frequency divider 205 and an error accumulation modulator 206. The pulse generator 200 is connected to and controls the pulse current source 207 through a pulse signal; the frequency discriminator 201 is connected to the pulse generator 200; the charge pump 202 is connected to the frequency discriminator 201; the filter 203 is connected to the charge pump 202 and The pulse current source 207 is connected at the same point; the voltage controlled oscillator 204 is connected with the filter 203 ; the frequency divider 205 is connected with the voltage controlled oscillator 204 ; the error accumulation modulator 206 is connected with the frequency divider 205 . The pulse generator is composed of a first flip-flop 510, a second flip-flop 510, a third flip-flop 512, a fourth flip-flop 513, a fifth flip-flop 514, an AND gate 515, a first inverter 516, The second inverter 517, the third inverter 518, the fourth inverter 518, the fifth inverter 521, the sixth inverter 522, the seventh inverter 523, the eighth inverter 524, or NOT gate 520; the data pole D of the first flip-flop 510 is connected to the output of the second inverter 517 and the input of the third inverter 518; the input of the second inverter 517 is connected to the output of the first inverter 516 The input of the first inverter 516 is connected to the reference clock signal 2; the positive output pole of the first flip-flop 510 is connected to the data pole of the second flip-flop 510; the negative output pole of the first flip-flop 510 is connected to the NOR gate ( 520) is connected to an input terminal; the reset pole R of the first flip-flop 510 is connected to the reset pole R of the second flip-flop 510, the reset pole R of the third flip-flop 512, and the output terminal of the fifth inverter 521; The clock pole of a flip-flop 510 is connected to the output terminal of the AND gate 515; the input terminal of the AND gate 515 is respectively connected to the high-speed clock signal 2 and the inverse output pole of the fourth flip-flop 513; the positive output pole of the second flip-flop 510 is connected to the The data pole D of the three flip-flop 512 is connected; the clock pole of the second flip-flop 510 is connected to the output end of the AND gate 515; the positive output pole of the third flip-flop 512 is connected to the clock pole of the fourth flip-flop 513, The input terminal of the inverter 522 is connected; the output terminal of the sixth inverter 522 is connected to the input terminal of the fifth inverter 521; the clock pole of the third flip-flop 512 is connected to the output terminal of the AND gate 515; the fourth flip-flop 513 The data pole D of the fourth flip-flop 513 is connected to the high level; the data pole D of the fourth flip-flop 513 is connected to the input end of the NOR gate 520; the reset pole R of the fourth flip-flop 513 is connected to the positive output pole of the fifth flip-flop 514 and the eighth The inverter 524 is connected; the data pole D of the fifth flip-flop 514 is connected to a high level; the reset pole R of the fifth flip-flop 514 is connected to the positive output pole of the fifth flip-flop 514; the clock pole of the fifth flip-flop is connected to the reference Clock signal 2; the reset pole of the fifth flip-flop is connected to the output pole of the seventh inverter 523; the input pole of the seventh inverter 523 is connected to the eighth inverter 524.

The low spurious analog phase-locked loop linearization circuit proposed by the present invention has the following advantages:

The low-stray analog phase-locked loop linearization circuit proposed by the present invention adds a pulse generator to the existing phase-locked loop circuit, controls the pulse current source to generate a current with a certain pulse width, and moves the locking point in a steady state. into the linear operating region of the charge pump, thereby reducing the quantization noise folding effect and the instantaneous ripple of the VCO input voltage. The low-spurious analog phase-locked loop linearization circuit of the present invention can make the PLL work in the CP linear region without causing significant reference spurs.

Description of drawings

FIG. 1 is a schematic diagram of an existing phase-locked loop circuit.

FIG. 2 is a waveform diagram of an existing phase-locked loop circuit.

FIG. 3 is a schematic diagram of a low-spurious analog phase-locked loop linearization circuit proposed by the present invention.

FIG. 4 is a waveform diagram of a phase-locked loop with high linearity and low spurious proposed by the present invention.

FIG. 5 is a circuit schematic diagram of the pulse generator in the analog phase-locked loop linearization circuit of the present invention.

FIG. 6 is a working waveform diagram of the pulse generator.

Figure 7 is a beneficial effect diagram.

FIG. 8( a ) is a graph showing the input and output characteristics of a general charge pump.

Figure 8(b) is a graph showing the input and output characteristics of the charge pump operating in the linear region.

In FIG. 5, 510 is the first flip-flop, 511 is the second flip-flop, 512 is the third flip-flop, 513 is the fourth flip-flop, 514 is the fifth flip-flop, 515 is the AND gate, and 516 is the first inversion 517 is the second inverter, 518 is the third inverter, 519 is the fourth inverter, 521 is the fifth inverter, 522 is the sixth inverter, 523 is the seventh inverter, 524 is the eighth inverter and 520 is the NOR gate.

Detailed ways

The low-spurious analog phase-locked loop linearization circuit proposed by the present invention has a structure as shown in Figure 3, including:

pulse current source 207, pulse generator 200, frequency and phase detector 201, charge pump 202, filter 203, voltage controlled oscillator 204, frequency divider 205 and error accumulation modulator 206;

The pulse generator 200 is connected to and controls the pulse current source 207 through a pulse signal; the frequency discriminator 201 is connected to the pulse generator 200; the charge pump 202 is connected to the frequency discriminator The filter 203 is connected to the charge pump 202 and the pulse current source 207 at the same point; the voltage controlled oscillator 204 is connected to the filter 203; the frequency divider 205 is connected to the The voltage controlled oscillator 204 is connected; the error accumulation modulator 206 is connected to the frequency divider 205 .

The pulse generator 200 in the above-mentioned low-spurious analog phase-locked loop linearization circuit has a structure as shown in FIG. 5 , including:

First flip-flop 510, second flip-flop 511, third flip-flop 512, fourth flip-flop 513, fifth flip-flop 514, AND gate 515, first inverter 516, second inverter 517, third Inverter 518, fourth inverter 518, fifth inverter 521, sixth inverter 522, seventh inverter 523, eighth inverter 524 and NOR gate 52);

The data pole D of the first flip-flop 510 is connected to the output of the second inverter 517 and the input of the third inverter 518; the input of the second inverter 517 is connected to the first inverter 516 The output of the first inverter 516 is connected to the reference clock signal 2; the positive output pole of the first flip-flop 510 is connected to the data pole of the second flip-flop 511; The inverting output pole is connected to an input end of the NOR gate 52); the reset pole R of the first flip-flop 510 is connected to the reset pole R of the second flip-flop 511 and the reset pole R of the third flip-flop 512 , the output of the fifth inverter 521 is connected; the clock pole of the first flip-flop 510 is connected with the output of the AND gate 515; the input of the AND gate 515 is connected to the high-speed clock signal 2 and The negative output pole of the fourth flip-flop 513; the positive output pole of the second flip-flop 511 is connected to the data pole D of the third flip-flop 512; the clock pole of the second flip-flop 511 is connected to the The output terminal of the AND gate 515 is connected; the positive output pole of the third flip-flop 512 is connected to the clock pole of the fourth flip-flop 513 and the input terminal of the sixth inverter 522; The output terminal of the inverter 522 is connected to the input terminal of the fifth inverter 521; the clock pole of the third flip-flop 512 is connected to the output terminal of the AND gate 515; the data pole of the fourth flip-flop 513 D is connected to high level; the data pole D of the fourth flip-flop 513 is connected to the input end of the NOR gate 520 ; the reset pole R of the fourth flip-flop 513 is connected to the positive terminal of the fifth flip-flop 514 The output pole is connected to the eighth inverter 524; the data pole D of the fifth flip-flop 514 is connected to a high level; the reset pole R of the fifth flip-flop 514 is connected to the positive output pole of the fifth flip-flop 514 connected; the clock pole of the fifth flip-flop is connected to the reference clock signal 2; the reset pole of the fifth flip-flop is connected to the output pole of the seventh inverter 523; the input pole of the seventh inverter 523 is connected to the Eight inverters 524 .

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to FIG. 3 , FIG. 4 , FIG. 5 and FIG. 6 . It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, and the diagrams only show the relevant aspects of the present invention. The components are not drawn according to the number, shape and size of the components in actual implementation. The type, number and ratio of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complicated.

The low-spurious analog phase-locked loop linearization circuit of the present invention at least includes a pulse current source 207 and a pulse generator 200 as shown in FIG. 2 and other basic modules of the phase-locked loop working with them, such as a frequency discriminator and a phase discriminator. 201 , a charge pump 202 , a filter 203 , a voltage controlled oscillator 204 , a frequency divider 205 and an error accumulation modulator 206 . The frequency discriminator 201 is connected to the pulse generator 200; the charge pump 202 is connected to the frequency discriminator 201; the filter 203 is connected to the charge pump 202 and the pulse The current source 207 is connected at the same point; the voltage controlled oscillator 204 is connected to the filter 203; the frequency divider 205 is connected to the voltage controlled oscillator 204; the error accumulation modulator 206 is connected to the divider frequency converter 205 is connected.

As a preferred solution of this embodiment, although the structures in FIG. 3 and FIG. 1 can both shift the operating point of the phase-locked loop to the linear region of the CP, the structure in FIG. 3 is compared with the conventional solution in FIG. 1 . The improvement lies in: the current source 207 in FIG. 3 is controlled by the pulse signal output from the pulse generator 200 and is turned on in a very short period of time. At this time, the pulse current 207 and the charge pump charging current 208 cancel each other out and will not The voltage-controlled oscillator control voltage 210 fluctuates, and at the same time achieves the purpose of shifting the operating point of the phase-locked loop, as shown in FIG. 4; and the current source 107 in FIG. The VCO control voltage 110 exhibits ramp-shaped fluctuations as shown in FIG. 3 .

Further preferably, the specific structure of the pulse generator 200 is shown in FIG. 5 , including: a first trigger 510 , a second trigger 511 , a third trigger 512 , a fourth trigger 513 , and a fifth trigger 514 , AND gate 515, first inverter 516, second inverter 517, third inverter 518, fourth inverter 518, fifth inverter 521, sixth inverter 522, seventh inverter Inverter 523, eighth inverter 524, NOR gate 52); the data pole D of the first flip-flop 510 is connected to the output of the second inverter 517 and the input of the third inverter 518; the second inverter The input of the inverter 517 is connected to the output of the first inverter 516; the input of the first inverter 516 is connected to the reference clock signal 2; the positive output pole of the first flip-flop 510 is connected to the data pole of the second flip-flop 511; The inverting output pole of a flip-flop 510 is connected to an input terminal of the NOR gate 520; the reset pole R of the first flip-flop 510 is connected to the reset pole R of the second flip-flop 511, the reset pole R of the third flip-flop 512, the The output terminals of the five inverters 521 are connected; the clock pole of the first flip-flop 510 is connected with the output terminal of the AND gate 515; The positive output pole of the second flip-flop 511 is connected to the data pole D of the third flip-flop 512; the clock pole of the second flip-flop 510 is connected to the output terminal of the AND gate 515; the positive output pole of the third flip-flop 512 is connected to the fourth flip-flop 512. The clock pole of the flip-flop 513 is connected to the input terminal of the sixth inverter 522; the output terminal of the sixth inverter 522 is connected to the input terminal of the fifth inverter 521; the clock pole of the third flip-flop 512 is connected to the AND gate The output terminal of 515 is connected; the data pole D of the fourth flip-flop 513 is connected to a high level; the data pole D of the fourth flip-flop 513 is connected to the input terminal of the NOR gate (520); the reset pole R of the fourth flip-flop 513 Connect to the positive output pole of the fifth flip-flop 514 and the eighth inverter 524; the data pole D of the fifth flip-flop 514 is connected to a high level; the reset pole R of the fifth flip-flop 514 is connected to the positive pole of the fifth flip-flop 514. The output poles are connected; the clock pole of the fifth flip-flop is connected to the reference clock signal 2; the reset pole of the fifth flip-flop is connected to the output pole of the seventh inverter 523; the input pole of the seventh inverter 523 is connected to the eighth inverter 524. The waveform diagram of the operation of the pulse generator 200 is shown in FIG. 6 . As shown in FIG. 6 , after the reference clock signal 2 becomes a high level, the pulse generator outputs a synchronized pulse signal with the input high-speed clock signal 2. In the preferred embodiment shown in FIG. 5 and FIG. 6 , the high level of the pulse signal lasts for two cycles of the high-speed clock signal 2 , and then is pulled to a low level, so that the pulse signal can control the pulse current source 207 to perform a fixed pulse width discharge operation on the filter 203 . When the next reference clock signal 2 goes high, repeat this operation again, so that a current with a fixed pulse width can be injected into the loop, so that the phase-locked loop works in the linear region of the CP without destroying the charge pump charging. The current 208 is instantaneously matched with the pulse current 207, thereby achieving the inventive object of making the PLL work in the CP linear region without causing significant reference spurs.

The beneficial effect of the preferred solution of the above embodiment is shown in FIG. 7 , it can be seen that the embodiment in FIG. 2 has avoided the existing 40MHz reference spur in FIG. 1 , and at the same time suppressed the quantization noise from folding back into the band at low frequencies. .

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (1)

1. A low spurious analog PLL linearizer comprising at least:

the device comprises a pulse current source, a pulse generator, a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a frequency divider and an error accumulation modulator; the pulse generator is connected with and controls the pulse current source through a pulse signal; the phase frequency detector is connected with the pulse generator; the charge pump is connected with the phase frequency detector; the filter is connected with the charge pump and the pulse current source at the same point; the voltage-controlled oscillator is connected with the filter; the frequency divider is connected with the voltage-controlled oscillator; the error accumulation modulator is connected with the frequency divider;

wherein the pulse generator comprises:

the circuit comprises a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, an AND gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter and a NOR gate; the data electrode D of the first trigger is connected with the output of the second inverter and the input of the third inverter; the input of the second inverter is connected with the output of the first inverter; the input of the first inverter is connected with a reference clock signal 2; the output of the third inverter is connected with the input of the fourth inverter; the output of the fourth inverter is connected with a reference clock signal of the phase frequency detector; the positive output pole of the first trigger is connected with the data pole of the second trigger; the inverted output pole of the first trigger is connected with one input end of the NOR gate; the reset pole R of the first trigger is connected with the reset pole R of the second trigger, the reset pole R of the third trigger and the output end of the fifth inverter; the clock pole of the first trigger is connected with the output end of the AND gate; the input end of the AND gate is respectively connected with a high-speed clock signal 2 and the inverted output electrode of the fourth trigger; the positive output pole of the second flip-flop is connected with the data pole D of the third flip-flop; the clock pole of the second trigger is connected with the output end of the AND gate; the positive output pole of the third trigger is connected with the clock pole of the fourth trigger and the input end of the sixth inverter; the output end of the sixth inverter is connected with the input end of the fifth inverter; the clock pole of the third trigger is connected with the output end of the AND gate; the data electrode D of the fourth trigger is connected with a high level; the positive output pole of the fourth flip-flop is connected with the other input end of the NOR gate; the reset pole R of the fourth trigger is connected with the positive output pole of the fifth trigger and the input end of the eighth inverter; the data electrode D of the fifth trigger is connected with a high level; the reset pole R of the fifth flip-flop is connected with the positive output pole of the fifth flip-flop; the clock electrode of the fifth trigger is connected with a reference clock signal 2; the reset electrode of the fifth trigger is connected with the output electrode of the seventh inverter; and the input pole of the seventh inverter is connected with the output end of the eighth inverter.

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