CN111884648A - Output feedback logic circuit and chip based on unipolar transistor - Google Patents

Abstract

The invention discloses an output feedback logic circuit and a chip based on a unipolar transistor, wherein the output feedback logic circuit comprises: the source electrode of the first transistor is connected with the first end of the pull-down unit and serves as the output end of the output feedback logic circuit, and the connecting point between the first end of the input control switch and the first end of the output control switch is connected with the grid electrode of the first transistor; the control end of the input control switch is connected to the signal input end, and the second end of the input control switch is connected with the output end of the output feedback logic circuit; the control end of the output control switch is connected with the output end of the output feedback logic circuit; the control end of the pull-down unit is connected to the signal input end, and the first end of the pull-down unit is connected with the output end of the output feedback logic circuit. The output feedback logic circuit of the invention only consists of unipolar transistors; compared with the traditional design, the output feedback logic circuit has lower circuit complexity and can be widely applied to the field of semiconductor integrated circuits.

Description

A kind of output feedback logic circuit and chip based on unipolar transistor

technical field

The invention relates to the field of semiconductor integrated circuits, in particular to an output feedback logic circuit and a chip based on unipolar transistors.

Background technique

Practical difficulties exist between traditional rigid electronics and bendable everyday objects such as paper, tape, human body, and textiles. We can solve this problem with large-area flexible electronics. These large-area flexible electronic technologies offer bendability, light weight, ultra-thin size, transparency, stretchability, large-area applicability, low cost, and several other attractive features.

However, most current flexible electronic technologies can only provide high-performance unipolar (purely n-type or pure p-type) devices. For example, in a-Si TFT technology, the main device type of oxide TFT technology is n-type transistor; while the main device type of organic TFT technology and carbon nanotube technology is p-type transistor. Therefore, under normal circumstances, flexible electronic circuits can only be realized based on unipolar transistors, which means that traditional CMOS circuit design technology is no longer applicable. Compared with mature CMOS integrated circuit design technology, the design of flexible integrated circuits faces many challenges.

The present invention only takes a pure n-type circuit as an example for discussion. For a pure p-type circuit, it is only necessary to turn the circuit up and down, so it will not be described in detail.

Based on the basic logic gate circuits of unipolar devices, there are two commonly used designs: pseudo-CMOS technology and capacitive bootstrap technology. Figure 1 shows the pseudo-CMOS inverter structure. Figure 2 shows the capacitive bootstrap inverter structure. From the perspective of circuit complexity, the pseudo-CMOS technology requires two power supplies, and the capacitor bootstrap technology requires a bootstrap capacitor, which undoubtedly increases the circuit complexity. From the perspective of power consumption, when the input is high, neither the pull-up transistor nor the pull-down transistor can be completely turned off, so there is a large leakage current, resulting in non-zero static power consumption.

SUMMARY OF THE INVENTION

In order to solve one of the above technical problems, the purpose of the present invention is to provide an output feedback logic circuit and chip based on unipolar transistors.

The first technical scheme adopted in the present invention is:

An output feedback logic circuit based on unipolar transistors includes a pull-up unit, a pull-down unit, an input control switch and an output control switch, the pull-up unit including a first transistor;

The drain of the first transistor is connected to the power supply terminal, the source of the first transistor is connected to the first terminal of the pull-down unit, and serves as the output terminal of the output feedback logic circuit, and the input controls the switch. a connection point between the first end and the first end of the output control switch is connected to the gate of the first transistor;

The control end of the input control switch is connected to the signal input end, and the second end of the input control switch is connected to the output end of the output feedback logic circuit;

The control terminal of the output control switch is connected to the output terminal of the output feedback logic circuit, and the second terminal of the output control switch is connected to the power supply terminal;

The control end of the pull-down unit is connected to the signal input end, the first end of the pull-down unit is connected to the output end of the output feedback logic circuit, and the second end of the pull-down unit is connected to the ground end;

The output feedback logic circuit includes at least one of an inverter circuit, a multi-input NOR circuit or a multi-input NAND circuit.

Further, the output control switch is made of one transistor.

Further, the unipolar transistor is an n-type transistor, the output feedback logic circuit is an inverter circuit, the pull-down unit includes a second transistor, the output control switch includes a third transistor, and the input control switch includes a third transistor. four transistors;

The drain of the second transistor is connected to the output terminal of the output feedback logic circuit, the gate of the second transistor is connected to the signal input terminal, and the source of the second transistor is connected to the ground terminal;

The drain of the third transistor is connected to the power supply terminal, the gate of the third transistor is connected to the output terminal of the output feedback logic circuit, and the source of the third transistor is connected to the drain of the fourth transistor connect;

The gate of the fourth transistor is connected to the signal input terminal, and the source of the fourth transistor is connected to the output terminal of the output feedback logic circuit.

Further, the unipolar transistor is an n-type transistor, the output feedback logic circuit is a multi-input NOR gate circuit, the pull-down unit includes m parallel transistors, and the input control switch includes m parallel transistors, The output control switch includes a transistor, and the gate of the transistor is connected to the output terminal of the output feedback logic circuit, and the m is an integer greater than 1.

Further, the multi-input NOR gate circuit is a two-input NOR gate circuit, the pull-down unit includes a fifth transistor and a sixth transistor, and the input control switch includes a seventh transistor and an eighth transistor;

The drain of the fifth transistor and the drain of the sixth transistor are both connected to the output terminal of the output feedback logic circuit, the source of the fifth transistor and the source of the sixth transistor are both connected to the ground terminal, so the gate of the fifth transistor is connected to the first signal input terminal, and the gate of the sixth transistor is connected to the second signal input terminal;

The drain of the seventh transistor and the drain of the eighth transistor are both connected to the source of the output control switch, and the source of the seventh transistor and the source of the eighth transistor are both connected to the output feedback logic At the output end of the circuit, the gate of the seventh transistor is connected to the first signal input end, and the gate of the eighth transistor is connected to the second signal input end.

Further, the unipolar transistor is an n-type transistor, the output feedback logic circuit is a multi-input NAND gate circuit, the pull-down unit includes p transistors in series, and the input control switch includes p transistors in series, The output control switch includes a transistor, and the gate of the transistor is connected to the output terminal of the output feedback logic circuit, and the p is an integer greater than 1.

Further, the multi-input NAND gate circuit is a two-input NAND gate circuit, the pull-down unit includes a ninth transistor and a tenth transistor, and the input control switch includes an eleventh transistor and a twelfth transistor;

The drain of the ninth transistor is connected to the output terminal of the output feedback logic circuit, the source of the ninth transistor is connected to the drain of the tenth transistor, and the gate of the ninth transistor is connected to the a signal input terminal;

The source of the tenth transistor is connected to the ground terminal, and the gate of the tenth transistor is connected to the second signal input terminal;

The drain of the eleventh transistor is connected to the source of the output control switch, the source of the eleventh transistor is connected to the drain of the twelfth transistor, and the gate of the eleventh transistor is connected connected to the first signal input terminal;

The source of the twelfth transistor is connected to the output terminal of the output feedback logic circuit, and the gate of the twelfth transistor is connected to the second signal input terminal.

The second technical scheme adopted by the present invention is:

A chip includes a logic circuit, and the logic circuit adopts the above-mentioned output feedback logic circuit based on unipolar transistors.

The beneficial effects of the present invention are: the output feedback logic circuit of the present invention is only composed of unipolar transistors and is suitable for flexible electronic technology; in addition, the output feedback logic circuit has lower circuit complexity compared with traditional designs.

Description of drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following descriptions are given to the accompanying drawings of the embodiments of the present invention or the related technical solutions in the prior art. It should be understood that the accompanying drawings in the following introduction It is only for the convenience of clearly expressing some embodiments of the technical solutions of the present invention, and for those skilled in the art, other drawings can also be obtained from these drawings without creative work.

1 is a schematic circuit diagram of a pseudo-CMOS inverter in the prior art;

2 is a schematic circuit diagram of a capacitor bootstrap inverter in the prior art;

3 is a schematic diagram of an inverter circuit in an embodiment of the present invention;

4 is a schematic diagram of an electronic circuit of an inverter circuit in an embodiment of the present invention;

5 is a schematic diagram of a VTC curve of an inverter circuit in an embodiment;

6 is a schematic diagram of current consumption of an inverter circuit in an embodiment;

7 is a schematic diagram of current consumption of a conventional pseudo-CMOS logic circuit;

8 is a schematic diagram of the current consumption of a conventional capacitive bootstrap logic circuit;

9 is a schematic diagram of a two-input NOR gate circuit in an embodiment of the present invention;

10 is a schematic diagram of a two-input NAND gate circuit in an embodiment of the present invention;

11 is a schematic diagram of the working waveform and current consumption of a two-input NOR gate according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of the working waveform and current consumption of a two-input NAND gate according to an embodiment of the present invention.

Detailed ways

The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention.

In the description of the present invention, it should be understood that the azimuth description, such as the azimuth or position relationship indicated by up, down, front, rear, left, right, etc., is based on the azimuth or position relationship shown in the drawings, only In order to facilitate the description of the present invention and simplify the description, it is not indicated or implied that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.

In the description of the present invention, the meaning of several is one or more, the meaning of multiple is two or more, greater than, less than, exceeding, etc. are understood as not including this number, above, below, within, etc. are understood as including this number. If it is described that the first and the second are only for the purpose of distinguishing technical features, it cannot be understood as indicating or implying relative importance, or indicating the number of the indicated technical features or the order of the indicated technical features. relation.

In the description of the present invention, unless otherwise clearly defined, words such as setting, installation, connection should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

This embodiment provides an output feedback logic circuit based on a unipolar transistor, and the output feedback logic circuit is an inverter circuit, a multi-input NOR circuit, a multi-input NAND circuit, or the like.

As shown in FIG. 3 , in some embodiments, the output feedback logic circuit is an inverter circuit with an output feedback structure. The inverter circuit consists of a pull-up transistor T1 (ie, the first transistor) and a pull-down transistor T2 (ie, the first transistor). Two transistors), and two switches T3, T4. Switch T3 is controlled by the output signal, and switch T4 is controlled by the input signal. When the control signal is at a high level, the switch is turned on, and when the control signal is at a low level, the switch is turned off. In some embodiments, the switches T3 and T4 can be made of transistors, as shown in FIG. 4 .

When the input is low, T2 and T4 are turned off, and the output node voltage rises, which makes T3 turn on, the gate voltage of T1 increases, and the output voltage continues to rise, causing T3 to turn on further. In this cycle, positive feedback is generated, and finally the output voltage is pulled up to a high level.

When the input is high, T2 and T4 turn on and the output node voltage drops, which makes T3 turn off. Because T4 is on, T1 is off, and the pull-up current is zero, so the final output node is pulled low.

Referring to Table 1, from the perspective of circuit complexity, the circuit structure of this embodiment uses the same number of transistors as the conventional structure, but does not need to use dual power supplies and capacitors, so the circuit complexity is lower.

Table 1

Pseudo CMOS logic Capacitive Bootstrap Logic This embodiment Number of power supplies 2 1 1 number of devices 4 transistors 4 transistors 1 capacitor 4 transistors Static power Have Have none

From the perspective of circuit power consumption, the circuit of this embodiment has no static power consumption. When the input is low and the output is high, both T1 and T2 have Vgs=0, both T1 and T2 are off, and there is no current path between the power supply and the ground, so the circuit has no static power consumption. When the input is high and the output is low, T1 has Vgs=0, T2 has Vds=0, both T1 and T2 are off, and there is no current path between the power supply and the ground, so the circuit has no static power consumption.

Symmetrical voltage transfer (VTC) curves can be obtained by adjusting the dimensions of T1 and T2. In this embodiment, the size of the transistors T2, T3, and T4 is W/L, and the size of T1 is 10 W/L.

FIG. 5 is a schematic diagram of VTC curves of the above inverter circuit under different power supplies. It can be seen from the figure that the inverter circuit of this embodiment can reach the ideal high and low level, so it has a full output swing. In addition, the VTC curve of this embodiment is symmetrical. Finally, because of the introduction of positive feedback, the transition of high and low levels is very fast, and the transition interval between high and low levels is very narrow. The above three points together indicate that the inverter circuit of this embodiment has a good noise margin.

FIG. 6 shows the current consumption of the inverter circuit of this embodiment under different power supplies. The circuit consumes current only during the high-low transition interval. In steady state, the circuit consumes no current. Therefore, the inverter circuit of this embodiment has only dynamic power consumption and no static power consumption.

As a comparison, FIG. 7 shows a schematic diagram of current consumption of a conventional pseudo-CMOS logic circuit, and FIG. 8 shows a schematic diagram of current consumption of a conventional capacitive bootstrap logic circuit. It can be seen that when the input is high and the output is low, there is a certain current consumption because both the pull-up and pull-down transistors cannot be completely turned off. Therefore, these two logic structures have static power consumption.

In some embodiments, a multi-input NOR gate can be obtained by extending the above-mentioned transistors T2 and T4 in parallel, as shown in FIG. T5 and T6, expand T4 to T7 and T8 in parallel. Among them, T5 and T7 inputs are connected to the same input terminal in1, and T6 and T8 inputs are connected to the same input terminal in2.

In some embodiments, a multi-input NAND gate can be obtained by extending T2 and T4 in series, as shown in FIG. 10 . FIG. 10 is a two-input NAND gate circuit of this embodiment, and T2 is extended to T9 and T10 connected in series. , expand T4 to T11 and T12 in parallel. Among them, the inputs of T9 and T11 are connected to the same input terminal in1, and the inputs of T10 and T12 are connected to the same input terminal in2.

FIG. 11 shows the working waveform and current consumption of the two-input NOR gate based on this embodiment; FIG. 12 shows the working waveform and current consumption of the two-input NAND gate based on this embodiment. It can be seen that the NOR and NAND operations function correctly. The circuit has dynamic power consumption only when the input signal transitions. In steady state, there is no static power dissipation.

To sum up, the output feedback logic circuit of this embodiment, firstly, only consists of unipolar transistors, so it is suitable for flexible electronic technologies (such as thin film transistors, carbon nanotubes, etc.). In addition, compared with the traditional design, the circuit complexity of this embodiment is low (no dual power supplies and bootstrap capacitors are required), and there is no static power consumption, which greatly reduces power consumption.

This embodiment also provides a chip, including a logic circuit, and the logic circuit adopts the above-mentioned output feedback logic circuit based on a unipolar transistor.

The chip of this embodiment has a corresponding relationship with the above-mentioned output feedback logic circuit, and thus has corresponding functions and beneficial effects of a flip-flop circuit.

The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the described embodiments, and those skilled in the art can also make various equivalent deformations or replacements on the premise that does not violate the spirit of the present invention , these equivalent modifications or substitutions are all included within the scope defined by the claims of the present application.

Claims (8)

1. An output feedback logic circuit based on a unipolar transistor is characterized by comprising a pull-up unit, a pull-down unit, an input control switch and an output control switch, wherein the pull-up unit comprises a first transistor;

the drain electrode of the first transistor is connected with a power supply end, the source electrode of the first transistor is connected with the first end of the pull-down unit and serves as the output end of the output feedback logic circuit, and the connecting point between the first end of the input control switch and the first end of the output control switch is connected with the grid electrode of the first transistor;

the control end of the input control switch is connected to the signal input end, and the second end of the input control switch is connected with the output end of the output feedback logic circuit;

the control end of the output control switch is connected with the output end of the output feedback logic circuit, and the second end of the output control switch is connected with a power supply end;

the control end of the pull-down unit is connected to the signal input end, the first end of the pull-down unit is connected with the output end of the output feedback logic circuit, and the second end of the pull-down unit is connected to the ground end;

the output feedback logic circuit includes at least one of an inverter circuit, a multiple-input nor gate circuit, or a multiple-input nand gate circuit.

2. The output feedback logic circuit based on unipolar transistors according to claim 1, wherein said output control switch is made of one transistor.

3. The output feedback logic circuit based on unipolar transistors according to claim 1, wherein the unipolar transistor is an n-type transistor, the output feedback logic circuit is an inverter circuit, the pull-down unit comprises a second transistor, the output control switch comprises a third transistor, and the input control switch comprises a fourth transistor;

the drain electrode of the second transistor is connected with the output end of the output feedback logic circuit, the grid electrode of the second transistor is connected to the signal input end, and the source electrode of the second transistor is connected to the ground end;

the drain electrode of the third transistor is connected to a power supply end, the grid electrode of the third transistor is connected with the output end of the output feedback logic circuit, and the source electrode of the third transistor is connected with the drain electrode of the fourth transistor;

and the grid electrode of the fourth transistor is connected to the signal input end, and the source electrode of the fourth transistor is connected with the output end of the output feedback logic circuit.

4. The output feedback logic circuit based on unipolar transistors according to claim 1, wherein the unipolar transistor is an n-type transistor, the output feedback logic circuit is a multiple-input nor gate circuit, the pull-down unit comprises m parallel transistors, the input control switch comprises m parallel transistors, the output control switch comprises one transistor, a gate of the transistor is connected to an output end of the output feedback logic circuit, and m is an integer greater than 1.

5. The output feedback logic circuit based on unipolar transistors according to claim 4, wherein the multiple-input NOR gate circuit is a two-input NOR gate circuit, the pull-down unit comprises a fifth transistor and a sixth transistor, and the input control switch comprises a seventh transistor and an eighth transistor;

the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are both connected to the output end of the output feedback logic circuit, the source electrode of the fifth transistor and the source electrode of the sixth transistor are both connected to the ground end, the grid electrode of the fifth transistor is connected to the first signal input end, and the grid electrode of the sixth transistor is connected to the second signal input end;

the drain electrode of the seventh transistor and the drain electrode of the eighth transistor are both connected with the source electrode of the output control switch, the source electrode of the seventh transistor and the source electrode of the eighth transistor are both connected with the output end of the output feedback logic circuit, the grid electrode of the seventh transistor is connected with the first signal input end, and the grid electrode of the eighth transistor is connected with the second signal input end.

6. The output feedback logic circuit based on unipolar transistors according to claim 1, wherein the unipolar transistor is an n-type transistor, the output feedback logic circuit is a multi-input nand gate circuit, the pull-down unit comprises p transistors connected in series, the input control switch comprises p transistors connected in series, the output control switch comprises one transistor, a gate of the transistor is connected to an output end of the output feedback logic circuit, and p is an integer greater than 1.

7. The output feedback logic circuit based on unipolar transistors according to claim 6, wherein the multiple-input NAND gate circuit is a two-input NAND gate circuit, the pull-down unit comprises a ninth transistor and a tenth transistor, and the input control switch comprises an eleventh transistor and a twelfth transistor;

the drain of the ninth transistor is connected with the output end of the output feedback logic circuit, the source of the ninth transistor is connected with the drain of the tenth transistor, and the gate of the ninth transistor is connected to the first signal input end;

a source of the tenth transistor is connected to a ground terminal, and a gate of the tenth transistor is connected to the second signal input terminal;

the drain of the eleventh transistor is connected with the source of the output control switch, the source of the eleventh transistor is connected with the drain of the twelfth transistor, and the gate of the eleventh transistor is connected to the first signal input end;

and the source electrode of the twelfth transistor is connected to the output end of the output feedback logic circuit, and the grid electrode of the twelfth transistor is connected to the second signal input end.

8. A chip comprising a logic circuit employing a unipolar transistor based output feedback logic circuit according to any one of claims 1 to 7.

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