CN111863646A - Method for detecting defects of semiconductor device - Google Patents
Method for detecting defects of semiconductor device Download PDFInfo
- Publication number
- CN111863646A CN111863646A CN201910335103.6A CN201910335103A CN111863646A CN 111863646 A CN111863646 A CN 111863646A CN 201910335103 A CN201910335103 A CN 201910335103A CN 111863646 A CN111863646 A CN 111863646A
- Authority
- CN
- China
- Prior art keywords
- wafer
- defect
- sem
- chip
- window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007547 defect Effects 0.000 title claims abstract description 103
- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000001514 detection method Methods 0.000 claims abstract description 44
- 238000009826 distribution Methods 0.000 claims abstract description 12
- 238000007689 inspection Methods 0.000 claims description 32
- 235000012431 wafers Nutrition 0.000 description 57
- 238000004626 scanning electron microscopy Methods 0.000 description 45
- 238000010586 diagram Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000004627 transmission electron microscopy Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Analysing Materials By The Use Of Radiation (AREA)
Abstract
The invention relates to a method for detecting defects of a semiconductor device. The method comprises the following steps: providing a wafer to be detected and scanning the wafer to be detected for defects so as to obtain defect distribution information of each chip in the wafer; acquiring offset parameters of different positions of the SEM detection machine relative to the wafer, and calibrating the precision of the SEM detection machine; and calibrating the position of the SEM detection machine based on the position deviation parameters, and executing a step of directly moving the wafer so as to enable the position of the defect in the chip to be positioned in the central area of a window of the SEM detection machine. By the method, a larger magnification factor can be obtained, and more accurate defect images and defect information can be obtained.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for detecting defects of a semiconductor device.
Background
As processes improve, many of the problems that lead to chip failures are caused by very small defects (defects), which typically require scanning imaging using auxiliary tools such as Scanning Electron Microscopy (SEM), Focused Ion Beam (FIB), or Transmission Electron Microscopy (TEM) to find the location where the defect occurs for improvement.
The SEM works by scanning the surface of a sample with an electron beam to obtain information about the sample, such as the surface structure of the sample, the physical and chemical properties of the sample, and the like. In recent years, SEM has been widely used in various fields. For example, in a semiconductor manufacturing process, SEM may be used to inspect wafers for defects, measure critical dimensions, and the like.
When performing Ultra small defect inspection (Ultra Tiny Defects) using SEM, SEM is generally used to detect the position of an alarm when a scanning tool detects a defect image, so as to help check on-line problems and potential risks, but as the device size is continuously reduced, it is increasingly challenging to obtain a high-quality (especially high magnification) Ultra small defect image.
Therefore, how to efficiently and rapidly scan the defects becomes an urgent problem to be solved in the prior art.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the existing problems, the invention provides a method for detecting defects of a semiconductor device, which comprises the following steps:
providing a wafer to be detected and scanning the wafer to be detected for defects so as to obtain defect distribution information of each chip in the wafer;
obtaining offset parameters of different positions of the SEM detection machine relative to the wafer;
and calibrating the position of the SEM detection machine based on the position deviation parameters, and executing a step of directly moving the wafer so as to enable the position of the defect in the chip to be positioned in the central area of a window of the SEM detection machine.
Optionally, before performing the calibration, the method further comprises:
and checking whether the position deviation parameter is within the control limit range, if so, correcting the position deviation parameter when the step of directly moving the wafer is executed according to the acquired position deviation information, and placing the position with the defect in the chip in the central area of the SEM detection machine table window.
Optionally, if the position offset parameter exceeds the control limit range, the step of directly moving the wafer is performed according to the acquired position offset information, and the position where the defect occurs in the chip is placed in the central area of the window of the SEM inspection machine.
Optionally, the central region of the viewing window is the very middle of the viewing window.
Optionally, the wafer to be detected is scanned for defects by a scanner table, so as to obtain a defect distribution map about the wafer.
Optionally, the method for acquiring the position offset parameter includes:
the wafer comprises a plurality of identical chips, and coordinates in one chip are given, wherein the coordinates have certain graphic features;
photographing the position of the coordinate in each chip at a fixed point to shoot a graph at the position of the coordinate;
and comparing the images obtained by shooting to obtain the offset value of the SEM detection machine relative to different chips distributed on the wafer.
Optionally, the photographed graph is compared with an ideal image corresponding to the position coordinate to obtain an offset value of the SEM inspection machine relative to different chips distributed on the wafer.
Optionally, the position offset parameter of the SEM detection machine relative to each chip in the wafer is obtained to obtain an offset map of the wafer.
Optionally, the position of the defect in the chip is placed in the central area of a window of an SEM inspection machine, and the defect position is enlarged and photographed to obtain an image containing the defect.
Optionally, after the position information is calibrated, the defect position is accurately located in the central area of the window of the SEM inspection machine according to the calibrated data.
In order to solve the problems in the prior art, the invention provides a method for detecting defects of a semiconductor device, and in the method, in order to detect ultra-small defects more accurately, when a defect position image is shot, offset parameters of an SEM (scanning Electron microscope) detection machine relative to different positions in a wafer are firstly obtained, so that when the defect position is subjected to SEM detection by directly moving the wafer in the follow-up process, the defect position is accurately placed in the central area of a window, more accurate defect images and defect information are obtained, the position where the defect occurs in a chip can be placed in the central area of the window of the SEM detection machine when the wafer is directly moved, a larger magnification factor is obtained, and more accurate defect images and defect information are obtained.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a process flow diagram of the detection method described in the examples of the present invention;
FIG. 2A illustrates a structural view of a template image in the detection method according to an embodiment of the present invention;
FIG. 2B is a diagram illustrating a deviation of the contrast between the template image and the chip image in the detection method according to the embodiment of the present invention;
FIG. 2C is a schematic diagram illustrating a wafer offset map in the inspection method according to the embodiment of the invention;
fig. 3 shows a flow chart of the detection method in the embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
In the wafer production process, products need to be checked randomly, and problems are found, so that the process improvement is facilitated, and the yield is improved. Generally, a scanning machine scans a wafer to form a defect distribution map, and then corresponding positions are found in an SEM inspection machine according to the positions of the defects given in the distribution map to obtain specific defect information.
Currently, SEM inspection methods adopted in the industry generally include a Direct wafer removal Location (DDL) method and an automatic wafer removal Location (ADL) method, which both have some limitations when facing ultra-small-sized defects:
(1) in the DDL, an SEM detection machine directly moves a wafer and directly takes a picture before a defect position is moved to a lens, but the precision of the machine is limited, so that the defect can be shot, the defect cannot be magnified to a sufficient multiple generally, and the defect with a small size cannot be seen clearly enough; (2) in the ADL, an SEM (scanning Electron microscope) detection machine moves a wafer, the defect position is moved to the front of a lens, a defect position picture and a picture of a reference position of an adjacent chip are respectively shot in a larger window, the positions of the defects in the window are identified through comparison of the two pictures and a certain algorithm, the position is moved to the middle of the window, and the shot is enlarged. The advantage of this method is that in most cases the defects calculated by the algorithm are not problematic, and defects that are sufficiently accurate (with sufficient magnification) are located in the very middle of the image. The disadvantage is that as the defect size decreases, the accuracy of the algorithm decreases and is prone to error (i.e., the place where the algorithm considers the largest difference is not the actual desired defect).
In order to solve at least one of the above technical problems, the present invention provides a method for detecting defects of a semiconductor device. The defect scanning method of the present invention is described in detail below with reference to the accompanying drawings; FIG. 1 shows a process flow diagram of the detection method described in the examples of the present invention; FIG. 2A illustrates a structural view of a template image in the detection method according to an embodiment of the present invention; FIG. 2B is a diagram illustrating a deviation of the contrast between the template image and the chip image in the detection method according to the embodiment of the present invention; FIG. 2C is a schematic diagram illustrating a wafer offset map in the inspection method according to the embodiment of the invention; fig. 3 shows a flow chart of the detection method in the embodiment of the present invention.
The invention provides a method for detecting defects of a semiconductor device, which mainly comprises the following steps as shown in figure 1:
step S1: providing a wafer to be detected and scanning the wafer to be detected for defects so as to obtain defect distribution information of each chip in the wafer;
step S2: obtaining offset parameters of different positions of the SEM detection machine relative to the wafer;
step S3: and calibrating the position of the SEM detection machine based on the position deviation parameters, and executing a step of directly moving the wafer so as to enable the position of the defect in the chip to be positioned in the central area of a window of the SEM detection machine.
Next, a detailed description will be given of a specific embodiment of the method for detecting defects in a semiconductor device of the present invention.
First, step S1 is executed to provide a wafer to be detected and perform defect scanning on the wafer to be detected, so as to obtain defect distribution information of each chip in the wafer.
Specifically, in this step, the wafer to be detected may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III/V compound semiconductors, as well as multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-stacked germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI), and the like.
Various devices may be formed in the wafer to be detected, for example, various active devices and/or passive devices may be formed, and various MEMS devices may also be formed, and the kinds and structures of the various devices are not described herein again.
Various defects are inevitably generated in the process of forming the various devices, and are critical to the performance and yield of the semiconductor device in order to avoid the failure of the device, to find the defects in time and to eliminate the defects as early as possible.
In the detection process, firstly, the wafer to be detected is scanned for defects so as to obtain defect distribution information of each chip in the wafer. For example, a defect distribution map is formed by scanning a wafer through a scanner, and then a corresponding position is found in an SEM inspection machine to take a picture according to the position of the defect given in the distribution map, so as to obtain specific defect information. The method and process for scanning the wafer by the scanner may be conventional processes and methods in the art, and are not described herein again.
Then, step S2 is executed to obtain the offset parameters of the SEM inspection apparatus relative to different positions of the wafer; for example, the position offset parameter of the SEM inspection tool with respect to each chip in the wafer is obtained for calibrating the accuracy of the SEM inspection tool.
In this step, in order to solve the problem that the defect cannot be magnified to a sufficient magnification to ensure that the defect can be captured due to the limited precision of the stage in the DDL step, and therefore the defect with a smaller size is not seen clearly enough, a step of correcting the precision of the SEM inspection stage is added before the DDL step is performed to ensure that the defect can be precisely moved to the middle of the window by the SEM inspection stage in the DDL mode, so that the defect can be captured by magnifying to a sufficient magnification.
The method for correcting the precision of the SEM detection machine comprises the following steps:
the wafer comprises a plurality of identical chips, and coordinates inside one chip are given;
photographing the position of the coordinate in each chip at a fixed point to shoot a graph at the position of the coordinate;
and comparing the images obtained by shooting to obtain the offset value of the SEM detection machine relative to different chips distributed on the wafer.
Specifically, in an embodiment of the present invention, a wafer to be tested is provided, wherein a same chip is located on the wafer to be tested, and given a coordinate inside the chip, the shape of each chip inside the wafer at the coordinate location is uniform. Before DDL detection, a CPI (fixed point photographing) mode is adopted firstly, photos of shooting the same coordinate (coordinate in a chip) are taken from the interior of each chip at four positions of a wafer respectively, and the position of the chip distributed at different positions on the wafer by an SEM detection machine table is deviated by comparing the photos. In the subsequent DDL detection process, the SEM detection machine table can be calibrated according to the deviation value obtained by the CPI, so that the SEM detection machine table is guaranteed to accurately move the defect position to the middle of the window for taking a picture.
Optionally, in the method for comparing photos, the photographed graph is compared with a preset template image to obtain offset values of the SEM inspection machine relative to different chips distributed on the wafer.
Illustratively, a corresponding correct product image, referred to as an ideal "image," i.e., a template image, is stored in advance before the comparison is performed, as shown in fig. 2A. Then, in the process of the position offset parameter, an image at the coordinate position of each chip is collected, and the template image is subtracted from the image. Ideally, if the chip is not shifted, the difference between the shifts of the two images should be zero, and the two images are completely overlapped. However, in the case of chip offset, the image and the template image have a position offset, as shown in fig. 2B, the image of the chip and the template image cannot be completely overlapped, and the difference between the two images is not zero in these areas.
After comparing all the chips in the wafer with the template image, the offset condition of all the chips in the wafer can be obtained, and further the offset map of the wafer as shown in fig. 2C is obtained, wherein the offset map includes the offset information of all the chips.
Then, in step S3, the position of the SEM inspection tool is calibrated based on the position offset parameter to ensure that the defect position in the chip is located in the center area of the window of the SEM inspection tool.
Prior to performing the calibration, the method comprises: executing different steps according to the size of the position offset parameter obtained in the step S2, as shown in fig. 3, when the position offset parameter is within the control limit range, directly executing a step of directly moving the wafer by the DDL, placing the position where the defect occurs in the chip in the central area of the window of the SEM inspection machine, and taking a picture of the defect position; and when the position deviation parameter exceeds the control limit range, giving an alarm.
Optionally, when the position deviation parameter exceeds the control limit range, after an alarm is given, an equipment engineer is required to manually calibrate the machine, and then the test is performed after the calibration.
The central area is positioned in the middle of a window of the SEM detection machine during photographing, so that the defect position is enlarged by a large enough factor and photographed. Preferably, the central region is located at the center of the window of the SEM inspection apparatus when the defect in the wafer is photographed.
Thus, the description of the steps related to the method for detecting defects of a semiconductor device according to the embodiment of the present invention is completed. After the above steps, other related steps may also be included, which are not described herein again. Besides the above steps, the preparation method of this embodiment may further include other steps among the above steps or between different steps, and these steps may be implemented by various processes in the prior art, and are not described herein again.
In order to solve the problems in the prior art, the invention provides a method for detecting defects of a semiconductor device, and in the method, in order to detect ultra-small defects more accurately, when a defect position image is shot, a position offset parameter of an SEM (scanning Electron microscope) detection machine relative to the defect position in a wafer is firstly obtained, so that the position of the defect in a chip can be placed in the central area of a window of the SEM detection machine when the wafer is directly moved, a larger magnification factor is obtained, and more accurate defect images and defect information are obtained.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A method of detecting defects in a semiconductor device, the method comprising:
providing a wafer to be detected and scanning the wafer to be detected for defects so as to obtain defect distribution information of each chip in the wafer;
obtaining offset parameters of different positions of the SEM detection machine relative to the wafer;
and calibrating the position of the SEM detection machine based on the position deviation parameters, and executing a step of directly moving the wafer so as to enable the position of the defect in the chip to be positioned in the central area of a window of the SEM detection machine.
2. The detection method according to claim 1, wherein prior to performing the calibration, the method further comprises:
and checking whether the position deviation parameter is within the control limit range, if so, correcting the position deviation parameter when the step of directly moving the wafer is executed according to the acquired position deviation information, and placing the position with the defect in the chip in the central area of the SEM detection machine table window.
3. The inspection method of claim 2, wherein if the shift parameter exceeds the control limit, the step of directly moving the wafer is performed according to the obtained shift information, and the defect position in the chip is located in a central area of a window of the SEM inspection machine.
4. The inspection method of claim 1, wherein the central region of the viewing window is substantially in the middle of the viewing window.
5. The inspection method according to claim 1, wherein the wafer to be inspected is scanned for defects by a scanner station to obtain a defect distribution map about the wafer.
6. The detection method according to claim 1, wherein the method of acquiring the position offset parameter includes:
the wafer comprises a plurality of identical chips, and coordinates in one chip are given, wherein the coordinates have certain graphic features;
photographing the position of the coordinate in each chip at a fixed point to shoot a graph at the position of the coordinate;
and comparing the images obtained by shooting to obtain the offset value of the SEM detection machine relative to different chips distributed on the wafer.
7. The inspection method of claim 6, wherein the photographed pattern is compared with an ideal image corresponding to the position coordinates to obtain an offset value of the SEM inspection machine with respect to different chips distributed on the wafer.
8. The inspection method of claim 1, wherein the offset parameter of the SEM inspection tool relative to each chip in the wafer is obtained to obtain an offset map of the wafer.
9. The inspection method of claim 1, wherein the defect position of the chip is located in a central area of a window of an SEM inspection machine, and the defect position is magnified and photographed to obtain an image containing the defect.
10. The inspection method of claim 1, wherein after calibrating the position information, the defect position is accurately located in a central region of a window of the SEM inspection tool according to the calibrated data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910335103.6A CN111863646A (en) | 2019-04-24 | 2019-04-24 | Method for detecting defects of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910335103.6A CN111863646A (en) | 2019-04-24 | 2019-04-24 | Method for detecting defects of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111863646A true CN111863646A (en) | 2020-10-30 |
Family
ID=72951363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910335103.6A Pending CN111863646A (en) | 2019-04-24 | 2019-04-24 | Method for detecting defects of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111863646A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112927170A (en) * | 2021-04-08 | 2021-06-08 | 上海哥瑞利软件股份有限公司 | Automatic defect removal method in semiconductor manufacturing process |
| CN114723650A (en) * | 2020-12-21 | 2022-07-08 | 东方晶源微电子科技（北京）有限公司 | Wafer defect detection method and device, equipment and storage medium |
| CN114994073A (en) * | 2022-05-24 | 2022-09-02 | 上海华力集成电路制造有限公司 | Defect scanning detection analysis method of Die |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020047098A1 (en) * | 2000-10-18 | 2002-04-25 | Applied Materials, Inc. | Substrate defect inspection method and substrate defect inspection system |
| JP2004093317A (en) * | 2002-08-30 | 2004-03-25 | Hamamatsu Photonics Kk | Method for aligning wafer and wafer inspecting device |
| US20070105245A1 (en) * | 2005-11-10 | 2007-05-10 | Hitachi High-Technologies Corporation | Wafer inspection data handling and defect review tool |
| JP2011043413A (en) * | 2009-08-21 | 2011-03-03 | Hitachi High-Technologies Corp | Method for processing image obtained using sem and sem system |
| US20110133066A1 (en) * | 2008-09-16 | 2011-06-09 | Mari Nozoe | Pattern inspection device and method |
| JP2011222636A (en) * | 2010-04-07 | 2011-11-04 | Hitachi High-Technologies Corp | Inspection apparatus, inspection method, and defect coordinate correction method |
| US20140061456A1 (en) * | 2012-08-30 | 2014-03-06 | Kabushiki Kaisha Toshiba | Coordinate correcting method, defect image acquiring method and electron microscope |
| JP2016072544A (en) * | 2014-10-01 | 2016-05-09 | 株式会社日立ハイテクノロジーズ | Review device |
| CN109616426A (en) * | 2017-10-05 | 2019-04-12 | 敖翔科技股份有限公司 | Intelligent defect correction system and its implementation method |
-
2019
- 2019-04-24 CN CN201910335103.6A patent/CN111863646A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020047098A1 (en) * | 2000-10-18 | 2002-04-25 | Applied Materials, Inc. | Substrate defect inspection method and substrate defect inspection system |
| JP2004093317A (en) * | 2002-08-30 | 2004-03-25 | Hamamatsu Photonics Kk | Method for aligning wafer and wafer inspecting device |
| US20070105245A1 (en) * | 2005-11-10 | 2007-05-10 | Hitachi High-Technologies Corporation | Wafer inspection data handling and defect review tool |
| US20110133066A1 (en) * | 2008-09-16 | 2011-06-09 | Mari Nozoe | Pattern inspection device and method |
| JP2011043413A (en) * | 2009-08-21 | 2011-03-03 | Hitachi High-Technologies Corp | Method for processing image obtained using sem and sem system |
| JP2011222636A (en) * | 2010-04-07 | 2011-11-04 | Hitachi High-Technologies Corp | Inspection apparatus, inspection method, and defect coordinate correction method |
| US20140061456A1 (en) * | 2012-08-30 | 2014-03-06 | Kabushiki Kaisha Toshiba | Coordinate correcting method, defect image acquiring method and electron microscope |
| JP2016072544A (en) * | 2014-10-01 | 2016-05-09 | 株式会社日立ハイテクノロジーズ | Review device |
| CN109616426A (en) * | 2017-10-05 | 2019-04-12 | 敖翔科技股份有限公司 | Intelligent defect correction system and its implementation method |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114723650A (en) * | 2020-12-21 | 2022-07-08 | 东方晶源微电子科技（北京）有限公司 | Wafer defect detection method and device, equipment and storage medium |
| CN112927170A (en) * | 2021-04-08 | 2021-06-08 | 上海哥瑞利软件股份有限公司 | Automatic defect removal method in semiconductor manufacturing process |
| CN112927170B (en) * | 2021-04-08 | 2024-03-15 | 上海哥瑞利软件股份有限公司 | Automatic defect removing method in semiconductor manufacturing process |
| CN114994073A (en) * | 2022-05-24 | 2022-09-02 | 上海华力集成电路制造有限公司 | Defect scanning detection analysis method of Die |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5066393B2 (en) | Foreign object / defect inspection / observation system | |
| JP5069904B2 (en) | Designated position specifying method and designated position measuring device | |
| US20060284088A1 (en) | Focus correction method for inspection of circuit patterns | |
| JP5059297B2 (en) | Electron beam observation device | |
| US20150146967A1 (en) | Pattern evaluation device and pattern evaluation method | |
| WO2011148975A1 (en) | Image processing device, charged particle beam device, charged particle beam device adjustment sample, and manufacturing method thereof | |
| KR20130102634A (en) | Charged particle beam device | |
| WO2010079657A1 (en) | Defect observation method and device using sem | |
| JP2009085657A (en) | Sample observation method and system using a scanning electron microscope | |
| CN111863646A (en) | Method for detecting defects of semiconductor device | |
| KR101654825B1 (en) | Method for Inspecting Compact Parts Formed on Substrate in Defect Inspection | |
| KR102557190B1 (en) | Pre-floor defect site review using design | |
| KR20190016695A (en) | Wafer alignment method and wafer inspection method using the same | |
| JP2022548544A (en) | Wafer alignment using multi-scanning electron microscopy | |
| TW201805620A (en) | Defect inspection device | |
| JP2012173072A (en) | Inspection device and inspection method | |
| US20180315670A1 (en) | Guided Metrology Based on Wafer Topography | |
| KR20170032602A (en) | Defect imaging apparatus for imaging defects, Defect inspection system having the same and method of inspecting defects using the same inspection system | |
| US9727799B2 (en) | Method of automatic defect classification | |
| JP2018146492A (en) | Defect inspection system and inspection device and review device used for the same | |
| US10198827B2 (en) | Inspection method and system and a method of inspecting a semiconductor device using the same | |
| JP2009188175A (en) | External appearance inspecting apparatus and method | |
| JP2008218259A (en) | Inspection method and inspection apparatus | |
| JP2013224961A (en) | Inspection device for semiconductor wafer | |
| CN115187641B (en) | Image generation for inspection of semiconductor samples |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20201030 |
|
| RJ01 | Rejection of invention patent application after publication |