CN111858195A

CN111858195A - Interface parameter adapting method for DRAM interface read check and storage medium

Info

Publication number: CN111858195A
Application number: CN202010522534.6A
Authority: CN
Inventors: 汤云平
Original assignee: Rockchip Electronics Co Ltd
Current assignee: Rockchip Electronics Co Ltd
Priority date: 2020-06-10
Filing date: 2020-06-10
Publication date: 2020-10-30

Abstract

A DRAM interface read check interface parameter adaptation method and a storage medium are provided, wherein the method comprises the following steps of adjusting memory particles to a rated frequency for operation, writing check data, adjusting the memory particles to be higher than the rated frequency, adjusting a time sequence parameter, reading the check data and checking to obtain a time sequence parameter interval capable of obtaining correct check data, and obtaining an optimal time sequence parameter according to the time sequence parameter interval. By over-clocking the DRAM above the nominal frequency, the environmental requirements of the ddr grains can be raised and the range over which the timing parameters can be selected becomes smaller. The steps are repeated for specific frequency, so that the system can automatically adjust parameters of any frequency, and the optimization of system power consumption is realized. The DRAM time sequence parameter debugged in this way is more stable in actual work.

Description

Interface parameter adapting method for DRAM interface read check and storage medium

Technical Field

The invention relates to the field of storage, in particular to a scheme capable of reading and checking a debug DRAM interface.

Background

At present, for the read dq calibration (interface read calibration; dq: data input and output pin, calibration) of DRAM, different DRAM particle materials need to be distinguished, and different read dq calibration strategies are used. The DDR3/LPDDR3 on the market offers MPR (multi purpose processor) mode or MRR (modegerster read) MR32/MR40 to perform read replication, but MPR or MRR MR32/MR40 only offers a read replication template for DQ0, and other DQs are highly dependent on the implementation of the particle vendor. In addition, such as DDR2 grain, itself does not provide MPR support, so currently, for the DRAM field, read dq calibration needs to distinguish different sizes of grains, and adaptability is poor. In the prior art, only the interface automatic read-write test method recorded in the device and method for realizing the DDR interface automatic read-write test based on the FPGA application No. 201710419906.0 exists, and no parameter adjustment scheme for DDR particles exists.

Disclosure of Invention

Therefore, a new method for reading and checking the DRAM interface is needed to be provided, so that the problem of configuration of the reading and checking parameters of the DRAM interface is solved;

in order to achieve the above object, the inventor provides an interface parameter adapting method for DRAM interface read verification, which includes the following steps of adjusting memory particles to a rated frequency for operation, writing verification data, adjusting the memory particles to a frequency higher than the rated frequency, adjusting timing parameters, reading the verification data and performing verification, obtaining a timing parameter interval in which correct verification data can be obtained, and obtaining an optimal timing parameter according to the timing parameter interval.

Specifically, the optimal timing parameter is a median value of the timing parameter intervals.

In particular, the timing parameter comprises a phase.

A DRAM interface read check interface parameter adaptive storage medium stores a computer program, and the computer program is executed when being operated, the computer program comprises the following steps of adjusting memory particles to a rated frequency for operation, writing check data in, adjusting the memory particles to be higher than the rated frequency, adjusting time sequence parameters, reading the check data and checking to obtain a time sequence parameter interval capable of obtaining correct check data, and obtaining an optimal time sequence parameter according to the time sequence parameter interval.

In particular, the timing parameter comprises a phase.

By over-clocking the DRAM above the nominal frequency, the environmental requirements of the ddr grains can be raised and the range over which the timing parameters can be selected becomes smaller. The steps are repeated for specific frequency, so that the system can automatically adjust parameters of any frequency, and the optimization of system power consumption is realized. The DRAM time sequence parameter debugged in this way is more stable in actual work.

Drawings

Fig. 1 is a flowchart of a DRAM interface parameter adaptation method according to an embodiment of the present invention.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1, the interface parameter adapting method for DRAM interface read verification according to the present invention includes the following steps, S100 adjusts memory particles to a rated frequency for operation, writes verification data, S102 adjusts the memory particles to a frequency higher than the rated frequency, adjusts timing parameters, reads the verification data and performs verification, obtains a timing parameter interval in which correct verification data can be obtained, and obtains an optimal timing parameter according to the timing parameter interval. Data required for interface read verification (read dq verification) is written into the DRAM granule as verification data by using the stability of reading and writing at low frequency. Here, low frequency may refer to the frequency at which the particle can operate stably, i.e. the nominal frequency or the default frequency, so-called low frequency unfixed value, which may generally be a most conservative value, e.g. 300 MHz. Higher than nominal frequency refers to a frequency at which the current default configuration does not allow, requiring various types of parameter debugging for interface read verification, which may also be referred to herein as high frequency. The specific frequency value can be adjusted according to the reading and checking requirements of the actual interface and different memory particles. The time sequence parameter intervals all refer to: the upper limit and the lower limit of the parameter are in the interval of the parameter which can stably work under the specific high frequency. The optimal timing parameter can be designed as the median value of the timing parameter interval.

The difference between low and high frequencies is that at low frequencies, the time for one period is long and at high frequencies, the time for one period is shorter. The low-frequency time period is long, the time sequence parameter is limited slightly, the time sequence parameter range of stable particles is wider, and the parameter selectable range is wider. Therefore, factory default parameters are generally not problematic. On the contrary, the high frequency time period is short, the selectable range of the parameters is small, the default parameters cannot be used and need to be adjusted. Thus, for each different specific frequency higher than the rated frequency, the optimal parameter configuration corresponding to the specific frequency can be determined by adopting the method. In practical application, the system automatically adjusts the frequency of the DRAM according to the load to realize the optimal performance and power consumption. Because the load of the system (which can be considered as a DRAM plus a host computer) changes in real time and needs different frequencies to meet the requirement, and each frequency needs different parameters, the configuration is carried out by the scheme, so that the system can automatically adjust the parameters of any frequency, and the optimization of the power consumption of the system is realized.

In particular, the timing parameter comprises a phase. In a high-frequency state, check data read from the DRAM is sampled by adjusting the phase difference between DQ and DQS (DQ strobe), a sampling interval is determined, and read DQ calibration is completed.

In other embodiments, if the DRAM supports MPR or the LPDDR3 and DDR3 granules of the MR32/MR40 register, the operation frequency of the granules is directly increased to a high-frequency state that the granules cannot stably operate, and the granules automatically perform timing phase adjustment and correction by configuring the MPR or MR32/MR40 register. If the particles cannot automatically complete the above steps, step S100 is performed. By supporting the MPR or the MR32/MR40 particle characteristics, the automation degree of interface read verification can be improved, and the debugging efficiency is improved.

In particular, the timing parameter comprises a phase.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims

1. The interface parameter adaptation method for DRAM interface read check is characterized by comprising the following steps of adjusting memory particles to a rated frequency for operation, writing check data, adjusting the memory particles to be higher than the rated frequency, adjusting time sequence parameters, reading the check data and checking to obtain a time sequence parameter interval capable of obtaining correct check data, and obtaining optimal time sequence parameters according to the time sequence parameter interval.

2. The method of claim 1, wherein the optimal timing parameter is a median value of timing parameter intervals.

3. The method of claim 1, wherein the timing parameter comprises a phase.

4. The interface parameter adaptive storage medium for DRAM interface read check is characterized in that a computer program is stored, and the computer program is executed when being executed, wherein the computer program comprises the following steps of adjusting memory particles to a rated frequency for operation, writing check data, adjusting the memory particles to be higher than the rated frequency, adjusting time sequence parameters, reading the check data and checking to obtain a time sequence parameter interval capable of obtaining correct check data, and obtaining an optimal time sequence parameter according to the time sequence parameter interval.

5. The DRAM interface read verify interface parameter adaptation storage medium of claim 4, wherein the optimal timing parameter is a median of timing parameter intervals.

6. The interface parameter adaptation storage medium of DRAM interface read verification of claim 4, wherein the timing parameter comprises a phase.