CN111857227B - A power-off retention circuit without separate core power domain - Google Patents
A power-off retention circuit without separate core power domain Download PDFInfo
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- CN111857227B CN111857227B CN202010809213.4A CN202010809213A CN111857227B CN 111857227 B CN111857227 B CN 111857227B CN 202010809213 A CN202010809213 A CN 202010809213A CN 111857227 B CN111857227 B CN 111857227B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is AC or DC
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Abstract
The invention discloses a power-down holding circuit without an independent core power domain, which comprises a holding control signal generating circuit, a holding circuit and a level conversion circuit for converting an input signal IN of a core voltage VDD level into an output signal OUTP and an output signal OUTN of an input output voltage VDDIO level, wherein the holding control signal generating circuit comprises a first NMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a resistor, and the holding circuit comprises a sixth PMOS tube, a ninth PMOS tube, a sixth NMOS tube, a ninth NMOS tube and a third NMOS tube. The design is simplified, the layout and the wiring are facilitated, and the layout area is saved.
Description
Technical Field
The invention relates to a power down holding circuit.
Background
In the DDR (double Rate synchronous dynamic random Access memory) power-off mode, the core module power is turned off, thereby realizing low power consumption. In this mode, the signal state before power-off needs to be maintained, so that the signal before power-off can be read quickly when exiting the power-off mode. A separate core power domain is typically required to maintain the core signal state.
Disclosure of Invention
The invention aims to provide a power-down holding circuit without an independent core power domain, so that the design is simplified, the layout and the wiring are convenient, and the layout area is saved.
The technical scheme for achieving the purpose is as follows:
A power-down holding circuit without a separate core power domain includes a holding control signal generating circuit, a holding circuit, and a level converting circuit for converting an input signal IN of a core voltage VDD level into an output signal OUTP and an output signal OUTN of an input-output voltage VDDIO level, wherein,
The holding control signal generating circuit comprises a first NMOS tube, a fifth NMOS tube, a first PMOS tube, a fifth PMOS tube and a resistor,
The source electrodes of the first PMOS tube and the fifth PMOS tube are connected with an input output voltage VDDIO;
The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube;
the grid electrode of the first PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube;
The grid electrode of the first NMOS tube is connected with the core voltage VDD through the resistor, the grid electrode of the first NMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube, and the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube;
the drain electrode of the fourth PMOS tube and the connecting end of the drain electrode of the fourth NMOS tube output hold control signals; a control signal is output holdb from the connection end of the drain electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube;
The holding circuit comprises a sixth PMOS tube, a ninth PMOS tube and a sixth NMOS tube;
the sources of the sixth PMOS tube and the seventh PMOS tube are connected with an input/output voltage VDDIO;
the source electrodes of the sixth NMOS tube and the seventh NMOS tube are grounded to VSS;
the drain electrode of the sixth PMOS tube is connected with the source electrode of the eighth PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the eighth NMOS tube;
The drain electrode of the seventh PMOS tube is connected with the source electrode of the ninth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube;
The connecting end of the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube is connected with an output signal OUTP;
the connecting end of the grid electrode of the seventh PMOS tube and the grid electrode of the seventh NMOS tube is connected with an output signal OUTN;
The gate of the eighth PMOS tube and the connected end of the gate of the ninth PMOS tube are connected with holdb control signals;
and the connection end of the grid electrode of the eighth NMOS tube and the grid electrode of the ninth NMOS tube is connected with a hold control signal.
Preferably, the level shift circuit transmits a hold control signal and holdb control signals to the holding circuit.
The invention has the beneficial effects that the core power supply (VDD) is utilized to power down and power up, and the hold/holdb control signal is generated in the input/output high power domain (VDDIO) so as to lock and maintain the state before the power down when the core power supply is powered down. And an independent core power domain is not needed, so that the design is simplified, the layout and the wiring are facilitated, and the layout area is saved.
Drawings
FIG. 1 is a circuit diagram of a power down holding circuit of the present invention;
Fig. 2 is a schematic diagram of input/output waveforms of the power-down holding circuit of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings.
Referring to fig. 1, the power-down holding circuit without a separate core power domain of the present invention includes a holding control signal generating circuit, a holding circuit, and a level converting circuit.
The hold control signal generating circuit comprises first to fifth NMOS transistors NM1 to NM5, first to fifth PMOS transistors PM1 to PM5 and a resistor R1.
The sources of the first to fifth PMOS tubes PM1 to PM5 are connected with the input/output voltage VDDIO, and the sources of the first to fifth NMOS tubes NM1 to NM5 are grounded to VSS.
The drain electrode of the first PMOS tube PM1 is connected with the drain electrode of the first NMOS tube NM1, the drain electrode of the second PMOS tube PM2 is connected with the drain electrode of the second NMOS tube NM2, the drain electrode of the third PMOS tube PM3 is connected with the drain electrode of the third NMOS tube NM3, the drain electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the fourth NMOS tube NM4, and the drain electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the fifth NMOS tube NM 5.
The grid electrode of the first PMOS tube PM1 is connected with the drain electrode of the third PMOS tube PM3, the grid electrode of the second PMOS tube PM2 is connected with the grid electrode of the second NMOS tube NM2, the grid electrode of the third PMOS tube PM3 is connected with the drain electrode of the first PMOS tube PM1, the grid electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the third PMOS tube PM3, and the grid electrode of the fifth PMOS tube PM5 is connected with the drain electrode of the fourth PMOS tube PM 4;
The grid electrode of the first NMOS tube NM1 is connected with the core voltage VDD through a resistor R1, the grid electrode of the first NMOS tube NM1 is connected with the grid electrode of the second PMOS tube PM2, the grid electrode of the third NMOS tube NM3 is connected with the drain electrode of the second NMOS tube NM2, the grid electrode of the fourth NMOS tube NM4 is connected with the drain electrode of the third PMOS tube PM3, and the grid electrode of the fifth NMOS tube NM5 is connected with the drain electrode of the fourth PMOS tube PM 4;
The drain of the fourth PMOS transistor PM4 and the drain of the fourth NMOS transistor NM4 are connected to each other to output a hold control signal, and the drain of the fifth PMOS transistor PM5 and the drain of the fifth NMOS transistor NM5 are connected to each other to output holdb a control signal. The core voltage VDD is powered down (from 1 to 0), the gates of the second NMOS transistor NM2 and the second PMOS transistor PM2 are changed from 1 to 0, so that the second NMOS transistor NM2 is turned off, the second PMOS transistor PM2 is turned on, the gate of the third NMOS transistor NM3 is pulled up to the input/output voltage VDDIO, and the third NMOS transistor NM3 is turned on. In the process of the core voltage VDD from 1 to 0, the first NMOS transistor NM1 turns off the pipe, and the gate of the third PMOS transistor PM3 is pulled high through the first PMOS transistor PM1, so that the third PMOS transistor PM3 is turned off. The drain end of the third PMOS transistor PM3 is pulled down to VSS (0 potential) by the third NMOS transistor NM3, and the hold control signal is pulled up to high potential through the inverter fourth PMOS transistor PM 4/fourth NMOS transistor NM4, as shown in fig. 2.
The level conversion circuit converts an input signal IN of the core voltage VDD level into an output signal OUTP and an output signal OUTN of the input-output voltage VDDIO level. At the core voltage VDD, which is powered down (from 1 to 0), the input signal IN is IN a high-impedance (Hi-Z) state. The output signal OUTP/OUTN at this time needs to be held by a holding circuit, which holds the state before power failure. The level shifter circuit transmits the hold control signal and holdb control signal to the hold circuit.
The holding circuit comprises sixth to ninth PMOS tubes PM1 to PM5 and sixth to ninth NMOS tubes NM6 to NM9.
The sources of the sixth PMOS tube PM6 and the seventh PMOS tube PM7 are connected with an input/output voltage VDDIO, and the sources of the sixth NMOS tube NM6 and the seventh NMOS tube NM7 are grounded to VSS;
The drain electrode of the sixth PMOS tube PM6 is connected with the source electrode of the eighth PMOS tube PM8, and the drain electrode of the eighth PMOS tube PM8 is connected with the drain electrode of the eighth NMOS tube NM 8;
the drain electrode of the seventh PMOS tube PM7 is connected with the source electrode of the ninth PMOS tube PM9, and the drain electrode of the ninth PMOS tube PM9 is connected with the drain electrode of the ninth NMOS tube NM 9;
the drain electrode of the ninth PMOS tube PM9 and the connecting end of the drain electrode of the ninth NMOS tube NM9 are connected with the output signal OUTP;
the drain electrode of the eighth PMOS tube PM8 and the connecting end of the drain electrode of the eighth NMOS tube NM8 are connected with the output signal OUTN;
The gate of the eighth PMOS pipe PM8 and the gate of the ninth PMOS pipe PM9 are connected with holdb control signals, and the gate of the eighth NMOS pipe NM8 and the gate of the ninth NMOS pipe NM9 are connected with hold control signals.
The core voltage VDD is powered down (from 1 to 0), the hold/holdb control signals are 1/0 respectively, the eighth NMOS tube NM8, the ninth NMOS tube NM9, the eighth PMOS tube PM8 and the ninth PMOS tube PM9 are opened, the sixth to ninth PMOS tubes PM1-PM5 and the sixth to ninth NMOS tubes NM6-NM9 are latch circuits formed by two inverters, and the output signal OUTP/OUTN latches the state before power down.
The above embodiments are provided for illustrating the present invention and not for limiting the present invention, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the present invention, and thus all equivalent technical solutions should be defined by the claims.
Claims (2)
1. A power-down holding circuit without a separate core power domain is characterized by comprising a holding control signal generating circuit, a holding circuit and a level converting circuit for converting an input signal IN of a core voltage VDD level into an output signal OUTP and an output signal OUTN of an input/output voltage VDDIO level, wherein,
The holding control signal generating circuit comprises a first NMOS tube, a fifth NMOS tube, a first PMOS tube, a fifth PMOS tube and a resistor,
The source electrodes of the first PMOS tube and the fifth PMOS tube are connected with an input output voltage VDDIO;
The drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube;
the grid electrode of the first PMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, and the grid electrode of the fifth PMOS tube is connected with the drain electrode of the fourth PMOS tube;
The grid electrode of the first NMOS tube is connected with the core voltage VDD through the resistor, the grid electrode of the first NMOS tube is connected with the grid electrode of the second PMOS tube, the grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the fourth NMOS tube is connected with the drain electrode of the third PMOS tube, and the grid electrode of the fifth NMOS tube is connected with the drain electrode of the fourth PMOS tube;
the drain electrode of the fourth PMOS tube and the connecting end of the drain electrode of the fourth NMOS tube output hold control signals; a control signal is output holdb from the connection end of the drain electrode of the fifth PMOS tube and the drain electrode of the fifth NMOS tube;
The holding circuit comprises a sixth PMOS tube, a ninth PMOS tube and a sixth NMOS tube;
the sources of the sixth PMOS tube and the seventh PMOS tube are connected with an input/output voltage VDDIO;
the source electrodes of the sixth NMOS tube and the seventh NMOS tube are grounded to VSS;
the drain electrode of the sixth PMOS tube is connected with the source electrode of the eighth PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the eighth NMOS tube;
The drain electrode of the seventh PMOS tube is connected with the source electrode of the ninth PMOS tube, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube;
The connecting end of the grid electrode of the sixth PMOS tube and the grid electrode of the sixth NMOS tube is connected with an output signal OUTP;
the connecting end of the grid electrode of the seventh PMOS tube and the grid electrode of the seventh NMOS tube is connected with an output signal OUTN;
The gate of the eighth PMOS tube and the connected end of the gate of the ninth PMOS tube are connected with holdb control signals;
and the connection end of the grid electrode of the eighth NMOS tube and the grid electrode of the ninth NMOS tube is connected with a hold control signal.
2. The power down holding circuit without a separate core power domain according to claim 1, wherein the level shifter circuit transmits hold control signals and holdb control signals to the holding circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010809213.4A CN111857227B (en) | 2020-08-12 | 2020-08-12 | A power-off retention circuit without separate core power domain |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010809213.4A CN111857227B (en) | 2020-08-12 | 2020-08-12 | A power-off retention circuit without separate core power domain |
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| CN111857227B true CN111857227B (en) | 2024-12-27 |
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| CN212411087U (en) * | 2020-08-12 | 2021-01-26 | 灿芯半导体(苏州)有限公司 | Power-down holding circuit without independent core power domain |
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| KR100302610B1 (en) * | 1999-05-21 | 2001-09-26 | 김영환 | High voltage driving circuit |
| US7839016B2 (en) * | 2007-12-13 | 2010-11-23 | Arm Limited | Maintaining output I/O signals within an integrated circuit with multiple power domains |
| US8710811B2 (en) * | 2012-01-03 | 2014-04-29 | Nan Ya Technology Corporation | Voltage regulator with improved voltage regulator response and reduced voltage drop |
| CN105094200A (en) * | 2015-08-14 | 2015-11-25 | 灿芯半导体(上海)有限公司 | Current source circuit |
| CN108958347A (en) * | 2018-07-19 | 2018-12-07 | 池州睿成微电子有限公司 | A kind of reference circuit with negative-feedback |
| CN110673681A (en) * | 2019-03-07 | 2020-01-10 | 深圳市芯天下技术有限公司 | Band gap reference circuit |
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| CN212411087U (en) * | 2020-08-12 | 2021-01-26 | 灿芯半导体(苏州)有限公司 | Power-down holding circuit without independent core power domain |
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