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CN111849735A - A chip with a composite layer and its application in biological detection - Google Patents

A chip with a composite layer and its application in biological detection Download PDF

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CN111849735A
CN111849735A CN201910346219.XA CN201910346219A CN111849735A CN 111849735 A CN111849735 A CN 111849735A CN 201910346219 A CN201910346219 A CN 201910346219A CN 111849735 A CN111849735 A CN 111849735A
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王琎
胡庚
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Chengdu Qitan Technology Ltd
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Abstract

本发明提供了一种具有复合层的芯片及其在生物检测中的应用,所述芯片包括至少上下设置的第一基层和第二基层,所述的第一基层上设置有至少一个通向第二基层的第一盲孔,所述的芯片上还设置有至少一个穿过第二基层的金属化过孔,所述的第一盲孔下面设置有电极,所述的芯片设置有触点,所述的电极与触点通过线路相连。本发明将塑料和金属结合,开发出具有复合层的芯片,通过所述芯片的基层、电路层和内部线路的合理布局,实现芯片的基本功能,并且制作简单,成本低廉。

Figure 201910346219

The present invention provides a chip with a composite layer and its application in biological detection. The chip includes at least a first base layer and a second base layer disposed up and down, and at least one base layer leading to a second base layer is disposed on the first base layer. The first blind hole of the second base layer, the chip is also provided with at least one metallized via hole passing through the second base layer, the electrode is provided under the first blind hole, and the chip is provided with a contact, The electrodes are connected with the contacts through lines. The invention combines plastic and metal to develop a chip with a composite layer. The basic function of the chip is realized through the rational layout of the base layer, circuit layer and internal circuit of the chip, and the production is simple and the cost is low.

Figure 201910346219

Description

一种具有复合层的芯片及其在生物检测中的应用A chip with a composite layer and its application in biological detection

技术领域technical field

本发明属于芯片技术领域,特别涉及一种具有复合层的芯片及其在生物检测中的应用。The invention belongs to the technical field of chips, and particularly relates to a chip with a composite layer and its application in biological detection.

背景技术Background technique

随着电子和信息技术的飞速发展,我国已经进入了信息时代。芯片作为微型集成电路,广泛应用于电脑、手机、家电、汽车、高铁、电网、医疗仪器、机器人、工业控制等各种电子产品和系统,是高端制造业的核心基石。芯片是由基层和线路构成的,基层采用单晶硅晶圆制作,采用光刻、掺杂、化学机械抛光(CMP)等技术制成金属-氧化物半导体场效应晶体管(MOSFET)或双极型晶体管(BJT)等组件,再利用薄膜和CMP技术制成线路,完成芯片制作。With the rapid development of electronics and information technology, our country has entered the information age. As miniature integrated circuits, chips are widely used in various electronic products and systems such as computers, mobile phones, home appliances, automobiles, high-speed rail, power grids, medical instruments, robots, and industrial control. They are the core cornerstone of high-end manufacturing. The chip is composed of a base layer and a circuit. The base layer is made of a single crystal silicon wafer, and a metal-oxide semiconductor field effect transistor (MOSFET) or bipolar type is made by lithography, doping, chemical mechanical polishing (CMP) and other technologies. Transistor (BJT) and other components, and then use thin film and CMP technology to make circuits to complete chip production.

目前,主流的芯片基层为单晶硅。在硅晶体制造的电子元器件和芯片中,载流子能以0.1m2/V.s的高迁移率快速传输。但目前的硅晶体生产工艺成本十分昂贵,对需求量巨大的消费电子产品行业,往往难以承受这种过于高昂的成本,也不利于芯片的推广使用。因此,科研工作者致力于寻找和开发其他的廉价替代品。塑料作为一种廉价的可塑性极强的材料进入了科学家的视野。目前,主要的研究方向是对绝缘的塑料材料进行物理和化学改性,使之能够导电。例如,奥地利科学家采用聚苯乙烯等塑料成功制造一款太阳能电池,其效率为3%;2011年,比利时微电子研究中心的科学家研制了一种塑料芯片原型;荷兰飞利浦公司推出了一款轻薄柔软的塑料计算机显示屏,这种显示屏的制作材料是塑料基半导体;日本科学家研制出包含几百个有机计算机芯片的柔韧的导电塑料,采用这种导电塑料制造出了新型的平板显示器和电子标签。虽然塑料基半导体或导电塑料的研究取得了一些成果,但距离大规模、低成本的应用还有很大差距。At present, the mainstream chip base layer is monocrystalline silicon. In electronic components and chips made of silicon crystals, carriers can be transported rapidly with a high mobility of 0.1 m 2 /Vs. However, the current silicon crystal production process is very expensive, and the consumer electronics industry, which has a huge demand, is often unable to bear this excessively high cost, and is not conducive to the promotion and use of chips. Therefore, researchers are devoted to finding and developing other cheap alternatives. Plastic has entered the field of vision of scientists as a cheap and extremely malleable material. At present, the main research direction is the physical and chemical modification of insulating plastic materials to make them conductive. For example, Austrian scientists used plastics such as polystyrene to successfully create a solar cell with an efficiency of 3%; in 2011, scientists at the Belgian Microelectronics Research Center developed a prototype of a plastic chip; Philips of the Netherlands launched a thin, flexible The plastic computer display screen of this kind of display is made of plastic-based semiconductors; Japanese scientists have developed flexible conductive plastics containing hundreds of organic computer chips, and new types of flat-panel displays and electronic labels have been made using this conductive plastic. . Although research on plastic-based semiconductors or conductive plastics has yielded some results, there is still a long way to go before large-scale, low-cost applications.

现在芯片的封装材料普遍采用塑料和金属,适用于绝大多数芯片应用场景。如果能将普通的塑料材料应用于芯片基层,将大大降低芯片的生产成本。然而,这是一个问题。Nowadays, the packaging materials of chips are generally plastic and metal, which are suitable for most chip application scenarios. If ordinary plastic materials can be applied to the base layer of the chip, the production cost of the chip will be greatly reduced. However, this is a problem.

专利CN201710699800.0公开了一种基于无线遥控的污秽区在线自动监控系统,该系统的电导传感器包括上表面为波浪形的绝缘塑料基材,绝缘塑料基材的上表面镀有绝缘瓷,绝缘塑料基材两端各设置有金属夹片,金属夹片与绝缘瓷紧密贴合,金属夹片外周套有防护套,电导传感器还包括与两块所述金属夹片连接的驱动芯片,驱动芯片连接至主板。该发明在金属夹片上接连电极,实现整个监控系统的运转。Patent CN201710699800.0 discloses an online automatic monitoring system for dirty areas based on wireless remote control. The conductance sensor of the system includes an insulating plastic substrate with a wavy upper surface, and the upper surface of the insulating plastic substrate is plated with insulating porcelain and insulating plastic. Both ends of the base material are provided with metal clips, the metal clips are closely attached to the insulating porcelain, and the outer circumference of the metal clips is covered with a protective sleeve. to the motherboard. The invention connects electrodes on the metal clip to realize the operation of the entire monitoring system.

另外,芯片在生物领域,尤其是基因检测方面,具有重要的应用价值,芯片可以代替传统激光镜头、荧光染色剂等成为新的测序仪,面对海量的基因检测和分析数据,多功能芯片的应用是未来的发展方向。目前新一代基因测序技术利用纳米尺寸的孔作为传感器,当核酸分子通过纳米孔时,检测通过每个纳米孔的离子电流,根据不同碱基过孔时的电流特点,通过追踪电流的变化,确定每个基因组片段的基因序列。例如,专利CN201810019657.0中公开了一种一次性纳米孔生物传感器,包括顺次层叠设置的衬底、电极层和顶盖,顶盖设置有直径为5-200μm的微孔,微孔用于注入纳米孔和磷脂薄膜,衬底和顶盖均为塑料层,电极为设置于衬底表面的一对银电极,微孔开设于绝缘覆盖件,绝缘覆盖件覆盖于一个银电极表面,微孔设置在银电极顶部,使该银电极仅通过微孔暴露。In addition, the chip has important application value in the biological field, especially in the field of genetic testing. The chip can replace the traditional laser lens, fluorescent dye, etc. to become a new sequencer. Applications are the way of the future. At present, the next-generation gene sequencing technology uses nano-sized pores as sensors. When nucleic acid molecules pass through the nano-pore, the ionic current passing through each nano-pore is detected. The gene sequence of each genome segment. For example, patent CN201810019657.0 discloses a disposable nanoporous biosensor, which includes a substrate, an electrode layer and a top cover that are stacked in sequence. The top cover is provided with micropores with a diameter of 5-200 μm, and the micropores are used for Nanopores and phospholipid films are injected, the substrate and the top cover are both plastic layers, the electrodes are a pair of silver electrodes arranged on the surface of the substrate, the micropores are opened on the insulating cover, the insulating cover covers the surface of a silver electrode, and the micropores It is placed on top of the silver electrode so that the silver electrode is only exposed through the micropores.

专利CN200880126160.3中公开了一种形成分隔两个体积的水溶液的层的方法,在形成的装置中上部为包含腔室的装置,下部包括至少一个通向腔室的凹槽的非导电性材料的主体,腔室与凹槽之间形成生物层脂质膜(BLM),该装置具有一对电极,上电极位于腔室中并引出腔室,下电极位于凹槽下部并引出非导电性材料主体。Patent CN200880126160.3 discloses a method of forming a layer separating two volumes of an aqueous solution, in which the upper part of the formed device is a device containing a chamber, and the lower part includes at least one non-conductive material leading to a groove leading to the chamber The main body of the device, a biolayer lipid membrane (BLM) is formed between the chamber and the groove, the device has a pair of electrodes, the upper electrode is located in the chamber and leads out of the chamber, and the lower electrode is located in the lower part of the groove and leads out the non-conductive material main body.

随着芯片逐渐应用于纳米孔基因检测中,芯片的结构应该适应海量基因检测的要求,使得结构更加合理,操作更加方便,功能更加多样。本发明将塑料材料和金属材料结合,开发出具有复合层的芯片,通过所述芯片的复合层的合理布局,实现芯片应用于纳米孔基因检测的基本功能。As the chip is gradually used in nanopore genetic testing, the structure of the chip should meet the requirements of mass genetic testing, making the structure more reasonable, the operation more convenient, and the functions more diverse. The invention combines the plastic material and the metal material to develop a chip with a composite layer, and through the rational layout of the composite layer of the chip, the basic function of the chip applied to the nanopore gene detection is realized.

发明内容SUMMARY OF THE INVENTION

为达到上述目的,本发明提供了一种具有复合层的芯片,所述芯片包括至少上下设置的第一基层和第二基层,所述的第一基层上设置有至少一个通向第二基层的第一盲孔,所述的芯片上还设置有至少一个穿过第二基层的金属化过孔,所述的第一盲孔下面设置有电极,所述的芯片设置有触点,所述的电极与触点通过线路相连。In order to achieve the above purpose, the present invention provides a chip with a composite layer, the chip includes at least a first base layer and a second base layer arranged up and down, and at least one base layer leading to the second base layer is provided on the first base layer. A first blind hole, the chip is also provided with at least one metallized via hole passing through the second base layer, an electrode is provided under the first blind hole, the chip is provided with a contact, the The electrodes and the contacts are connected by wires.

所述的第一基层上、下表面或第一基层上方还设有第一电极,所述的芯片还设有第一触点,所述的第一电极与第一触点通过线路相连。A first electrode is further provided on the upper and lower surfaces of the first base layer or above the first base layer, the chip is further provided with a first contact, and the first electrode is connected with the first contact through a circuit.

优选的,所述的第二基层中设置有内层线路,更优选的,所述金属化过孔的内壁上具有向外延伸的内层线路,所述内层线路延伸并嵌入第一基层和第二基层的内部,成为互联电路;所述互联电路能够在所述芯片内部延伸到并连接其他电路元器件,实现多个元器件的互联,有利于所述芯片实现多种功能应用。Preferably, the second base layer is provided with an inner layer circuit, more preferably, the inner wall of the metallized via has an inner layer circuit extending outward, and the inner layer circuit extends and is embedded in the first base layer and The inside of the second base layer becomes an interconnection circuit; the interconnection circuit can extend to and connect to other circuit components inside the chip to realize interconnection of multiple components, which is beneficial for the chip to realize multiple functional applications.

优选的,所述的第一基层和第二基层之间还设置有至少一个第三基层。更优选的,所述的第一基层和第二基层之间还设置有1-5个第三基层。例如,所述的第一基层和第二基层之间还设置有1、2、3、4或5个第三基层。Preferably, at least one third base layer is further arranged between the first base layer and the second base layer. More preferably, 1-5 third base layers are further arranged between the first base layer and the second base layer. For example, 1, 2, 3, 4 or 5 third base layers are further arranged between the first base layer and the second base layer.

本发明所述的芯片的一种形式,所述的第一基层上还设置有至少一个通向第二基层的第二盲孔,所述的第二盲孔下面设置有第一电极。所述芯片上设置至少两个贯穿第二基层的金属化过孔,所述金属化过孔的外壁设有内层线路。所述第一电极通过金属线路联通第一金属化过孔,电极通过金属线路联通第二金属化过孔。所述第一金属化过孔的内层线路或第一金属化过孔在第二基层下表面的延伸金属线路上设有第一触点;所述第二金属化过孔的内层线路或第二金属化过孔在第二基层下表面的延伸金属线路上设有触点。In one form of the chip of the present invention, the first base layer is further provided with at least one second blind hole leading to the second base layer, and the second blind hole is provided with a first electrode below. At least two metallized via holes penetrating the second base layer are arranged on the chip, and inner layer lines are arranged on the outer walls of the metallized via holes. The first electrode is communicated with the first metallized via hole through a metal line, and the electrode is communicated with the second metallized via hole through the metal line. The inner layer line of the first metallized via or the first metallization via is provided with a first contact on the extended metal line on the lower surface of the second base layer; the inner layer line of the second metallization via or The second metallized via is provided with a contact on the extended metal line on the lower surface of the second base layer.

在本发明的一个具体实施方式中,所述第一基层上设有一个通向第二基层的第二盲孔,所述第二盲孔下面设置有第一电极,所述第一电极通过延伸金属线路与所述第一金属化过孔联通,所述第一触点设在第一金属化过孔在第二基层下表面的延伸金属线路上;所述第一金属化过孔和第二金属化过孔贯穿第二基层,但不贯穿第一基层;所述第一金属化过孔和第二金属化过孔在所述第二基层中设有内层线路,所述内层线路围绕第一金属化过孔和第二金属化过孔的孔壁展开。所述触点位于第二金属化过孔在第二基层下表面的延伸金属线路上。所述电极设在所述第一盲孔的底部,并通过延伸金属线路连接第二金属化过孔,由此间接连接内层线路和第二基层下表面的环形金属线路,进而连接所述触点。In a specific embodiment of the present invention, the first base layer is provided with a second blind hole leading to the second base layer, a first electrode is provided under the second blind hole, and the first electrode extends through the The metal circuit communicates with the first metallized via, and the first contact is arranged on the extended metal circuit of the first metallized via on the lower surface of the second base layer; the first metallized via and the second The metallized via passes through the second base layer, but does not penetrate the first base layer; the first metallized via hole and the second metallized via hole are provided with inner layer lines in the second base layer, and the inner layer lines surround The hole walls of the first metallized via and the second metallized via are spread out. The contact is located on the extended metal line of the second metallized via on the lower surface of the second base layer. The electrodes are arranged at the bottom of the first blind holes, and are connected to the second metallized vias by extending metal lines, thereby indirectly connecting the inner layer lines and the annular metal lines on the lower surface of the second base layer, and then connecting the contacts. point.

使用时,所述第一触点和触点连接电源,即可在所述第一电极和电极之间形成电压,所述第一盲孔和第二盲孔上方连通导电介质。When in use, the first contact and the contact are connected to a power source, so that a voltage can be formed between the first electrode and the electrode, and a conductive medium is connected above the first blind hole and the second blind hole.

本发明所述的芯片的另一种形式,所述第一电极设置在第一基层的上表面,优选的,所述第一电极设置在第一金属化过孔上端边缘,更优选的,所述的第一电极设置在所述第一金属化过孔上端附近。In another form of the chip according to the present invention, the first electrode is arranged on the upper surface of the first base layer, preferably, the first electrode is arranged at the upper edge of the first metallized via hole, more preferably, the The first electrode is arranged near the upper end of the first metallized via.

所述电极设置在第一基层底部下表面,并通过所述第一盲孔的底部,更优选的,所述电极设置在第一基层和第二基层之间,更优选的,所述的电极覆盖所述第一盲孔的整个底面,特别优选的,所述电极延伸到第二金属化过孔。The electrode is arranged on the lower surface of the bottom of the first base layer and passes through the bottom of the first blind hole, more preferably, the electrode is arranged between the first base layer and the second base layer, more preferably, the electrode Covering the entire bottom surface of the first blind hole, particularly preferably, the electrode extends to the second metallized via hole.

所述第一盲孔位于第一基层,第一盲孔的底部设有电极,所述第一盲孔、第一电极和电极构成孔电极。The first blind hole is located on the first base layer, the bottom of the first blind hole is provided with an electrode, and the first blind hole, the first electrode and the electrode constitute a hole electrode.

所述第一触点位于所述第一金属化过孔在第一基层上表面或第二基层下表面的延伸金属线路,所述触点位于第二金属化过孔在第一基层上表面或第二基层下表面的延伸金属线路。所述第一电极能够通过第一金属化过孔在第一基层上表面或第二基层下表面的环形金属线路以及内层线路连接所述第一触点,电极能够通过第二金属化过孔在第一基层上表面或第二基层下表面的环形金属线路以及内层线路连接所述触点。The first contact is located on the extended metal line of the first metallized via on the upper surface of the first base layer or the lower surface of the second base layer, and the contact is located on the upper surface of the second metallized via or the first base layer. The extended metal lines on the lower surface of the second base layer. The first electrode can be connected to the first contact through a first metallized via on the ring metal circuit on the upper surface of the first base layer or the lower surface of the second base layer and the inner layer circuit, and the electrode can pass through the second metallized through hole Ring-shaped metal lines and inner-layer lines on the upper surface of the first base layer or the lower surface of the second base layer connect the contacts.

更选的,所述的金属线路和内层线路为铜箔。More preferably, the metal circuit and the inner layer circuit are copper foils.

所述的第一基层和第二基层材料为塑料。The materials of the first base layer and the second base layer are plastics.

优选的,所述第一基层的材料为塑料,优选的,所述第一基层的材料为聚酰亚胺树脂板、FR-4板材、FR-1板材或CEM-1/3板材,更优选的,所述FR-4板为具有FR-4等级的玻璃纤维板或环氧树脂板材。在本发明的一个具体实施方式中,所述第一基层的材料为聚酰亚胺树脂板。Preferably, the material of the first base layer is plastic, preferably, the material of the first base layer is polyimide resin board, FR-4 board, FR-1 board or CEM-1/3 board, more preferably Yes, the FR-4 board is a glass fiber board or an epoxy resin board with FR-4 grade. In a specific embodiment of the present invention, the material of the first base layer is a polyimide resin board.

所述第一基层的厚度为0.05-0.5mm,优选的,所述第一基层的厚度为0.08-0.2mm。在本发明的一个具体实施方式中,所述第一基层的厚度为0.1mm。The thickness of the first base layer is 0.05-0.5mm, preferably, the thickness of the first base layer is 0.08-0.2mm. In a specific embodiment of the present invention, the thickness of the first base layer is 0.1 mm.

所述第一盲孔和第二盲孔设置在所述第一基层的上表面,优选的,所述第一盲孔和第二盲孔为圆形孔;优选的,所述第一盲孔的孔径为0.05-0.2mm,更优选的,所述第一盲孔的孔径为0.1-0.15mm。所述第一盲孔可以通过激光钻孔的技术形成。优选的,所述第二盲孔的孔径为0.5-2mm,更优选的,所述第二盲孔的孔径为1-1.5mm。所述第二盲孔可以通过激光钻孔的技术形成。The first blind hole and the second blind hole are arranged on the upper surface of the first base layer, preferably, the first blind hole and the second blind hole are circular holes; preferably, the first blind hole The hole diameter of the first blind hole is 0.05-0.2mm, and more preferably, the hole diameter of the first blind hole is 0.1-0.15mm. The first blind hole can be formed by laser drilling technology. Preferably, the diameter of the second blind hole is 0.5-2 mm, and more preferably, the diameter of the second blind hole is 1-1.5 mm. The second blind hole can be formed by laser drilling technology.

所述第二基层的材料为塑料,优选的,所述第二基层的材料为聚酰亚胺树脂板、FR-4板材、FR-1板材或CEM-1/3板材,更优选的,所述第二基层的材料为FR-4板材,更优选的,所述FR-4板材为具有FR-4等级的玻璃纤维板或环氧树脂板材。在本发明的一个具体实施方式中,所述第二基层的材料为FR-4环氧树脂板材。The material of the second base layer is plastic, preferably, the material of the second base layer is polyimide resin board, FR-4 board, FR-1 board or CEM-1/3 board, more preferably, the The material of the second base layer is FR-4 board, more preferably, the FR-4 board is a glass fiber board or an epoxy resin board with FR-4 grade. In a specific embodiment of the present invention, the material of the second base layer is FR-4 epoxy resin board.

所述第一基层和第二基层的材料绝缘,保证所述芯片的电流信号只能由所述金属线路和内层线路传导,便于根据实际需求设计不同结构的金属线路和内层线路;所述第一基层和第二基层的材料耐腐蚀,在保证一定强度的同时,还具有较强的抗冲击性,使所述芯片的适用范围广泛;所述第一基层和第二基层材料的可塑性强,便于利用PCB加工技术制作芯片。The materials of the first base layer and the second base layer are insulated to ensure that the current signal of the chip can only be conducted by the metal circuit and the inner layer circuit, which facilitates the design of metal circuits and inner layer circuits of different structures according to actual needs; the The materials of the first base layer and the second base layer are corrosion-resistant, and while ensuring a certain strength, they also have strong impact resistance, so that the chip has a wide range of applications; the first base layer and the second base layer materials have strong plasticity , it is convenient to use PCB processing technology to make chips.

在本发明的一个具体实施方式中,所述芯片包括第一基层和第二基层。In a specific embodiment of the present invention, the chip includes a first base layer and a second base layer.

在本发明的另一个具体实施方式中,所述芯片包括第一基层、第二基层和第一基层与第二基层之间的第三基层。In another specific embodiment of the present invention, the chip includes a first base layer, a second base layer, and a third base layer between the first base layer and the second base layer.

本发明还提供了所述芯片在生物检测中的应用,优选的,所述芯片在核酸测序中的应用,更优选的,所述芯片在纳米孔核酸测序中的应用。The present invention also provides the application of the chip in biological detection, preferably, the application of the chip in nucleic acid sequencing, more preferably, the application of the chip in nanopore nucleic acid sequencing.

所述芯片的内层线路能够与所需的检测分析设备连接,所述芯片的孔电极、第一触点和触点接入电流,电流再通过内层线路传导到需要的检测分析设备,因此,所述芯片对检测分析设备实现了控制作用。The inner layer circuit of the chip can be connected with the required detection and analysis equipment, the hole electrode, the first contact and the contact of the chip are connected to the current, and the current is then conducted to the required detection and analysis equipment through the inner layer circuit, so , the chip can control the detection and analysis equipment.

本发明还提供了所述芯片作为生物监测的芯片的应用,优选的,所述芯片作为核酸测序装置的芯片的应用,更优选的,所述芯片作为纳米孔测序装置的芯片的应用。所述芯片相对于硅基材的芯片,能够实现多层基层间的电路排布,并且成本低廉、工艺简便。The present invention also provides the application of the chip as a chip for biological monitoring, preferably, the application of the chip as a chip of a nucleic acid sequencing device, and more preferably, the application of the chip as a chip of a nanopore sequencing device. Compared with the chip of silicon base material, the chip can realize the circuit arrangement among the multi-layer base layers, and has low cost and simple process.

附图说明Description of drawings

图1是本发明的芯片结构图。Fig. 1 is a chip structure diagram of the present invention.

图2是本发明的一种可选的芯片结构图。FIG. 2 is an optional chip structure diagram of the present invention.

图3是本发明的芯片应用在纳米孔基因测序装置的结构图。FIG. 3 is a structural diagram of the application of the chip of the present invention in a nanopore gene sequencing device.

图4是本发明的芯片应用在一种可选的纳米孔基因测序装置的结构图。FIG. 4 is a structural diagram of the chip of the present invention applied to an optional nanopore gene sequencing device.

图5是本发明的芯片上表面结构图。FIG. 5 is a structural view of the top surface of the chip of the present invention.

图6是本发明的一种可选的芯片结构图。FIG. 6 is an optional chip structure diagram of the present invention.

附图中,1-第一基层,2-第二基层,3-第一盲孔,4-金属线路,401-第一电极,402-电极,5-第一金属化过孔,501-第二金属化过孔,6-内层线路,7-第一触点,8-触点,9-第三基层,10-电解液腔室,11-磷脂层隔膜,12-第二盲孔。In the drawings, 1-first base layer, 2-second base layer, 3-first blind hole, 4-metal circuit, 401-first electrode, 402-electrode, 5-first metallized via, 501-th Two metallized vias, 6-inner layer circuit, 7-first contact, 8-contact, 9-third base layer, 10-electrolyte chamber, 11-phospholipid layer membrane, 12-second blind hole.

具体实施方式Detailed ways

下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

本发明提供了本发明提供了一种具有复合层的芯片,所述芯片包括至少上下设置的第一基层1和第二基层2,第一基层1上设置有至少一个通向第二基层2的第一盲孔3,所述芯片上还设置有至少一个穿过第二基层2的金属化过孔,第一盲孔3下面设置有电极402,所述芯片设置有触点8,电极402与触点8通过线路相连。The present invention provides a chip with a composite layer, the chip includes at least a first base layer 1 and a second base layer 2 disposed up and down, and at least one base layer leading to the second base layer 2 is disposed on the first base layer 1 The first blind hole 3, the chip is also provided with at least one metallized via hole passing through the second base layer 2, the electrode 402 is provided under the first blind hole 3, the chip is provided with a contact 8, and the electrode 402 is connected with the first blind hole 3. The contacts 8 are connected by wires.

以下实施例中所有金属线路为铜箔。All metal lines in the following examples are copper foils.

实施例1Example 1

本实施例的芯片结构如图1所示,第一基层1位于芯片上部,第一基层1为聚酰亚胺树脂板,第一基层1的厚度为0.1mm;第一基层1上设有孔电极,第一基层1的上表面设有第一盲孔3,第一盲孔3为圆形孔,孔径为0.1mm,第一盲孔3通过激光钻孔的技术形成,第一盲孔3的底部设有金属线路4,第一盲孔3和金属线路4构成孔电极;第一电极401设置在第一金属化过孔5上端的附近,电极402设置在第一基层1和第二基层2之间,并覆盖第一盲孔3的整个底面,电极402延伸到第二金属化过孔501;第二基层2位于第一基层1的下方,并且紧贴第一基层1,第二基层2为FR-4环氧树脂板材;第一金属化过孔5和第二金属化过孔501贯穿第一基层1和第二基层2,第一金属化过孔5和第二金属化过孔501的孔壁上设有内层线路6,内层线路6的多条金属线路延伸进入第一基层1和第二基层2,孔电极的金属线路4与第二金属化过孔501的内层线路6连接;第一触点7设置在第一金属化过孔5的顶部或底部的金属线路上,触点8设置在第二金属化过孔501的顶部或底部的金属线路上,第一电极401通过第一金属化过孔5的金属线路和内层线路6连接第一触点7,电极402通过第二金属化过孔501的金属线路和内层线路6连接触点8,实现互联,进而实现第一基层1和第二基层2的电路排布。The chip structure of this embodiment is shown in FIG. 1 , the first base layer 1 is located on the upper part of the chip, the first base layer 1 is a polyimide resin board, and the thickness of the first base layer 1 is 0.1 mm; the first base layer 1 is provided with holes Electrode, the upper surface of the first base layer 1 is provided with a first blind hole 3, the first blind hole 3 is a circular hole with a diameter of 0.1mm, the first blind hole 3 is formed by the technology of laser drilling, the first blind hole 3 There is a metal circuit 4 at the bottom of the metal circuit 4, the first blind hole 3 and the metal circuit 4 constitute a hole electrode; the first electrode 401 is arranged near the upper end of the first metallized via hole 5, and the electrode 402 is arranged on the first base layer 1 and the second base layer 2 and cover the entire bottom surface of the first blind hole 3, the electrode 402 extends to the second metallized via 501; the second base layer 2 is located under the first base layer 1, and is close to the first base layer 1, the second base layer 2 is an FR-4 epoxy resin sheet; the first metallized vias 5 and the second metallized vias 501 penetrate the first base layer 1 and the second base layer 2, and the first metallized vias 5 and the second metallized vias The inner layer circuit 6 is arranged on the hole wall of 501, the multiple metal circuits of the inner layer circuit 6 extend into the first base layer 1 and the second base layer 2, the metal circuit 4 of the hole electrode and the inner layer of the second metallized via hole 501 The line 6 is connected; the first contact 7 is arranged on the metal line on the top or bottom of the first metallized via 5, the contact 8 is arranged on the metal line on the top or bottom of the second metallized via 501, the first The electrode 401 is connected to the first contact 7 through the metal circuit of the first metallized via 5 and the inner layer circuit 6, and the electrode 402 is connected to the contact 8 through the metal circuit of the second metallized via 501 and the inner layer circuit 6 to realize interconnection , and further realize the circuit arrangement of the first base layer 1 and the second base layer 2 .

实施例2Example 2

本实施例的芯片结构如图2所示,第一基层1位于芯片上部,第一基层1为聚酰亚胺树脂板,第一基层1的厚度为0.1mm;第一基层1上设有孔电极,第一基层1的上表面设有第一盲孔3,第一盲孔3为圆形孔,孔径为0.1mm,第一盲孔3通过激光钻孔的技术形成,第一盲孔3的底部设有金属线路4,第一盲孔3和金属线路4构成孔电极;第一电极401设置在第一金属化过孔5上端的附近,电极402设置在第一基层1和第三基层9之间,并覆盖第一盲孔3的整个底面,电极402延伸到第二金属化过孔501;第三基层9位于第一基层1的下方,并且紧贴第一基层1,第二基层2位于第三基层9的下方,并且紧贴第三基层9,第二基层2和第三基层9均为FR-4环氧树脂板材;第一金属化过孔5和第二金属化过孔501贯穿第一基层1、第三基层9和第二基层2,第一金属化过孔5和第二金属化过孔501的孔壁上设有内层线路6,内层线路6的多条金属线路延伸进入第一基层1、第三基层9和第二基层2,孔电极的金属线路4与第二金属化过孔501的内层线路6连接;第一触点7设置在第一金属化过孔5的顶部或底部的金属线路上,触点8设置在第二金属化过孔501的顶部或底部的金属线路上,第一电极401通过第一金属化过孔5的金属线路和内层线路6连接第一触点7,电极402通过第二金属化过孔501的金属线路和内层线路6连接触点8,实现互联,进而实现第一基层1、第三基层9和第二基层2的电路排布。The chip structure of this embodiment is shown in FIG. 2 , the first base layer 1 is located on the upper part of the chip, the first base layer 1 is a polyimide resin board, and the thickness of the first base layer 1 is 0.1 mm; the first base layer 1 is provided with holes Electrode, the upper surface of the first base layer 1 is provided with a first blind hole 3, the first blind hole 3 is a circular hole with a diameter of 0.1mm, the first blind hole 3 is formed by the technology of laser drilling, the first blind hole 3 There is a metal circuit 4 at the bottom of the hole, the first blind hole 3 and the metal circuit 4 constitute a hole electrode; the first electrode 401 is arranged near the upper end of the first metallized via 5, and the electrode 402 is arranged on the first base layer 1 and the third base layer 9 and cover the entire bottom surface of the first blind hole 3, the electrode 402 extends to the second metallized via 501; the third base layer 9 is located under the first base layer 1, and is close to the first base layer 1, the second base layer 2 is located below the third base layer 9 and is close to the third base layer 9, the second base layer 2 and the third base layer 9 are both FR-4 epoxy resin sheets; the first metallized via 5 and the second metallized via 501 runs through the first base layer 1 , the third base layer 9 and the second base layer 2 , the inner layer circuit 6 is provided on the hole wall of the first metallized via hole 5 and the second metallized via hole 501 , and a plurality of inner layer circuits 6 are provided. The metal circuit extends into the first base layer 1, the third base layer 9 and the second base layer 2, the metal circuit 4 of the hole electrode is connected with the inner layer circuit 6 of the second metallized via 501; the first contact 7 is arranged on the first metal On the top or bottom metal line of the metallized via 5, the contact 8 is arranged on the top or bottom metal line of the second metallized via 501, and the first electrode 401 passes through the metal line of the first metallized via 5 and The inner layer circuit 6 is connected to the first contact 7, and the electrode 402 is connected to the contact 8 through the metal circuit of the second metallized via 501 and the inner layer circuit 6 to realize interconnection, thereby realizing the first base layer 1, the third base layer 9 and the first base layer 9. The circuit arrangement of the second base layer 2.

实施例3Example 3

芯片应用在纳米孔基因测序装置的结构如图3所示,第一基层1位于芯片上部,第一基层1为聚酰亚胺树脂板,第一基层1的厚度为0.1mm。芯片上部设有电解液腔室10,用于容纳含有DNA检测样品的电解液;第一基层1上设有孔电极,第一基层1的上表面设有第一盲孔3,第一盲孔3为圆形孔,孔径为0.1mm,第一盲孔3通过激光钻孔的技术形成,第一盲孔3的底部设有金属线路4,第一盲孔3和金属线路4构成孔电极。第一电极401设置在第一金属化过孔5上端的附近,电极402设置在第一基层1和第二基层2之间,并覆盖第一盲孔3的整个底面,电极402延伸到第二金属化过孔501。第二基层2位于第一基层1的下方,并且紧贴第一基层1,第二基层2为FR-4环氧树脂板材。第一金属化过孔5和第二金属化过孔501贯穿第一基层1和第二基层2,并且位于电解液腔室10外部,第一金属化过孔5和第二金属化过孔501的孔壁上设有内层线路6,内层线路6的多条金属线路延伸进入第一基层1和第二基层2,孔电极的金属线路4与第二金属化过孔501的内层线路6连接。第一触点7设置在第一金属化过孔5的顶部或底部的金属线路上,触点8设置在第二金属化过孔501的顶部或底部的金属线路上,第一电极401通过第一金属化过孔5的金属线路和内层线路6连接第一触点7,电极402通过第二金属化过孔501的金属线路和内层线路6连接触点8,实现互联,进而实现第一基层1和第二基层2的电路排布。The structure of the chip applied in the nanopore gene sequencing device is shown in FIG. 3 , the first base layer 1 is located on the upper part of the chip, the first base layer 1 is a polyimide resin board, and the thickness of the first base layer 1 is 0.1 mm. The upper part of the chip is provided with an electrolyte chamber 10 for accommodating the electrolyte containing the DNA detection sample; the first base layer 1 is provided with a hole electrode, and the upper surface of the first base layer 1 is provided with a first blind hole 3, the first blind hole 3 is a circular hole with a diameter of 0.1 mm. The first blind hole 3 is formed by laser drilling technology. The bottom of the first blind hole 3 is provided with a metal circuit 4, and the first blind hole 3 and the metal circuit 4 constitute a hole electrode. The first electrode 401 is arranged near the upper end of the first metallized via 5, the electrode 402 is arranged between the first base layer 1 and the second base layer 2, and covers the entire bottom surface of the first blind hole 3, and the electrode 402 extends to the second Metallized vias 501 . The second base layer 2 is located below the first base layer 1 and is close to the first base layer 1 , and the second base layer 2 is an FR-4 epoxy resin board. The first metallization via hole 5 and the second metallization via hole 501 penetrate through the first base layer 1 and the second base layer 2 and are located outside the electrolyte chamber 10 . The first metallization via hole 5 and the second metallization via hole 501 There is an inner layer circuit 6 on the wall of the hole, the multiple metal circuits of the inner layer circuit 6 extend into the first base layer 1 and the second base layer 2, the metal circuit 4 of the hole electrode and the inner layer circuit of the second metallized via 501 6 connections. The first contact 7 is arranged on the metal line on the top or bottom of the first metallized via 5, the contact 8 is arranged on the metal line on the top or bottom of the second metallized via 501, and the first electrode 401 passes through the The metal circuit of a metallized via 5 and the inner layer circuit 6 are connected to the first contact 7, and the electrode 402 is connected to the contact 8 through the metal circuit of the second metallized via 501 and the inner layer circuit 6 to realize interconnection, thereby realizing the first contact. Circuit arrangement of a base layer 1 and a second base layer 2.

电解液腔室10与第一盲孔3之间设有磷脂双分子层隔膜11,使电解液腔室10和第一盲孔3形成两个腔室,磷脂双分子层隔膜11上嵌有具有纳米孔结构的蛋白,当第一触点7和触点8接通电源,即第一电极401和电极402接通电源后,电解液腔室10中的DNA检测样品在电流作用下运动,并通过蛋白的纳米孔进入第一盲孔3,并记录DNA上不同碱基通过纳米孔时的电流变化,分析DNA序列。A phospholipid bilayer membrane 11 is arranged between the electrolyte chamber 10 and the first blind hole 3, so that the electrolyte chamber 10 and the first blind hole 3 form two chambers. For the protein with nanopore structure, when the first contact 7 and the contact 8 are powered on, that is, after the first electrode 401 and the electrode 402 are powered on, the DNA detection sample in the electrolyte chamber 10 moves under the action of the current, and Enter the first blind hole 3 through the nanopore of the protein, and record the current changes of different bases on the DNA when passing through the nanopore, and analyze the DNA sequence.

实施例4Example 4

芯片应用在一种可选的纳米孔基因测序装置的结构如图4所示,第一基层1位于芯片上部,第一基层1为聚酰亚胺树脂板,第一基层1的厚度为0.1mm。芯片上部设有电解液腔室10,用于容纳含有DNA检测样品的电解液;第一基层1上设有孔电极,第一基层1的上表面设有第一盲孔3,第一盲孔3为圆形孔,孔径为0.1mm,第一盲孔3通过激光钻孔的技术形成,第一盲孔3的底部设有金属线路4,第一盲孔3和金属线路4构成孔电极。第一电极401设置在电解液腔室10的上部并延伸到外部用于连接电源,电极402设置在第一基层1和第二基层2之间,并覆盖第一盲孔3的整个底面,电极402延伸到第二金属化过孔501。第二基层2位于第一基层1的下方,并且紧贴第一基层1,第二基层2为FR-4环氧树脂板材。第二金属化过孔501贯穿第一基层1和第二基层2,并且位于电解液腔室10外部,第二金属化过孔501的孔壁上设有内层线路6,内层线路6的多条金属线路延伸进入第一基层1和第二基层2,孔电极的金属线路4与第二金属化过孔501的内层线路6连接。第一触点7设置在第一电极401上,触点8设置在第二金属化过孔501的顶部或底部的金属线路上,电极402通过第二金属化过孔501的金属线路和内层线路6连接触点8,实现互联,进而实现第一基层1和第二基层2的电路排布。The structure of the chip applied to an optional nanopore gene sequencing device is shown in Figure 4. The first base layer 1 is located on the upper part of the chip, the first base layer 1 is a polyimide resin plate, and the thickness of the first base layer 1 is 0.1mm . The upper part of the chip is provided with an electrolyte chamber 10 for accommodating the electrolyte containing the DNA detection sample; the first base layer 1 is provided with a hole electrode, and the upper surface of the first base layer 1 is provided with a first blind hole 3, the first blind hole 3 is a circular hole with a diameter of 0.1 mm. The first blind hole 3 is formed by laser drilling technology. The bottom of the first blind hole 3 is provided with a metal circuit 4, and the first blind hole 3 and the metal circuit 4 constitute a hole electrode. The first electrode 401 is arranged on the upper part of the electrolyte chamber 10 and extends to the outside for connecting the power supply. The electrode 402 is arranged between the first base layer 1 and the second base layer 2 and covers the entire bottom surface of the first blind hole 3. The electrode 402 extends to the second metallized via 501 . The second base layer 2 is located below the first base layer 1 and is close to the first base layer 1 , and the second base layer 2 is an FR-4 epoxy resin board. The second metallized via hole 501 penetrates through the first base layer 1 and the second base layer 2 and is located outside the electrolyte chamber 10 . The inner layer circuit 6 is provided on the hole wall of the second metallized via hole 501 . A plurality of metal lines extend into the first base layer 1 and the second base layer 2 , and the metal lines 4 of the hole electrodes are connected to the inner layer lines 6 of the second metallized vias 501 . The first contact 7 is arranged on the first electrode 401, the contact 8 is arranged on the metal line on the top or bottom of the second metallized via 501, and the electrode 402 passes through the metal line and the inner layer of the second metallized via 501 The lines 6 are connected to the contacts 8 to realize interconnection, thereby realizing the circuit arrangement of the first base layer 1 and the second base layer 2 .

电解液腔室10与第一盲孔3之间设有磷脂双分子层隔膜11,使电解液腔室10和第一盲孔3形成两个腔室,磷脂双分子层隔膜11上嵌有具有纳米孔结构的蛋白,当第一触点7和触点8接通电源,即第一电极401和电极402接通电源后,电解液腔室10中的DNA检测样品在电流作用下运动,并通过蛋白的纳米孔进入第一盲孔3,并记录DNA上不同碱基通过纳米孔时的电流变化,分析DNA序列。A phospholipid bilayer membrane 11 is arranged between the electrolyte chamber 10 and the first blind hole 3, so that the electrolyte chamber 10 and the first blind hole 3 form two chambers. For the protein with nanopore structure, when the first contact 7 and the contact 8 are powered on, that is, after the first electrode 401 and the electrode 402 are powered on, the DNA detection sample in the electrolyte chamber 10 moves under the action of the current, and Enter the first blind hole 3 through the nanopore of the protein, and record the current changes of different bases on the DNA when passing through the nanopore, and analyze the DNA sequence.

实施例5Example 5

芯片上表面结构如图5所示,第一触点7位于第一金属化过孔5在第一基层1上表面的延伸金属线路,第一电极401通过金属化过孔5在第一基层1上表面的环形金属线路连接第一触点7,电极402位于第一盲孔3的底部,电极402通过第二金属化过孔501的内壁和第一基层1上表面的环形金属线路连接触点8。The top surface structure of the chip is shown in FIG. 5 , the first contact 7 is located on the extended metal line of the first metallized via 5 on the upper surface of the first base layer 1 , and the first electrode 401 is located on the first base layer 1 through the metallized via 5 The ring-shaped metal circuit on the upper surface is connected to the first contact 7, the electrode 402 is located at the bottom of the first blind hole 3, and the electrode 402 is connected to the contact through the inner wall of the second metallized via 501 and the ring-shaped metal circuit on the upper surface of the first base layer 1 8.

实施例6Example 6

本实施例的芯片结构如图6所示,第一基层1上设有一个通向第二基层2的第二盲孔12,第二盲孔12下面设置有第一电极401,第一电极401通过延伸金属线路4与第一金属化过孔5联通,第一触点7设在第一金属化过孔5在第二基层2下表面的延伸金属线路上;第一金属化过孔5和第二金属化过孔501贯穿第二基层2,但不贯穿第一基层1;第一金属化过孔5和第二金属化过孔501在第二基层2中设有内层线路6,内层线路6围绕第一金属化过孔5和第二金属化过孔501的孔壁展开。触点8位于第二金属化过孔501在第二基层2下表面的延伸金属线路上。电极402设在第一盲孔3的底部,并通过延伸金属线路4连接第二金属化过孔501,由此间接连接内层线路6和第二基层2下表面的环形金属线路,进而连接触点8。The chip structure of this embodiment is shown in FIG. 6 , the first base layer 1 is provided with a second blind hole 12 leading to the second base layer 2 , and a first electrode 401 is provided under the second blind hole 12 . The first electrode 401 The extended metal line 4 communicates with the first metallized via hole 5, and the first contact 7 is provided on the extended metal line of the first metallized via hole 5 on the lower surface of the second base layer 2; the first metallized via hole 5 and The second metallized via hole 501 penetrates through the second base layer 2, but does not penetrate the first base layer 1; the first metallized via hole 5 and the second metallized via hole 501 are provided with inner layer lines 6 in the second base layer 2, The layer wiring 6 spreads around the hole walls of the first metallized via 5 and the second metallized via 501 . The contact 8 is located on the extended metal line of the second metallized via 501 on the lower surface of the second base layer 2 . The electrode 402 is arranged at the bottom of the first blind hole 3, and is connected to the second metallized via 501 by extending the metal circuit 4, thereby indirectly connecting the inner layer circuit 6 and the annular metal circuit on the lower surface of the second base layer 2, and then connecting the contact. Point 8.

使用时,第一触点7和触点8连接电源,即可在第一电极401和电极402之间形成电压,第一盲孔3和第二盲孔12上方连通导电介质。When in use, the first contact 7 and the contact 8 are connected to a power supply, so that a voltage can be formed between the first electrode 401 and the electrode 402 , and a conductive medium is connected above the first blind hole 3 and the second blind hole 12 .

Claims (13)

1.一种具有复合层的芯片及其在生物检测中的应用,其特征在于,所述芯片包括至少上下设置的第一基层和第二基层,所述的第一基层上设置有至少一个通向第二基层的第一盲孔,所述的芯片上还设置有至少一个穿过第二基层的金属化过孔,所述的第一盲孔下面设置有电极,所述的芯片设置有触点,所述的电极与触点通过线路相连。1. a chip with a composite layer and its application in biological detection, wherein the chip comprises at least a first base layer and a second base layer arranged up and down, and the first base layer is provided with at least one pass through. To the first blind hole of the second base layer, the chip is also provided with at least one metallized via hole passing through the second base layer, an electrode is provided under the first blind hole, and the chip is provided with a contact hole. point, the electrodes are connected with the contacts through lines. 2.根据权利要求1所述的芯片,其特征在于,所述的第一基层上、下表面或第一基层上方还设有第一电极,所述的芯片还设有第一触点,所述的第一电极与第一触点通过线路相连。2 . The chip according to claim 1 , wherein a first electrode is further provided on the upper and lower surfaces of the first base layer or above the first base layer, and the chip is further provided with a first contact, so 2 . The first electrode is connected with the first contact through a line. 3.根据权利要求2所述的芯片,其特征在于,所述的第一基层上还设置有至少一个通向第二基层的第二盲孔,所述的第二盲孔下面设置有第一电极。3. The chip according to claim 2, wherein the first base layer is further provided with at least one second blind hole leading to the second base layer, and the second blind hole is provided with a first electrode. 4.根据权利要求3所述的芯片,其特征在于,所述芯片上设置至少两个贯穿第二基层的金属化过孔,所述金属化过孔的外壁设有内层线路。4 . The chip according to claim 3 , wherein at least two metallized vias penetrating through the second base layer are provided on the chip, and inner-layer lines are provided on the outer walls of the metallized vias. 5 . 5.根据权利要求3和4所述的芯片,其特征在于,所述第一电极通过金属线路联通第一金属化过孔,电极通过金属线路联通第二金属化过孔。5 . The chip according to claim 3 and 4 , wherein the first electrode communicates with the first metallized via via a metal line, and the electrode communicates with the second metallized via via a metal line. 6 . 6.根据权利要求5所述的芯片,其特征在于,所述第一金属化过孔的内层线路或第一金属化过孔在第二基层下表面的延伸金属线路上设有第一触点;所述第二金属化过孔的内层线路或第二金属化过孔在第二基层下表面的延伸金属线路上设有触点。6 . The chip according to claim 5 , wherein the inner layer line of the first metallized via or the first metallization via is provided with a first contact on the extended metal line on the lower surface of the second base layer. 7 . point; the inner layer line of the second metallized via hole or the second metallized via hole is provided with a contact on the extended metal line on the lower surface of the second base layer. 7.根据权利要求1和2所述的芯片,其特征在于,所述金属化过孔贯穿第一基层和第二基层,所述第一触点位于第一金属化过孔在第一基层上表面或第二基层下表面的延伸金属线路,所述第一电极设置在所述第一金属化过孔上端边缘,所述第一电极通过第一金属化过孔在第一基层上表面或第二基层下表面的环形金属线路以及内层线路连接所述第一触点。7 . The chip according to claim 1 and 2 , wherein the metallized via penetrates the first base layer and the second base layer, and the first contact is located on the first metallized via on the first base layer. 8 . The extended metal line on the surface or the lower surface of the second base layer, the first electrode is arranged on the upper edge of the first metallized via hole, and the first electrode is on the upper surface or the first base layer through the first metallized via hole. The annular metal circuit on the lower surface of the two base layers and the inner layer circuit are connected to the first contact. 8.根据权利要求1所述的芯片,其特征在于,所述触点位于第二金属化过孔在第一基层上表面或第二基层下表面的延伸金属线路;所述电极能够通过第二金属化过孔在第一基层上表面或第二基层下表面的环形金属线路以及内层线路连接所述触点。8 . The chip according to claim 1 , wherein the contact is located on the extended metal line of the second metallized via on the upper surface of the first base layer or the lower surface of the second base layer; the electrode can pass through the second base layer. 9 . The metallized vias are connected to the contacts by a ring-shaped metal circuit on the upper surface of the first base layer or the lower surface of the second base layer and the inner layer circuit. 9.根据权利要求1所述的芯片,其特征在于,所述的第二基层中设置有内层线路。9 . The chip of claim 1 , wherein the second base layer is provided with inner layer lines. 10 . 10.根据权利要求1所述的芯片,其特征在于,所述的第一基层和第二基层之间还设置有至少一个第三基层。10. The chip according to claim 1, wherein at least one third base layer is further disposed between the first base layer and the second base layer. 11.根据权利要求1所述的芯片,其特征在于,所述的第一基层和第二基层材料为塑料,优选的,所述第一基层和第二基层的材料为聚酰亚胺树脂板、FR-4板材、FR-1板材或CEM-1/3板材。11. The chip according to claim 1, wherein the materials of the first base layer and the second base layer are plastics, and preferably, the materials of the first base layer and the second base layer are polyimide resin plates , FR-4 sheet, FR-1 sheet or CEM-1/3 sheet. 12.根据权利要求1和3所述的芯片,其特征在于,所述第一盲孔的孔径为0.1-0.15mm,所述第二盲孔的孔径为1-1.5mm。12 . The chip according to claim 1 , wherein the diameter of the first blind hole is 0.1-0.15 mm, and the diameter of the second blind hole is 1-1.5 mm. 13 . 13.根据权利要求1所述的芯片在生物检测中的应用,优选的,所述芯片在核酸测序中的应用,更优选的,所述芯片在纳米孔核酸测序中的应用。13. The application of the chip according to claim 1 in biological detection, preferably, the application of the chip in nucleic acid sequencing, more preferably, the application of the chip in nanopore nucleic acid sequencing.
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