CN111835600B - Multimode ultra-high speed digital subscriber line transceiver device and method of implementing the same - Google Patents
Multimode ultra-high speed digital subscriber line transceiver device and method of implementing the same Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/2854—Wide area networks, e.g. public data networks
- H04L12/2856—Access arrangements, e.g. Internet access
- H04L12/2869—Operational details of access network equipments
- H04L12/2898—Subscriber equipments
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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Abstract
The invention provides a multimode ultra-high speed digital subscriber line transceiver device, which comprises a transmitting device, a receiving device and an analog front end hybrid circuit. The transmitting apparatus includes a modulator, an inverse fast Fourier transformer, a transmitting filter, a up-sampler, and a digital-to-analog converter, which are connected in series in order. The receiving apparatus includes an analog-to-digital converter, a down-sampler, a receiving filter, a fast Fourier transformer, and a frequency equalizer, which are connected in series. The analog front end mixed circuit is connected between the digital-to-analog converter of the sending device and the analog-to-digital converter of the receiving device and is further connected to an external circuit.
Description
Technical Field
The present invention relates to the field of cable communication technologies, and in particular, to a multimode Very-high-bit-rate Digital Subscriber Line (VDSL) transceiver device and an execution method thereof.
Background
The proliferation of the internet has caused a greater demand for high rate data transmission. Given that copper twisted pairs have long been ubiquitous in telephone networks, many data communication protocols may have to be designed to be suitable for transmitting data over standard analog plain old telephone systems.
However, since the highest transmission rate of modem is only 56.6 kbits/sec, the industry is continuously researching new technology for providing higher data access via copper twisted pair cable, and finally promoting the emergence of Digital Subscriber Line (DSL).
DSL includes Asymmetric Digital Subscriber Line (ADSL), Discrete Multi-Tone (DMT) Very high-speed Digital Subscriber Line (VDSL), or VDSL2, among others. DSL reserves a frequency band in the range of 0.3kHz to 4kHz for Plain Old Telephone Service (POTS), and uses an available frequency band above this range for data transmission.
The available frequency band can be divided into tones (tones) of about 4KHz in width. Line coding may be introduced to encode digital signals into analog signals for transmitting data over an analog telephone network, subject to limitations on the width of 4KHz and the power of the telephone network. Line coding aims at controlling three properties of the analog carrier signal: amplitude, phase, and frequency. Various Modulation techniques, such as Quadrature Amplitude Modulation (QAM), are known to control the phase and Amplitude of a carrier signal in order to accommodate more data in a frequency band.
For example, in a QAM system, each symbol may carry two bits of data. The transmitted signal set may be represented by a Constellation diagram (Constellation), where a Constellation point of the Constellation diagram represents a signal of the transmitted signal set, and the position of the Constellation point in the Constellation diagram represents the amplitude and phase of the signal. Increasing the size of the constellation, i.e., the number of constellation points, increases the bit density of each symbol, thereby achieving higher data rates.
In the known art, the Central Office (Central Office) uses various DSLs to communicate with various subscriber locations. Each DSL supports only a corresponding communication channel, requiring different sampling rates and bandwidths, respectively. In this case, each DSL requires its own transceiver device, that is, for a DSL, one transceiver device dedicated to the DSL must be provided, which results in a complicated architecture and increased cost.
There is therefore a real need to provide innovative devices and methods for implementing them in order to integrate various DSLs.
Disclosure of Invention
The present invention is directed to an innovative digital circuit in which the sampling rate of a digital-to-analog converter (DAC) and/or analog-to-digital converter (ADC) is fixed and still supports multiple DSL standards, including but not limited to: ADSL2, ADSL2+, 35b, 17a, 12a or 8a of VDSL2, and the like. These standards require different sampling rates and bandwidths, respectively.
In one aspect, the digital circuit provided by the present invention includes a multiplier variable up-sampler and/or down-sampler configured to flexibly adjust the frequency of the signal as seen by the analog and digital transceiver circuits when the signal is in a sampled and quantized state. After the sampling rate is adjusted, the bandwidth is also adjusted equivalently.
The present invention can use only one set of ADC/DACs with a fixed sampling rate, and does not require multiple sets of ADC/DACs with different sampling rates to accommodate different DSL modes. Alternatively, or preferably, the ADC and DAC may have the same sampling rate.
In accordance with this aspect, the present invention provides a multimode, ultra-high speed digital subscriber line transceiver apparatus comprising a transmitting device, a receiving device, and an analog front end hybrid circuit. The transmitting apparatus includes a modulator, an inverse fast Fourier transformer, a transmitting filter, a up-sampler, and a digital-to-analog converter, which are connected in series in order. The receiving device includes an analog-to-digital converter, a down-sampler, a receiving filter, a fast Fourier transformer, and a frequency equalizer, which are connected in series in sequence. The analog front end mixed circuit is connected between the digital-to-analog converter of the sending device and the analog-to-digital converter of the receiving device and is further connected to an external circuit.
Alternatively, or preferably, the external line is a twisted pair.
Alternatively, or preferably, the digital-to-analog converter has a fixed sampling rate.
Furthermore, the analog-to-digital converter has another fixed sampling rate accordingly.
Alternatively, or preferably, the up-sampler comprises one or more stages of up-sampling circuits, each stage of up-sampling circuits comprising an interpolator and an up-sampling low-pass filter, the interpolator being configured to adjust a sampling rate by a multiplier, and the sampling rate of each stage of up-sampling circuits being independently adjustable by a respective multiplier of a respective interpolator.
Alternatively, or preferably, the up-sampler comprises one or more stages of up-sampling circuits, and each stage of up-sampling circuits may comprise an interpolator, an integral-differential modulation module, and a dynamic element matching module, which are connected in series in sequence.
Alternatively, or preferably, the down-sampler comprises one or more stages of down-sampling circuits, each stage of down-sampling circuits comprising a decimator and a down-sampling low-pass filter, the decimator being configured to adjust the further sampling rate by a respective further multiplier, and the sampling rate of each stage of down-sampling circuits being independently adjustable by a respective multiplier of a respective decimator.
Optionally, or preferably, the Analog front end hybrid circuit includes an Analog Echo Canceller (Analog Echo Canceller) configured to switch with Different (DSL) modes. Therefore, the efficiency of signal receiving and transmitting can be optimized.
More broadly, the present invention provides a multimode, ultra-high speed digital subscriber line transceiver apparatus, comprising a transmitting device, a receiving device, and an analog front end including a hybrid circuit. The transmitting device comprises a modulator, an inverse fast Fourier transformer, a transmitting filter and a digital-to-analog converter which are connected in series; a transmit digital channel is defined between the inverse fast Fourier transformer and the digital-to-analog converter, and a up-sampler is provided on the transmit digital channel. The receiving device comprises an analog-to-digital converter, a receiving filter, a fast Fourier transformer and a frequency equalizer which are connected in series in sequence; a receiving digital channel is defined between the analog-to-digital converter and the fast Fourier transformer, and a down-sampler is provided on the receiving digital channel. The analog front end mixed circuit is connected between the digital-to-analog converter of the sending device and the analog-to-digital converter of the receiving device and is further connected to an external circuit.
In another aspect, the present invention may use only one set of ADC/DACs with a fixed sampling rate, rather than multiple sets of ADC/DACs with different sampling rates, to accommodate different DSL modes. Alternatively, or preferably, the ADC and DAC may have the same sampling rate. The invention switches the inverse fast fourier transformer/fast fourier transformer Size Flag (Size Flag) to a Size of 16384, 8192, or other sizes to select the up/down sampling rate of each of the up-sampler and/or down-sampler, based on the DSL mode determined in the handshake phase, after the handshake phase according to the ITU-t g.994.1(Ghs) standard. Therefore, the same set of fundamental frequency fixed line (Baseband Hardwired) equipment can conveniently support multiple DSL modes.
According to another aspect, the present invention provides a method for executing a multimode ultra-high speed digital subscriber line transceiver device, comprising steps S1 to S3. Step S1 is a handshake procedure performed by a multimode ultra-high speed digital subscriber line transceiver device to exchange initial data; the multimode ultra-high speed digital subscriber line transceiver device uses a predetermined sampling rate and a predetermined bandwidth. Step S2 is to determine a dsl mode, a corresponding agreed sampling rate and an agreed bandwidth of the multimode dsl transceiver device based on the initial data obtained from the handshake procedure, and declare the end of the handshake procedure. Step S3 is to set at least one up-sampling parameter of an up-sampling circuit and/or a down-sampling parameter of a down-sampling circuit of the multimode ultra-high speed digital subscriber line transceiver device according to the negotiated sampling rate and negotiated bandwidth.
Alternatively, or preferably, the executing step may further include step S4: the performance of an analog echo canceller of a multimode ultra-high speed digital subscriber line transceiver apparatus is maximized.
In summary, the multimode ultra-high speed digital subscriber line transceiver device and the implementation method thereof of the present invention can simplify the analog circuit and further reduce the occupied area on the premise of supporting various DSL standards. Furthermore, the complexity of the chip and the circuit board can be reduced, and the qualification rate of the product is also improved. In any case, the quality of signal transmission and reception is not affected thereby.
In addition, the architecture of the multimode xDSL transceiver device and the implementation method thereof of the present invention is clear and can be implemented accordingly.
Drawings
Figure 1 shows a multimode very high speed digital subscriber line transceiver device according to a first embodiment of the present invention.
Fig. 2 shows an up-sampling circuit according to an embodiment of the present invention.
Figure 3 shows a multimode ultra high speed digital subscriber line transceiver apparatus of the present invention communicating with a counterpart transceiver apparatus of a different DSL mode.
Figure 4 shows a second embodiment of the multimode very high speed digital subscriber line transceiver apparatus of the present invention.
Figure 5 shows a third embodiment of the multimode very high speed digital subscriber line transceiver device of the present invention.
Figure 6 shows a fourth embodiment of the multimode very high speed digital subscriber line transceiver device of the present invention.
Figure 7 shows a method of implementing a multimode very high speed digital subscriber line transceiver device according to a fifth embodiment of the present invention.
[ notation ] to show
1 multimode ultra-high speed digital subscriber line transceiver device
10 transmitting device
11 modulator
12 Inverse Fast Fourier Transformer (IFFT)
13 transmitting filter
14 liter sampler
140 liter sampling circuit
141 interpolator
142 up-sampling Low Pass Filter (LPF)
1421 integral-differential modulation (SDM) module
1422 Dynamic Element Matching (DEM) module
15 digital-to-analog converter (DAC)
20 receiver
21 analog-to-digital converter (ADC)
22-step down sampler
220 down-sampling circuit
221 extractor
222 down-sampling low-pass filter
23 receiving filter
24 Fast Fourier Transformer (FFT)
25 Frequency Equalizer (FEQ)
30 analog front end with hybrid circuit
31 analog echo canceller
40 external line
5 counterpart transceiver device
L14 send digital channel
L22 receive digital channel
S1 step S1
S2 step S2
S3 step S3
S4 step S4
Detailed Description
Various embodiments of the invention are provided below. These examples are intended to illustrate the technical contents of the present invention, and are not intended to limit the scope of the claims of the present invention. Features of the invention may be modified, replaced, combined, separated, or designed to be applied to other embodiments.
(first embodiment)
Figure 1 shows a multimode ultra high speed digital subscriber line transceiver device 1 according to a first embodiment of the present invention.
The multimode ultra-high speed digital subscriber line transceiver apparatus 1 of the present invention comprises a transmitting device 10, a receiving device 20, and an Analog Front End (AFE) Hybrid (Hybrid) circuit 30. The analog front end mixer 30 is connected between the transmitter 10 and the receiver 20, which is further connected to an external Line 40, such as a Twisted Pair Line (Twisted Pair Line).
The transmitter 10 includes a Modulator (Modulator)11, an Inverse Fast Fourier Transformer (IFFT) 12, a transmit Filter (TX Filter)13, an Up-Sampler (Up-Sampler)14, and a Digital-to-Analog converter (DAC) 15.
The input of the modulator 11 is intended to receive a digital signal to be transmitted, which is for example a bit string. The output of the modulator 11 is connected to the input of the inverse fast fourier transformer 12. The output of the inverse fast fourier transformer 12 is connected to the input of a transmit filter 13. The output of the transmit filter 13 is connected to the input of the up-sampler 14. The output of the up-sampler 14 is connected to the input of a digital-to-analog converter 15. The output of the digital-to-analog converter 15 is connected to an analog front end mixer 30.
The receiving apparatus 20 includes an Analog-to-Digital converter (ADC) 21, a Down-Sampler (Down-Sampler)22, a receiving Filter (RX Filter)23, a Fast Fourier Transformer (FFT) 24, and a Frequency Equalizer (FEQ) 25.
The input of the analog-to-digital converter 21 is connected to the analog front end mixer 30. The output of the analog-to-digital converter 21 is connected to the input of the down-sampler 22. The output of the down-sampler 22 is connected to the input of a receive filter 23. The output of the receive filter 23 is connected to the input of a fast fourier transformer 24. The output of the fast fourier transformer 24 is connected to the input of a frequency equalizer 25. The output of the frequency equalizer 25 is used to transmit a received digital signal.
The transmission device 10 operates as follows: a digital signal to be transmitted is input to the modulator 11. The modulator 11 includes one or more Modulation functions (Modulation functions), also called Mapping functions (Mapping functions), including but not limited to: quadrature Amplitude Modulation (QAM), Phase Shift Keying (PSK), Amplitude Shift Keying (ASK), Binary Phase Shift Keying (BPSK), or Frequency Shift Keying (FSK) to modulate a digital signal to be transmitted into a Frequency domain symbol to be transmitted.
Then, the frequency domain symbol to be transmitted is input to the inverse fast fourier transformer 12 for inverse fast fourier transform to become a time domain symbol to be transmitted. At this point, the time domain symbols to be transmitted are in a sampled and quantized state.
The transmit filter 13 may further Shape-filter (Shape Filtering) the time-domain symbols to be transmitted.
The up-sampler 14 may include one or more stages of up-sampling circuits 140 (only one stage is shown in fig. 1), and each stage of up-sampling circuits 140 includes an Interpolator (Interpolator)141 and a Low-Pass Filter (LPF) 142.
Fig. 2 shows an up-sampling circuit 140 according to an embodiment of the present invention.
In one embodiment, the up-sampling circuit 140 may include an interpolator 141, a Sigma Delta Modulation (SDM) module 1421, and a Dynamic Element Matching (DEM) module 1422, which are connected in series.
The interpolator 141 converts an un-interpolated digital signal with a sampling rate Fs received by it into an interpolated digital signal with an oversampling rate Fos, which is higher than the sampling rate Fs, by difference method, and the ratio of the oversampling rate Fos to the sampling rate Fs is a multiplier. The interpolated digital signals do not have aliasing.
The SDM module 1421 converts the interpolated digital signal to an SDM digital signal by Noise Shaping (Noise Shaping).
The DEM module 1422 generates a DEM signal by digitally processing to shift noise generated due to mismatch between analog elements to a range outside the passband of the SDM digital signal. This improves the Signal-to-Noise Ratio (Signal-to-Noise Ratio) of the passband. The DEM module 1422 may use a general DEM type, and the structure and principle thereof are not described herein.
Returning to fig. 1, the signal (e.g., DEM signal) generated by the time domain symbol to be transmitted through the transmit filter 13 and the up-sampler 14 is input to the dac 15 and converted into an analog signal to be transmitted. In one embodiment, the digital-to-analog converter 15 may include a plurality of capacitors, a corresponding plurality of switches, and an amplifier, each capacitor and each switch being connected in series as a group, and each group being connected in parallel to the amplifier. The structure and parts of the digital-to-analog converter 15 are not shown here.
In particular, in the present invention, the DAC 15 has a fixed sampling rate, such as 70.656MHz or 35.328 MHz.
The analog signal to be transmitted enters the analog front end mixer 30 for additional (analog) signal processing and is finally transmitted to a counterpart transceiver device 5 via the external line 40.
Fig. 3 shows a multimode ultra high speed digital subscriber line transceiver apparatus 1 of the present invention communicating with a counterpart transceiver apparatus 5 of a different DSL mode.
Returning to fig. 1, the operation of the receiving device 20 is substantially the same as or complementary to the operation of the transmitting device 10. The operation of the receiving device 20 is as follows: a received analog signal arriving from a pair of transceiver devices 5 via external lines 40 enters the analog front end mixer 30 for additional (analog) signal processing and is input to the analog-to-digital converter 21 for conversion into a to-be-processed digital signal. At this point, the digital signal to be processed is in a sampled and quantized state.
In particular, in the present invention, the analog-to-digital converter 21 has another fixed sampling rate, such as 70.656MHz, or 141.312 MHz.
Down-sampler 22 may include one or more stages of down-sampling circuits 220 (only one stage is shown in fig. 1), and each stage of down-sampling circuit 220 includes a Decimator (Decimator)221 and a down-sampling Low Pass Filter (LPF) 222.
The decimator 221 is configured to adjust another sampling rate by another multiplier, respectively. Furthermore, the sampling rate of each down-sampling circuit 220 can be independently adjusted by respective multipliers of the respective decimators 221, for example, by quarter, by half, … …, by two, by four, … …, and the like. However, the other multiplier of the decimator 211 and the multiplier of the interpolator 141 may be reciprocal or complementary to each other. The decimator 221 may be designed opposite or complementary to the principles of the interpolator 141.
The coefficients of the down-sampling low-pass filter 121 are determined according to the multipliers of the decimator 221. In one embodiment, the down-sampling low-pass Filter 121 may be an Anti-Aliasing Filter (Anti-Aliasing Filter).
The receive filter 23 may further shape and filter the time domain symbols.
The signal generated by the digital signal to be processed through the down-sampler 22 and the receiving filter 23, i.e. a received time-domain symbol, is input to the fast fourier transformer 24 for fast fourier transformation into a received frequency-domain symbol.
The received frequency domain symbols are input to a frequency equalizer 25. The frequency equalizer 25 is configured to have a vector FEQ function for obtaining an estimate of a complex value of a digital signal of a counterpart to be transmitted by the counterpart transceiver device as a received digital signal. The suitable vector FEQ function may be designed by a Least Mean method (Least Mean Squared Approach) or a Maximum Likelihood method (Maximum-likehood Approach), but is not limited thereto. The vector FEQ function may be obtained by training or periodic operations.
The analog front end mixer 30 is composed of a pure analog circuit and a digital-analog mixer. In addition, the Analog front end mixer 30 may include an Analog Echo Canceller (Analog Echo Canceller)31 configured to switch with different DSL modes to optimize signal transceiving performance.
(second embodiment)
Figure 4 shows a multimode very high speed digital subscriber line transceiver device 1 according to a second embodiment of the present invention.
The present embodiment is modified based on the first embodiment, so that the structure, details, functions and functions of the elements having the same reference numerals can be understood by referring to the first embodiment.
The difference of the present embodiment is: in the transmitting apparatus 10, the up-sampler 14 is connected between the inverse fast fourier transformer 12 and the transmission filter 13 instead. Accordingly, in the receiving apparatus 20, the down-sampler 22 is instead connected between the receiving filter 23 and the fast fourier transformer 24. The remaining components may need to be adjusted in response to the changes, such as adjusting the operating frequency.
(third embodiment)
Figure 5 shows a third embodiment of the multimode very high speed digital subscriber line transceiver device 1 of the present invention.
The present embodiment is modified based on the first embodiment, so that the structure, details, functions and functions of the elements having the same reference numerals can be understood by referring to the first embodiment.
The difference of the present embodiment is: in the transmitting apparatus 10, the up-sampler 14 is connected between the inverse fast fourier transformer 12 and the transmission filter 13 instead. However, in the receiving apparatus 20, the down-sampler 22 is still connected between the analog-to-digital converter 21 and the receiving filter 23. Even if the up-sampler 14 and the down-sampler 22 have no symmetry in configuration, the structure and details of the respective elements can be adjusted by mathematical calculation to achieve the function and function equivalent to those of the first embodiment. Therefore, the mathematical calculations required for the adjustment are performed depending on the actual circuit configuration.
(fourth embodiment)
Fig. 6 shows a fourth embodiment of the multimode very high speed digital subscriber line transceiver apparatus 1 of the present invention.
The present embodiment is modified based on the first embodiment, so that the structure, details, functions and functions of the elements having the same reference numerals can be understood by referring to the first embodiment.
The difference of the present embodiment is: in the transmitting apparatus 10, the up-sampler 14 is still connected between the transmit filter 13 and the digital-to-analog converter 15. However, in the receiving apparatus 20, the down-sampler 22 is instead connected between the receiving filter 23 and the fast fourier transformer 24. Even if the up-sampler 14 and the down-sampler 22 do not have symmetry in configuration, the structure and details of the respective elements can be adjusted by mathematical calculation to achieve the function and function equivalent to those of the first embodiment. Therefore, the mathematical calculations required for the adjustment are performed depending on the actual circuit configuration.
In summary of the first to fourth embodiments, a transmission digital channel L14 may be defined between the ifft 12 and the dac 15 of the transmission apparatus 10, and the up-sampler 14 may be provided in series with other blocks (e.g., the transmission filter 13) on the transmission digital channel L14. Similarly, a receiving digital channel L14 may be defined between the analog-to-digital converter 21 and the fast fourier transformer 24 of the receiving apparatus 20, and the down-sampler 22 may be disposed on the receiving digital channel L22 in a serial manner with other modules (e.g., the receiving filter 23).
(fifth embodiment)
Fig. 7 shows a method of implementing a multimode very high speed digital subscriber line transceiver device 1 according to a fifth embodiment of the present invention.
This embodiment is intended to explain the method of executing the multimode very high speed digital subscriber line transceiver device 1 of the present invention, and is applicable to various multimode very high speed digital subscriber line transceiver devices 1 of the first to fourth embodiments, without being limited thereto. The execution method of the invention comprises a plurality of steps which are respectively as follows:
step S1 is the initial phase of connection, in which the multimode ultra-high speed digital subscriber line transceiver device 1 of the present invention and the counterpart transceiver device 5 perform a handshake procedure to exchange initial data. The handshaking procedure is, for example, performed according to the ITU-T g.994.1(Ghs) standard. In this stage, the multimode very high speed digital subscriber line transceiver apparatus 1 uses a predetermined sampling rate and a predetermined bandwidth.
Step S2 is to determine a DSL mode, a corresponding agreed sampling rate and an agreed bandwidth of the multimode very high speed DSL transceiver device 1 based on the initial data obtained from the handshake procedure, and declare the end of the handshake procedure.
Step S3 is to set at least one up-sampling parameter of an up-sampling circuit 14 and/or a down-sampling parameter of a down-sampling circuit 22 of the multimode very high speed digital subscriber line transceiver apparatus 1 according to the negotiated sampling rate and negotiated bandwidth.
In particular, in step S3, the inverse fast fourier transformer/fast fourier transformer Size Flag (Size Flag) may be switched, for example, 16384, 8192, or other Size, to select the up/down sampling rate of each of the up-sampler and/or the down-sampler.
Further, optionally, or preferably, step S4 may be performed, which is to maximize the performance of an analog echo canceller of the multimode very high speed digital subscriber line transceiver device. Therefore, the quality of signal receiving and transmitting can be ensured.
As can be seen from the above steps, the up-sampling parameter or the down-sampling parameter set by the multimode very high speed digital subscriber line transceiver device 1 of the present invention does not need to be transmitted to the counterpart transceiver device 5, and thus does not have any influence on the counterpart transceiver device 5.
The multimode ultra-high speed digital subscriber line transceiver device 1 of the present invention can communicate with a counterpart transceiver device 5 even if it has only a limited, even a single DSL mode.
In summary, the multimode ultra-high speed digital subscriber line transceiver apparatus 1 and the implementation method thereof of the present invention can simplify the analog circuit and further reduce the occupied area thereof on the premise of supporting various DSL standards. Furthermore, the complexity of the chip and even the circuit board can be reduced, and the qualified rate of the product can be improved. In any case, the quality of signal transmission and reception is not affected thereby.
In addition, the architecture of the multimode very high speed digital subscriber line transceiver apparatus 1 and the implementation method thereof of the present invention is clear and can be realized accordingly.
It will be appreciated that the modules of the invention described above may be implemented in any desired and suitable manner. For example, they may be implemented in hardware or software. The various functional elements, layers and instrumentalities of the present invention may include, but are not limited to, a suitable processor, a controller, a functional unit, a circuit, a program logic, a microprocessor, etc., for operating to perform the desired functions, unless otherwise specified. There may be a dedicated hardware component and/or programmable hardware component that may be configured to operate in a desired and appropriate manner. Unless specifically stated otherwise, "a" feature refers to one or more of that feature.
Although the present invention has been described by way of preferred embodiments thereof, it should be understood that numerous other modifications and variations could be made thereto without departing from the spirit of the invention and the claims.
Claims (9)
1. A multimode ultra high speed digital subscriber line transceiver device comprising:
a transmitter including a modulator, an inverse fast fourier transformer, a transmission filter, an up-sampler, and a digital-to-analog converter, which are connected in series in this order; wherein the up-sampler comprises an interpolator configured to adjust a sampling rate by a multiplier for the up-sampler to provide a first oversampling rate for a first DSL mode and to adjust the sampling rate by another multiplier for the up-sampler to provide a second oversampling rate for a second DSL mode, wherein the first DSL mode is different from the second DSL mode and the first oversampling rate is different from the second oversampling rate;
a receiving device including an analog-to-digital converter, a down-sampler, a receiving filter, a fast fourier transformer, and a frequency equalizer, which are connected in series in order; and
an analog front end includes a hybrid circuit that is connected between the digital-to-analog converter of the transmitting device and the analog-to-digital converter of the receiving device, and further connected to an external line.
2. A multimode ultra high speed digital subscriber line transceiver device as defined in claim 1, wherein the external line is a twisted pair.
3. A multimode ultra high speed digital subscriber line transceiver device as claimed in claim 1, wherein the digital to analog converter has a fixed sample rate.
4. A multimode very high speed digital subscriber line transceiver device as defined in claim 1, wherein the up-sampler comprises one or more stages of up-sampling circuits, each stage of up-sampling circuits further comprising an up-sampling low pass filter, and the sampling rate of each stage of up-sampling circuits is independently adjusted by respective multipliers of respective interpolators.
5. A multimode ultra high speed digital subscriber line transceiver device as defined in claim 1, wherein the up-sampler comprises one or more stages of up-sampling circuits, and each stage of up-sampling circuit further comprises an integral differential modulation module and a dynamic element matching module, which are connected in series with the interpolator.
6. A multimode very high speed digital subscriber line transceiver apparatus as claimed in claim 1 wherein said down-sampler comprises one or more stages of down-sampling circuits, each stage of down-sampling circuits comprising a decimator and a down-sampling low pass filter, said decimator being configured to adjust another sampling rate by a respective multiplier for said down-sampler, and the sampling rate of each stage of down-sampling circuits being independently adjusted by the respective multiplier of the respective decimator.
7. The multimode ultra high speed digital subscriber line transceiver apparatus of claim 1, wherein the analog front end mixing circuit comprises an analog echo canceller configured to switch with different modes.
8. A method of implementing a multimode ultra high speed digital subscriber line transceiver device as claimed in claim 1, comprising:
step S1: performing a handshake procedure by the multimode ultra-high speed digital subscriber line transceiver device to exchange initial data; wherein the multimode ultra-high speed digital subscriber line transceiver device uses a predetermined sampling rate and a predetermined bandwidth;
step S2: determining a digital subscriber line mode, a corresponding agreed-upon sampling rate and an agreed-upon bandwidth of the multimode ultra-high speed digital subscriber line transceiver device based on the initial data obtained by the handshake procedure, and declaring the handshake procedure to be ended; and
step S3: at least one up-sampling parameter of an up-sampling circuit and/or a down-sampling parameter of a down-sampling circuit of the multimode ultra-high speed digital subscriber line transceiver device is set according to the agreed sampling rate and the agreed bandwidth.
9. The method of claim 8, further comprising the step of S4: the performance of an analog echo canceller of the multimode ultra-high speed digital subscriber line transceiver apparatus is maximized.
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| US20030063659A1 (en) * | 2001-10-03 | 2003-04-03 | Antti Kaltiainen | Method and apparatus for adjusting digital filters in a DSL modem |
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